2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
12 static s32 igc_wait_autoneg(struct igc_hw *hw);
15 * igc_init_phy_ops_generic - Initialize PHY function pointers
16 * @hw: pointer to the HW structure
18 * Setups up the function pointers to no-op functions
20 void igc_init_phy_ops_generic(struct igc_hw *hw)
22 struct igc_phy_info *phy = &hw->phy;
23 DEBUGFUNC("igc_init_phy_ops_generic");
25 /* Initialize function pointers */
26 phy->ops.init_params = igc_null_ops_generic;
27 phy->ops.acquire = igc_null_ops_generic;
28 phy->ops.check_reset_block = igc_null_ops_generic;
29 phy->ops.commit = igc_null_ops_generic;
30 phy->ops.force_speed_duplex = igc_null_ops_generic;
31 phy->ops.get_info = igc_null_ops_generic;
32 phy->ops.set_page = igc_null_set_page;
33 phy->ops.read_reg = igc_null_read_reg;
34 phy->ops.read_reg_locked = igc_null_read_reg;
35 phy->ops.read_reg_page = igc_null_read_reg;
36 phy->ops.release = igc_null_phy_generic;
37 phy->ops.reset = igc_null_ops_generic;
38 phy->ops.set_d0_lplu_state = igc_null_lplu_state;
39 phy->ops.set_d3_lplu_state = igc_null_lplu_state;
40 phy->ops.write_reg = igc_null_write_reg;
41 phy->ops.write_reg_locked = igc_null_write_reg;
42 phy->ops.write_reg_page = igc_null_write_reg;
43 phy->ops.power_up = igc_null_phy_generic;
44 phy->ops.power_down = igc_null_phy_generic;
48 * igc_null_set_page - No-op function, return 0
49 * @hw: pointer to the HW structure
50 * @data: dummy variable
52 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw,
53 u16 IGC_UNUSEDARG data)
55 DEBUGFUNC("igc_null_set_page");
60 * igc_null_read_reg - No-op function, return 0
61 * @hw: pointer to the HW structure
62 * @offset: dummy variable
63 * @data: dummy variable
65 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw,
66 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG *data)
68 DEBUGFUNC("igc_null_read_reg");
73 * igc_null_phy_generic - No-op function, return void
74 * @hw: pointer to the HW structure
76 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw)
78 DEBUGFUNC("igc_null_phy_generic");
83 * igc_null_lplu_state - No-op function, return 0
84 * @hw: pointer to the HW structure
85 * @active: dummy variable
87 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw,
88 bool IGC_UNUSEDARG active)
90 DEBUGFUNC("igc_null_lplu_state");
95 * igc_null_write_reg - No-op function, return 0
96 * @hw: pointer to the HW structure
97 * @offset: dummy variable
98 * @data: dummy variable
100 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw,
101 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)
103 DEBUGFUNC("igc_null_write_reg");
108 * igc_check_reset_block_generic - Check if PHY reset is blocked
109 * @hw: pointer to the HW structure
111 * Read the PHY management control register and check whether a PHY reset
112 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise
113 * return IGC_BLK_PHY_RESET (12).
115 s32 igc_check_reset_block_generic(struct igc_hw *hw)
119 DEBUGFUNC("igc_check_reset_block");
121 manc = IGC_READ_REG(hw, IGC_MANC);
123 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
124 IGC_BLK_PHY_RESET : IGC_SUCCESS;
128 * igc_get_phy_id - Retrieve the PHY ID and revision
129 * @hw: pointer to the HW structure
131 * Reads the PHY registers and stores the PHY ID and possibly the PHY
132 * revision in the hardware structure.
134 s32 igc_get_phy_id(struct igc_hw *hw)
136 struct igc_phy_info *phy = &hw->phy;
137 s32 ret_val = IGC_SUCCESS;
140 DEBUGFUNC("igc_get_phy_id");
142 if (!phy->ops.read_reg)
145 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
149 phy->id = (u32)(phy_id << 16);
151 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
155 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
156 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
163 * igc_read_phy_reg_mdic - Read MDI control register
164 * @hw: pointer to the HW structure
165 * @offset: register offset to be read
166 * @data: pointer to the read data
168 * Reads the MDI control register in the PHY at offset and stores the
169 * information read to data.
171 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
173 struct igc_phy_info *phy = &hw->phy;
176 DEBUGFUNC("igc_read_phy_reg_mdic");
178 if (offset > MAX_PHY_REG_ADDRESS) {
179 DEBUGOUT1("PHY Address %d is out of range\n", offset);
180 return -IGC_ERR_PARAM;
183 /* Set up Op-code, Phy Address, and register offset in the MDI
184 * Control register. The MAC will take care of interfacing with the
185 * PHY to retrieve the desired data.
187 mdic = ((offset << IGC_MDIC_REG_SHIFT) |
188 (phy->addr << IGC_MDIC_PHY_SHIFT) |
191 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
193 /* Poll the ready bit to see if the MDI read completed
194 * Increasing the time out as testing showed failures with
197 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
199 mdic = IGC_READ_REG(hw, IGC_MDIC);
200 if (mdic & IGC_MDIC_READY)
203 if (!(mdic & IGC_MDIC_READY)) {
204 DEBUGOUT("MDI Read did not complete\n");
207 if (mdic & IGC_MDIC_ERROR) {
208 DEBUGOUT("MDI Error\n");
211 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
212 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
214 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
223 * igc_write_phy_reg_mdic - Write MDI control register
224 * @hw: pointer to the HW structure
225 * @offset: register offset to write to
226 * @data: data to write to register at offset
228 * Writes data to MDI control register in the PHY at offset.
230 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
232 struct igc_phy_info *phy = &hw->phy;
235 DEBUGFUNC("igc_write_phy_reg_mdic");
237 if (offset > MAX_PHY_REG_ADDRESS) {
238 DEBUGOUT1("PHY Address %d is out of range\n", offset);
239 return -IGC_ERR_PARAM;
242 /* Set up Op-code, Phy Address, and register offset in the MDI
243 * Control register. The MAC will take care of interfacing with the
244 * PHY to retrieve the desired data.
246 mdic = (((u32)data) |
247 (offset << IGC_MDIC_REG_SHIFT) |
248 (phy->addr << IGC_MDIC_PHY_SHIFT) |
249 (IGC_MDIC_OP_WRITE));
251 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
253 /* Poll the ready bit to see if the MDI read completed
254 * Increasing the time out as testing showed failures with
257 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
259 mdic = IGC_READ_REG(hw, IGC_MDIC);
260 if (mdic & IGC_MDIC_READY)
263 if (!(mdic & IGC_MDIC_READY)) {
264 DEBUGOUT("MDI Write did not complete\n");
267 if (mdic & IGC_MDIC_ERROR) {
268 DEBUGOUT("MDI Error\n");
271 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
272 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
274 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
282 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
283 * @hw: pointer to the HW structure
285 * Reads the MII auto-neg advertisement register and/or the 1000T control
286 * register and if the PHY is already setup for auto-negotiation, then
287 * return successful. Otherwise, setup advertisement and flow control to
288 * the appropriate values for the wanted auto-negotiation.
290 static s32 igc_phy_setup_autoneg(struct igc_hw *hw)
292 struct igc_phy_info *phy = &hw->phy;
294 u16 mii_autoneg_adv_reg;
295 u16 mii_1000t_ctrl_reg = 0;
296 u16 aneg_multigbt_an_ctrl = 0;
298 DEBUGFUNC("igc_phy_setup_autoneg");
300 phy->autoneg_advertised &= phy->autoneg_mask;
302 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
303 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
307 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
308 /* Read the MII 1000Base-T Control Register (Address 9). */
309 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
310 &mii_1000t_ctrl_reg);
315 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
316 hw->phy.id == I225_I_PHY_ID) {
317 /* Read the MULTI GBT AN Control Register - reg 7.32 */
318 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
320 ANEG_MULTIGBT_AN_CTRL,
321 &aneg_multigbt_an_ctrl);
327 /* Need to parse both autoneg_advertised and fc and set up
328 * the appropriate PHY registers. First we will parse for
329 * autoneg_advertised software override. Since we can advertise
330 * a plethora of combinations, we need to check each bit
334 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
335 * Advertisement Register (Address 4) and the 1000 mb speed bits in
336 * the 1000Base-T Control Register (Address 9).
338 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
339 NWAY_AR_100TX_HD_CAPS |
340 NWAY_AR_10T_FD_CAPS |
341 NWAY_AR_10T_HD_CAPS);
342 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
344 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
346 /* Do we want to advertise 10 Mb Half Duplex? */
347 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
348 DEBUGOUT("Advertise 10mb Half duplex\n");
349 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
352 /* Do we want to advertise 10 Mb Full Duplex? */
353 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
354 DEBUGOUT("Advertise 10mb Full duplex\n");
355 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
358 /* Do we want to advertise 100 Mb Half Duplex? */
359 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
360 DEBUGOUT("Advertise 100mb Half duplex\n");
361 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
364 /* Do we want to advertise 100 Mb Full Duplex? */
365 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
366 DEBUGOUT("Advertise 100mb Full duplex\n");
367 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
370 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
371 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
372 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
374 /* Do we want to advertise 1000 Mb Full Duplex? */
375 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
376 DEBUGOUT("Advertise 1000mb Full duplex\n");
377 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
380 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */
381 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
382 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n");
384 /* Do we want to advertise 2500 Mb Full Duplex? */
385 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
386 DEBUGOUT("Advertise 2500mb Full duplex\n");
387 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
389 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
392 /* Check for a software override of the flow control settings, and
393 * setup the PHY advertisement registers accordingly. If
394 * auto-negotiation is enabled, then software will have to set the
395 * "PAUSE" bits to the correct value in the Auto-Negotiation
396 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
399 * The possible values of the "fc" parameter are:
400 * 0: Flow control is completely disabled
401 * 1: Rx flow control is enabled (we can receive pause frames
402 * but not send pause frames).
403 * 2: Tx flow control is enabled (we can send pause frames
404 * but we do not support receiving pause frames).
405 * 3: Both Rx and Tx flow control (symmetric) are enabled.
406 * other: No software override. The flow control configuration
407 * in the EEPROM is used.
409 switch (hw->fc.current_mode) {
411 /* Flow control (Rx & Tx) is completely disabled by a
412 * software over-ride.
414 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
416 case igc_fc_rx_pause:
417 /* Rx Flow control is enabled, and Tx Flow control is
418 * disabled, by a software over-ride.
420 * Since there really isn't a way to advertise that we are
421 * capable of Rx Pause ONLY, we will advertise that we
422 * support both symmetric and asymmetric Rx PAUSE. Later
423 * (in igc_config_fc_after_link_up) we will disable the
424 * hw's ability to send PAUSE frames.
426 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
428 case igc_fc_tx_pause:
429 /* Tx Flow control is enabled, and Rx Flow control is
430 * disabled, by a software over-ride.
432 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
433 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
436 /* Flow control (both Rx and Tx) is enabled by a software
439 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
442 DEBUGOUT("Flow control param set incorrectly\n");
443 return -IGC_ERR_CONFIG;
446 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
450 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
452 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
453 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
456 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
457 hw->phy.id == I225_I_PHY_ID)
458 ret_val = phy->ops.write_reg(hw,
459 (STANDARD_AN_REG_MASK <<
461 ANEG_MULTIGBT_AN_CTRL,
462 aneg_multigbt_an_ctrl);
468 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
469 * @hw: pointer to the HW structure
471 * Performs initial bounds checking on autoneg advertisement parameter, then
472 * configure to advertise the full capability. Setup the PHY to autoneg
473 * and restart the negotiation process between the link partner. If
474 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
476 static s32 igc_copper_link_autoneg(struct igc_hw *hw)
478 struct igc_phy_info *phy = &hw->phy;
482 DEBUGFUNC("igc_copper_link_autoneg");
484 /* Perform some bounds checking on the autoneg advertisement
487 phy->autoneg_advertised &= phy->autoneg_mask;
489 /* If autoneg_advertised is zero, we assume it was not defaulted
490 * by the calling code so we set to advertise full capability.
492 if (!phy->autoneg_advertised)
493 phy->autoneg_advertised = phy->autoneg_mask;
495 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
496 ret_val = igc_phy_setup_autoneg(hw);
498 DEBUGOUT("Error Setting up Auto-Negotiation\n");
501 DEBUGOUT("Restarting Auto-Neg\n");
503 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
504 * the Auto Neg Restart bit in the PHY control register.
506 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
510 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
511 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
515 /* Does the user want to wait for Auto-Neg to complete here, or
516 * check at a later time (for example, callback routine).
518 if (phy->autoneg_wait_to_complete) {
519 ret_val = igc_wait_autoneg(hw);
521 DEBUGOUT("Error while waiting for autoneg to complete\n");
526 hw->mac.get_link_status = true;
532 * igc_setup_copper_link_generic - Configure copper link settings
533 * @hw: pointer to the HW structure
535 * Calls the appropriate function to configure the link for auto-neg or forced
536 * speed and duplex. Then we check for link, once link is established calls
537 * to configure collision distance and flow control are called. If link is
538 * not established, we return -IGC_ERR_PHY (-2).
540 s32 igc_setup_copper_link_generic(struct igc_hw *hw)
545 DEBUGFUNC("igc_setup_copper_link_generic");
547 if (hw->mac.autoneg) {
548 /* Setup autoneg and flow control advertisement and perform
551 ret_val = igc_copper_link_autoneg(hw);
555 /* PHY will be set to 10H, 10F, 100H or 100F
556 * depending on user settings.
558 DEBUGOUT("Forcing Speed and Duplex\n");
559 ret_val = hw->phy.ops.force_speed_duplex(hw);
561 DEBUGOUT("Error Forcing Speed and Duplex\n");
566 /* Check link status. Wait up to 100 microseconds for link to become
569 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
575 DEBUGOUT("Valid link established!!!\n");
576 hw->mac.ops.config_collision_dist(hw);
577 ret_val = igc_config_fc_after_link_up_generic(hw);
579 DEBUGOUT("Unable to establish link!!!\n");
586 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
587 * @hw: pointer to the HW structure
588 * @phy_ctrl: pointer to current value of PHY_CONTROL
590 * Forces speed and duplex on the PHY by doing the following: disable flow
591 * control, force speed/duplex on the MAC, disable auto speed detection,
592 * disable auto-negotiation, configure duplex, configure speed, configure
593 * the collision distance, write configuration to CTRL register. The
594 * caller must write to the PHY_CONTROL register for these settings to
597 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)
599 struct igc_mac_info *mac = &hw->mac;
602 DEBUGFUNC("igc_phy_force_speed_duplex_setup");
604 /* Turn off flow control when forcing speed/duplex */
605 hw->fc.current_mode = igc_fc_none;
607 /* Force speed/duplex on the mac */
608 ctrl = IGC_READ_REG(hw, IGC_CTRL);
609 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
610 ctrl &= ~IGC_CTRL_SPD_SEL;
612 /* Disable Auto Speed Detection */
613 ctrl &= ~IGC_CTRL_ASDE;
615 /* Disable autoneg on the phy */
616 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
618 /* Forcing Full or Half Duplex? */
619 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {
620 ctrl &= ~IGC_CTRL_FD;
621 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
622 DEBUGOUT("Half Duplex\n");
625 *phy_ctrl |= MII_CR_FULL_DUPLEX;
626 DEBUGOUT("Full Duplex\n");
629 /* Forcing 10mb or 100mb? */
630 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {
631 ctrl |= IGC_CTRL_SPD_100;
632 *phy_ctrl |= MII_CR_SPEED_100;
633 *phy_ctrl &= ~MII_CR_SPEED_1000;
634 DEBUGOUT("Forcing 100mb\n");
636 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);
637 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
638 DEBUGOUT("Forcing 10mb\n");
641 hw->mac.ops.config_collision_dist(hw);
643 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
647 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3
648 * @hw: pointer to the HW structure
649 * @active: boolean used to enable/disable lplu
651 * Success returns 0, Failure returns 1
653 * The low power link up (lplu) state is set to the power management level D3
654 * and SmartSpeed is disabled when active is true, else clear lplu for D3
655 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
656 * is used during Dx states where the power conservation is most important.
657 * During driver activity, SmartSpeed should be enabled so performance is
660 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)
662 struct igc_phy_info *phy = &hw->phy;
666 DEBUGFUNC("igc_set_d3_lplu_state_generic");
668 if (!hw->phy.ops.read_reg)
671 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
676 data &= ~IGP02IGC_PM_D3_LPLU;
677 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
681 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
682 * during Dx states where the power conservation is most
683 * important. During driver activity we should enable
684 * SmartSpeed, so performance is maintained.
686 if (phy->smart_speed == igc_smart_speed_on) {
687 ret_val = phy->ops.read_reg(hw,
688 IGP01IGC_PHY_PORT_CONFIG,
693 data |= IGP01IGC_PSCFR_SMART_SPEED;
694 ret_val = phy->ops.write_reg(hw,
695 IGP01IGC_PHY_PORT_CONFIG,
699 } else if (phy->smart_speed == igc_smart_speed_off) {
700 ret_val = phy->ops.read_reg(hw,
701 IGP01IGC_PHY_PORT_CONFIG,
706 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
707 ret_val = phy->ops.write_reg(hw,
708 IGP01IGC_PHY_PORT_CONFIG,
713 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
714 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
715 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
716 data |= IGP02IGC_PM_D3_LPLU;
717 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
722 /* When LPLU is enabled, we should disable SmartSpeed */
723 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
728 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
729 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
737 * igc_check_downshift_generic - Checks whether a downshift in speed occurred
738 * @hw: pointer to the HW structure
740 * Success returns 0, Failure returns 1
742 * A downshift is detected by querying the PHY link health.
744 s32 igc_check_downshift_generic(struct igc_hw *hw)
746 struct igc_phy_info *phy = &hw->phy;
749 DEBUGFUNC("igc_check_downshift_generic");
754 /* speed downshift not supported */
755 phy->speed_downgraded = false;
763 * igc_wait_autoneg - Wait for auto-neg completion
764 * @hw: pointer to the HW structure
766 * Waits for auto-negotiation to complete or for the auto-negotiation time
767 * limit to expire, which ever happens first.
769 static s32 igc_wait_autoneg(struct igc_hw *hw)
771 s32 ret_val = IGC_SUCCESS;
774 DEBUGFUNC("igc_wait_autoneg");
776 if (!hw->phy.ops.read_reg)
779 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
780 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
781 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
784 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
787 if (phy_status & MII_SR_AUTONEG_COMPLETE)
792 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
799 * igc_phy_has_link_generic - Polls PHY for link
800 * @hw: pointer to the HW structure
801 * @iterations: number of times to poll for link
802 * @usec_interval: delay between polling attempts
803 * @success: pointer to whether polling was successful or not
805 * Polls the PHY status register for link, 'iterations' number of times.
807 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
808 u32 usec_interval, bool *success)
810 s32 ret_val = IGC_SUCCESS;
813 DEBUGFUNC("igc_phy_has_link_generic");
815 if (!hw->phy.ops.read_reg)
818 for (i = 0; i < iterations; i++) {
819 /* Some PHYs require the PHY_STATUS register to be read
820 * twice due to the link bit being sticky. No harm doing
821 * it across the board.
823 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
825 /* If the first read fails, another entity may have
826 * ownership of the resources, wait and try again to
827 * see if they have relinquished the resources yet.
829 if (usec_interval >= 1000)
830 msec_delay(usec_interval/1000);
832 usec_delay(usec_interval);
834 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
837 if (phy_status & MII_SR_LINK_STATUS)
839 if (usec_interval >= 1000)
840 msec_delay(usec_interval/1000);
842 usec_delay(usec_interval);
845 *success = (i < iterations);
851 * igc_phy_sw_reset_generic - PHY software reset
852 * @hw: pointer to the HW structure
854 * Does a software reset of the PHY by reading the PHY control register and
855 * setting/write the control register reset bit to the PHY.
857 s32 igc_phy_sw_reset_generic(struct igc_hw *hw)
862 DEBUGFUNC("igc_phy_sw_reset_generic");
864 if (!hw->phy.ops.read_reg)
867 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
871 phy_ctrl |= MII_CR_RESET;
872 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
882 * igc_phy_hw_reset_generic - PHY hardware reset
883 * @hw: pointer to the HW structure
885 * Verify the reset block is not blocking us from resetting. Acquire
886 * semaphore (if necessary) and read/set/write the device control reset
887 * bit in the PHY. Wait the appropriate delay time for the device to
888 * reset and release the semaphore (if necessary).
890 s32 igc_phy_hw_reset_generic(struct igc_hw *hw)
892 struct igc_phy_info *phy = &hw->phy;
894 u32 ctrl, timeout = 10000, phpm = 0;
896 DEBUGFUNC("igc_phy_hw_reset_generic");
898 if (phy->ops.check_reset_block) {
899 ret_val = phy->ops.check_reset_block(hw);
904 ret_val = phy->ops.acquire(hw);
908 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
910 ctrl = IGC_READ_REG(hw, IGC_CTRL);
911 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
914 usec_delay(phy->reset_delay_us);
916 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
922 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
925 } while (!(phpm & IGC_I225_PHPM_RST_COMPL) && timeout);
928 DEBUGOUT("Timeout expired after a phy reset\n");
930 phy->ops.release(hw);
936 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
937 * @hw: pointer to the HW structure
939 * In the case of a PHY power down to save power, or to turn off link during a
940 * driver unload, or wake on lan is not enabled, restore the link to previous
943 void igc_power_up_phy_copper(struct igc_hw *hw)
947 /* The PHY will retain its settings across a power down/up cycle */
948 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
949 mii_reg &= ~MII_CR_POWER_DOWN;
950 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
955 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
956 * @hw: pointer to the HW structure
958 * In the case of a PHY power down to save power, or to turn off link during a
959 * driver unload, or wake on lan is not enabled, restore the link to previous
962 void igc_power_down_phy_copper(struct igc_hw *hw)
966 /* The PHY will retain its settings across a power down/up cycle */
967 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
968 mii_reg |= MII_CR_POWER_DOWN;
969 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
973 * igc_write_phy_reg_gpy - Write GPY PHY register
974 * @hw: pointer to the HW structure
975 * @offset: register offset to write to
976 * @data: data to write at register offset
978 * Acquires semaphore, if necessary, then writes the data to PHY register
979 * at the offset. Release any acquired semaphores before exiting.
981 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
984 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
986 DEBUGFUNC("igc_write_phy_reg_gpy");
988 offset = offset & GPY_REG_MASK;
991 ret_val = hw->phy.ops.acquire(hw);
994 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
997 hw->phy.ops.release(hw);
999 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
1006 * igc_read_phy_reg_gpy - Read GPY PHY register
1007 * @hw: pointer to the HW structure
1008 * @offset: lower half is register offset to read to
1009 * upper half is MMD to use.
1010 * @data: data to read at register offset
1012 * Acquires semaphore, if necessary, then reads the data in the PHY register
1013 * at the offset. Release any acquired semaphores before exiting.
1015 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
1018 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
1020 DEBUGFUNC("igc_read_phy_reg_gpy");
1022 offset = offset & GPY_REG_MASK;
1025 ret_val = hw->phy.ops.acquire(hw);
1028 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
1031 hw->phy.ops.release(hw);
1033 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
1041 * __igc_access_xmdio_reg - Read/write XMDIO register
1042 * @hw: pointer to the HW structure
1043 * @address: XMDIO address to program
1044 * @dev_addr: device address to program
1045 * @data: pointer to value to read/write from/to the XMDIO address
1046 * @read: boolean flag to indicate read or write
1048 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
1049 u8 dev_addr, u16 *data, bool read)
1053 DEBUGFUNC("__igc_access_xmdio_reg");
1055 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
1059 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
1063 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
1069 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
1071 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
1075 /* Recalibrate the device back to 0 */
1076 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
1084 * igc_read_xmdio_reg - Read XMDIO register
1085 * @hw: pointer to the HW structure
1086 * @addr: XMDIO address to program
1087 * @dev_addr: device address to program
1088 * @data: value to be read from the EMI address
1090 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)
1092 DEBUGFUNC("igc_read_xmdio_reg");
1094 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
1098 * igc_write_xmdio_reg - Write XMDIO register
1099 * @hw: pointer to the HW structure
1100 * @addr: XMDIO address to program
1101 * @dev_addr: device address to program
1102 * @data: value to be written to the XMDIO address
1104 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)
1106 DEBUGFUNC("igc_write_xmdio_reg");
1108 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);