2 * Copyright (c) 2014-2015 Luiz Otavio O Souza <loos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Driver for Maxim DS3231[N] real-time clock/calendar.
34 #include "opt_platform.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/clock.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/sysctl.h>
44 #include <dev/iicbus/iicbus.h>
45 #include <dev/iicbus/iiconf.h>
47 #include <dev/ofw/openfirm.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/iicbus/ds3231reg.h>
55 #include "iicbus_if.h"
61 struct intr_config_hook enum_hook;
62 uint16_t sc_addr; /* DS3231 slave address. */
68 static void ds3231_start(void *);
71 ds3231_read1(device_t dev, uint8_t reg, uint8_t *data)
74 return (iicdev_readfrom(dev, reg, data, 1, IIC_INTRWAIT));
78 ds3231_write1(device_t dev, uint8_t reg, uint8_t data)
81 return (iicdev_writeto(dev, reg, &data, 1, IIC_INTRWAIT));
85 ds3231_ctrl_read(struct ds3231_softc *sc)
89 error = ds3231_read1(sc->sc_dev, DS3231_CONTROL, &sc->sc_ctrl);
91 device_printf(sc->sc_dev, "cannot read from RTC.\n");
98 ds3231_ctrl_write(struct ds3231_softc *sc)
103 /* Always enable the oscillator. Always disable both alarms. */
104 data = sc->sc_ctrl & ~DS3231_CTRL_MASK;
105 error = ds3231_write1(sc->sc_dev, DS3231_CONTROL, data);
107 device_printf(sc->sc_dev, "cannot write to RTC.\n");
113 ds3231_status_read(struct ds3231_softc *sc)
117 error = ds3231_read1(sc->sc_dev, DS3231_STATUS, &sc->sc_status);
119 device_printf(sc->sc_dev, "cannot read from RTC.\n");
127 ds3231_status_write(struct ds3231_softc *sc, int clear_a1, int clear_a2)
132 data = sc->sc_status;
134 data |= DS3231_STATUS_A1F;
136 data |= DS3231_STATUS_A2F;
137 error = ds3231_write1(sc->sc_dev, DS3231_STATUS, data);
139 device_printf(sc->sc_dev, "cannot write to RTC.\n");
145 ds3231_temp_read(struct ds3231_softc *sc, int *temp)
151 error = iicdev_readfrom(sc->sc_dev, DS3231_TEMP, buf8, sizeof(buf8),
155 buf = (buf8[0] << 8) | (buf8[1] & 0xff);
157 if (buf & DS3231_NEG_BIT) {
158 buf = ~(buf & DS3231_TEMP_MASK) + 1;
161 *temp = ((int16_t)buf >> 8) * 10;
163 if (buf & DS3231_0250C)
165 if (buf & DS3231_0500C)
177 ds3231_temp_sysctl(SYSCTL_HANDLER_ARGS)
180 struct ds3231_softc *sc;
182 sc = (struct ds3231_softc *)arg1;
183 if (ds3231_temp_read(sc, &temp) != 0)
185 error = sysctl_handle_int(oidp, &temp, 0, req);
191 ds3231_conv_sysctl(SYSCTL_HANDLER_ARGS)
193 int error, conv, newc;
194 struct ds3231_softc *sc;
196 sc = (struct ds3231_softc *)arg1;
197 error = ds3231_ctrl_read(sc);
200 newc = conv = (sc->sc_ctrl & DS3231_CTRL_CONV) ? 1 : 0;
201 error = sysctl_handle_int(oidp, &newc, 0, req);
202 if (error != 0 || req->newptr == NULL)
204 if (conv == 0 && newc != 0) {
205 error = ds3231_status_read(sc);
208 if (sc->sc_status & DS3231_STATUS_BUSY)
210 sc->sc_ctrl |= DS3231_CTRL_CONV;
211 error = ds3231_ctrl_write(sc);
220 ds3231_bbsqw_sysctl(SYSCTL_HANDLER_ARGS)
222 int bbsqw, error, newb;
223 struct ds3231_softc *sc;
225 sc = (struct ds3231_softc *)arg1;
226 error = ds3231_ctrl_read(sc);
229 bbsqw = newb = (sc->sc_ctrl & DS3231_CTRL_BBSQW) ? 1 : 0;
230 error = sysctl_handle_int(oidp, &newb, 0, req);
231 if (error != 0 || req->newptr == NULL)
234 sc->sc_ctrl &= ~DS3231_CTRL_BBSQW;
236 sc->sc_ctrl |= DS3231_CTRL_BBSQW;
237 error = ds3231_ctrl_write(sc);
246 ds3231_sqw_freq_sysctl(SYSCTL_HANDLER_ARGS)
248 int ds3231_sqw_freq[] = { 1, 1024, 4096, 8192 };
249 int error, freq, i, newf, tmp;
250 struct ds3231_softc *sc;
252 sc = (struct ds3231_softc *)arg1;
253 error = ds3231_ctrl_read(sc);
256 tmp = (sc->sc_ctrl & DS3231_CTRL_RS_MASK) >> DS3231_CTRL_RS_SHIFT;
257 if (tmp >= nitems(ds3231_sqw_freq))
258 tmp = nitems(ds3231_sqw_freq) - 1;
259 freq = ds3231_sqw_freq[tmp];
260 error = sysctl_handle_int(oidp, &freq, 0, req);
261 if (error != 0 || req->newptr == NULL)
263 if (freq != ds3231_sqw_freq[tmp]) {
265 for (i = 0; i < nitems(ds3231_sqw_freq); i++)
266 if (freq >= ds3231_sqw_freq[i])
268 sc->sc_ctrl &= ~DS3231_CTRL_RS_MASK;
269 sc->sc_ctrl |= newf << DS3231_CTRL_RS_SHIFT;
270 error = ds3231_ctrl_write(sc);
279 ds3231_str_sqw_mode(char *buf)
285 if ((len > 2 && strncasecmp("interrupt", buf, len) == 0) ||
286 (len > 2 && strncasecmp("int", buf, len) == 0)) {
288 } else if ((len > 2 && strncasecmp("square-wave", buf, len) == 0) ||
289 (len > 2 && strncasecmp("sqw", buf, len) == 0)) {
297 ds3231_sqw_mode_sysctl(SYSCTL_HANDLER_ARGS)
300 int error, mode, newm;
301 struct ds3231_softc *sc;
303 sc = (struct ds3231_softc *)arg1;
304 error = ds3231_ctrl_read(sc);
307 if (sc->sc_ctrl & DS3231_CTRL_INTCN) {
309 strlcpy(buf, "interrupt", sizeof(buf));
312 strlcpy(buf, "square-wave", sizeof(buf));
314 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
315 if (error != 0 || req->newptr == NULL)
317 newm = ds3231_str_sqw_mode(buf);
318 if (newm != -1 && mode != newm) {
319 sc->sc_ctrl &= ~DS3231_CTRL_INTCN;
321 sc->sc_ctrl |= DS3231_CTRL_INTCN;
322 error = ds3231_ctrl_write(sc);
331 ds3231_en32khz_sysctl(SYSCTL_HANDLER_ARGS)
333 int error, en32khz, tmp;
334 struct ds3231_softc *sc;
336 sc = (struct ds3231_softc *)arg1;
337 error = ds3231_status_read(sc);
340 tmp = en32khz = (sc->sc_status & DS3231_STATUS_EN32KHZ) ? 1 : 0;
341 error = sysctl_handle_int(oidp, &en32khz, 0, req);
342 if (error != 0 || req->newptr == NULL)
344 if (en32khz != tmp) {
345 sc->sc_status &= ~DS3231_STATUS_EN32KHZ;
347 sc->sc_status |= DS3231_STATUS_EN32KHZ;
348 error = ds3231_status_write(sc, 0, 0);
357 ds3231_probe(device_t dev)
361 if (!ofw_bus_status_okay(dev))
363 if (!ofw_bus_is_compatible(dev, "maxim,ds3231"))
366 device_set_desc(dev, "Maxim DS3231 RTC");
368 return (BUS_PROBE_DEFAULT);
372 ds3231_attach(device_t dev)
374 struct ds3231_softc *sc;
376 sc = device_get_softc(dev);
378 sc->sc_addr = iicbus_get_addr(dev);
381 sc->enum_hook.ich_func = ds3231_start;
382 sc->enum_hook.ich_arg = dev;
385 * We have to wait until interrupts are enabled. Usually I2C read
386 * and write only works when the interrupts are available.
388 if (config_intrhook_establish(&sc->enum_hook) != 0)
395 ds3231_detach(device_t dev)
398 clock_unregister(dev);
403 ds3231_start(void *xdev)
406 struct ds3231_softc *sc;
407 struct sysctl_ctx_list *ctx;
408 struct sysctl_oid *tree_node;
409 struct sysctl_oid_list *tree;
411 dev = (device_t)xdev;
412 sc = device_get_softc(dev);
413 ctx = device_get_sysctl_ctx(dev);
414 tree_node = device_get_sysctl_tree(dev);
415 tree = SYSCTL_CHILDREN(tree_node);
417 config_intrhook_disestablish(&sc->enum_hook);
418 if (ds3231_ctrl_read(sc) != 0)
420 if (ds3231_status_read(sc) != 0)
423 * Warn if the clock stopped, but don't restart it until the first
424 * clock_settime() call.
426 if (sc->sc_status & DS3231_STATUS_OSF) {
427 device_printf(sc->sc_dev,
428 "WARNING: RTC clock stopped, check the battery.\n");
432 * Ack any pending alarm interrupts and clear the EOSC bit to ensure the
433 * clock runs even when on battery power. Do not give up if these
434 * writes fail, because a factory-fresh chip is in a special mode that
435 * disables much of the chip to save battery power, and the only thing
436 * that gets it out of that mode is writing to the time registers. In
437 * these pristine chips, the EOSC and alarm bits are zero already, so
438 * the first valid write of time will get everything running properly.
440 ds3231_status_write(sc, 1, 1);
441 ds3231_ctrl_write(sc);
444 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "temperature",
445 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
446 ds3231_temp_sysctl, "IK", "Current temperature");
447 /* Configuration parameters. */
448 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "temp_conv",
449 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
450 ds3231_conv_sysctl, "IU",
451 "DS3231 start a new temperature converstion");
452 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "bbsqw",
453 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
454 ds3231_bbsqw_sysctl, "IU",
455 "DS3231 battery-backed square-wave output enable");
456 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "sqw_freq",
457 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
458 ds3231_sqw_freq_sysctl, "IU",
459 "DS3231 square-wave output frequency");
460 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "sqw_mode",
461 CTLFLAG_RW | CTLTYPE_STRING | CTLFLAG_MPSAFE, sc, 0,
462 ds3231_sqw_mode_sysctl, "A", "DS3231 SQW output mode control");
463 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "32khz_enable",
464 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
465 ds3231_en32khz_sysctl, "IU", "DS3231 enable the 32kHz output");
468 * Register as a clock with 1 second resolution. Schedule the
469 * clock_settime() method to be called just after top-of-second;
470 * resetting the time resets top-of-second in the hardware.
472 clock_register_flags(dev, 1000000, CLOCKF_SETTIME_NO_ADJ);
473 clock_schedule(dev, 1);
477 ds3231_gettime(device_t dev, struct timespec *ts)
480 struct bcd_clocktime bct;
481 struct ds3231_softc *sc;
482 uint8_t data[7], hourmask;
484 sc = device_get_softc(dev);
486 /* If the clock halted, we don't have good data. */
487 if ((error = ds3231_status_read(sc)) != 0) {
488 device_printf(dev, "cannot read from RTC.\n");
491 if (sc->sc_status & DS3231_STATUS_OSF)
494 error = iicdev_readfrom(sc->sc_dev, DS3231_SECS, data, sizeof(data),
497 device_printf(dev, "cannot read from RTC.\n");
501 /* If chip is in AM/PM mode remember that. */
502 if (data[DS3231_HOUR] & DS3231_HOUR_USE_AMPM) {
503 sc->sc_use_ampm = true;
504 hourmask = DS3231_HOUR_MASK_12HR;
506 hourmask = DS3231_HOUR_MASK_24HR;
509 bct.sec = data[DS3231_SECS] & DS3231_SECS_MASK;
510 bct.min = data[DS3231_MINS] & DS3231_MINS_MASK;
511 bct.hour = data[DS3231_HOUR] & hourmask;
512 bct.day = data[DS3231_DATE] & DS3231_DATE_MASK;
513 bct.mon = data[DS3231_MONTH] & DS3231_MONTH_MASK;
514 bct.year = data[DS3231_YEAR] & DS3231_YEAR_MASK;
515 bct.ispm = data[DS3231_HOUR] & DS3231_HOUR_IS_PM;
518 * If the century flag has toggled since we last saw it, there has been
519 * a century rollover. If this is the first time we're seeing it,
520 * remember the state so we can preserve its polarity on writes.
522 c = (data[DS3231_MONTH] & DS3231_C_MASK) ? 1 : 0;
523 if (sc->sc_last_c == -1)
525 else if (c != sc->sc_last_c) {
526 sc->sc_year0 += 0x100;
529 bct.year |= sc->sc_year0;
531 clock_dbgprint_bcd(sc->sc_dev, CLOCK_DBG_READ, &bct);
532 return (clock_bcd_to_ts(&bct, ts, sc->sc_use_ampm));
536 ds3231_settime(device_t dev, struct timespec *ts)
539 struct bcd_clocktime bct;
540 struct ds3231_softc *sc;
544 sc = device_get_softc(dev);
547 * We request a timespec with no resolution-adjustment. That also
548 * disables utc adjustment, so apply that ourselves.
550 ts->tv_sec -= utc_offset();
551 clock_ts_to_bcd(ts, &bct, sc->sc_use_ampm);
552 clock_dbgprint_bcd(sc->sc_dev, CLOCK_DBG_WRITE, &bct);
554 /* If the chip is in AM/PM mode, adjust hour and set flags as needed. */
555 if (sc->sc_use_ampm) {
556 pmflags = DS3231_HOUR_USE_AMPM;
558 pmflags |= DS3231_HOUR_IS_PM;
562 data[DS3231_SECS] = bct.sec;
563 data[DS3231_MINS] = bct.min;
564 data[DS3231_HOUR] = bct.hour | pmflags;
565 data[DS3231_DATE] = bct.day;
566 data[DS3231_WEEKDAY] = bct.dow + 1;
567 data[DS3231_MONTH] = bct.mon;
568 data[DS3231_YEAR] = bct.year & 0xff;
570 data[DS3231_MONTH] |= DS3231_C_MASK;
572 /* Write the time back to RTC. */
573 error = iicdev_writeto(dev, DS3231_SECS, data, sizeof(data),
576 device_printf(dev, "cannot write to RTC.\n");
581 * Unlike most hardware, the osc-was-stopped bit does not clear itself
582 * after setting the time, it has to be manually written to zero.
584 if (sc->sc_status & DS3231_STATUS_OSF) {
585 if ((error = ds3231_status_read(sc)) != 0) {
586 device_printf(dev, "cannot read from RTC.\n");
589 sc->sc_status &= ~DS3231_STATUS_OSF;
590 if ((error = ds3231_status_write(sc, 0, 0)) != 0) {
591 device_printf(dev, "cannot write to RTC.\n");
599 static device_method_t ds3231_methods[] = {
600 DEVMETHOD(device_probe, ds3231_probe),
601 DEVMETHOD(device_attach, ds3231_attach),
602 DEVMETHOD(device_detach, ds3231_detach),
604 DEVMETHOD(clock_gettime, ds3231_gettime),
605 DEVMETHOD(clock_settime, ds3231_settime),
610 static driver_t ds3231_driver = {
613 sizeof(struct ds3231_softc),
616 static devclass_t ds3231_devclass;
618 DRIVER_MODULE(ds3231, iicbus, ds3231_driver, ds3231_devclass, NULL, NULL);
619 MODULE_VERSION(ds3231, 1);
620 MODULE_DEPEND(ds3231, iicbus, 1, 1, 1);