2 * Copyright (c) 2017 Ian Lepore. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
29 * Driver for ISL12xx family i2c realtime clocks:
30 * - ISL1209 = 2B sram, tamper/event timestamp
31 * - ISL1218 = 8B sram, DS13xx pin compatible (but not software compatible)
32 * - ISL1219 = 2B sram, tamper/event timestamp
33 * - ISL1220 = 8B sram, separate Fout
34 * - ISL1221 = 2B sram, separate Fout, tamper/event timestamp
36 * This driver supports only the basic RTC functionality in all these chips.
39 #include "opt_platform.h"
41 #include <sys/param.h>
42 #include <sys/systm.h>
44 #include <sys/clock.h>
45 #include <sys/kernel.h>
47 #include <sys/module.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
55 #include <dev/iicbus/iiconf.h>
56 #include <dev/iicbus/iicbus.h>
59 #include "iicbus_if.h"
62 * All register and bit names as found in the datasheet. When a bit name ends
63 * in 'B' that stands for "bar" and it is an active-low signal; something named
64 * "EVENB" implies 1=event-disable, 0=event-enable.
67 #define ISL12XX_SC_REG 0x00 /* RTC Seconds */
69 #define ISL12XX_SR_REG 0x07 /* Status */
70 #define ISL12XX_SR_ARST (1u << 7) /* Auto-reset on status read */
71 #define ISL12XX_SR_XTOSCB (1u << 5) /* Osc disable (use ext osc) */
72 #define ISL12XX_SR_WRTC (1u << 4) /* Write RTC enable */
73 #define ISL12XX_SR_EVT (1u << 3) /* Event occurred (w0c) */
74 #define ISL12XX_SR_ALM (1u << 2) /* Alarm occurred (w0c) */
75 #define ISL12XX_SR_BAT (1u << 1) /* Running on battery (w0c) */
76 #define ISL12XX_SR_RTCF (1u << 0) /* RTC fail (power loss) */
77 #define ISL12XX_SR_W0C_BITS (ISL12XX_SR_BAT | ISL12XX_SR_ALM | ISL12XX_SR_EVT)
79 #define ISL12XX_INT_REG 0x08 /* Interrupts */
80 #define ISL12XX_INT_IM (1u << 7) /* Alarm interrupt mode */
81 #define ISL12XX_INT_ALME (1u << 6) /* Alarm enable */
82 #define ISL12XX_INT_LPMODE (1u << 5) /* Low Power mode */
83 #define ISL12XX_INT_FOBATB (1u << 4) /* Fout/IRQ disabled on bat */
84 #define ISL12XX_INT_FO_SHIFT 0 /* Frequency output select */
85 #define ISL12XX_INT_FO_MASK 0x0f /* shift and mask. */
87 #define ISL12XX_EV_REG 0x09 /* Event */
88 #define ISL12XX_EV_EVIENB (1u << 7) /* Disable internal pullup */
89 #define ISL12XX_EV_EVBATB (1u << 6) /* Disable ev detect on bat */
90 #define ISL12XX_EV_RTCHLT (1u << 5) /* Halt RTC on event */
91 #define ISL12XX_EV_EVEN (1u << 4) /* Event detect enable */
92 #define ISL12XX_EV_EHYS_SHIFT 2 /* Event input hysteresis */
93 #define ISL12XX_EV_EHYS_MASK 0x03 /* selection; see datasheet */
94 #define ISL12XX_EV_ESMP_SHIFT 0 /* Event input sample rate */
95 #define ISL12XX_EV_ESMP_MASK 0x03 /* selection; see datasheet */
97 #define ISL12XX_ATR_REG 0x0a /* Analog trim (osc adjust) */
99 #define ISL12XX_DTR_REG 0x0b /* Digital trim (osc adjust) */
101 #define ISL12XX_SCA_REG 0x0c /* Alarm seconds */
103 #define ISL12XX_USR1_REG 0x12 /* User byte 1 */
105 #define ISL12XX_USR2_REG 0x13 /* User byte 2 */
107 #define ISL12XX_SCT_REG 0x14 /* Timestamp (event) seconds */
109 #define ISL12XX_24HR_FLAG (1u << 7) /* Hours register 24-hr mode */
110 #define ISL12XX_PM_FLAG (1u << 5) /* Hours register PM flag */
111 #define ISL12xx_12HR_MASK 0x1f /* Hours mask in AM/PM mode */
112 #define ISL12xx_24HR_MASK 0x3f /* Hours mask in 24-hr mode */
115 * A struct laid out in the same order as the time registers in the chip.
118 uint8_t sec, min, hour, day, month, year;
121 struct isl12xx_softc {
124 struct intr_config_hook
130 static struct ofw_compat_data compat_data[] = {
141 * When doing i2c IO, indicate that we need to wait for exclusive bus ownership,
142 * but that we should not wait if we already own the bus. This lets us put
143 * iicbus_acquire_bus() calls with a non-recursive wait at the entry of our API
144 * functions to ensure that only one client at a time accesses the hardware for
145 * the entire series of operations it takes to read or write the clock.
147 #define WAITFLAGS (IIC_WAIT | IIC_RECURSIVE)
150 isl12xx_read1(struct isl12xx_softc *sc, uint8_t reg, uint8_t *data)
153 return (iicdev_readfrom(sc->dev, reg, data, 1, WAITFLAGS));
157 isl12xx_write1(struct isl12xx_softc *sc, uint8_t reg, uint8_t val)
160 return (iicdev_writeto(sc->dev, reg, &val, 1, WAITFLAGS));
164 isl12xx_init(void *arg)
166 struct isl12xx_softc *sc = arg;
169 config_intrhook_disestablish(&sc->init_hook);
172 * Check the clock-stopped/power-fail bit, just so we can report it to
173 * the user at boot time.
175 isl12xx_read1(sc, ISL12XX_SR_REG, &sreg);
176 if (sreg & ISL12XX_SR_RTCF) {
177 device_printf(sc->dev,
178 "RTC clock stopped; check battery\n");
182 * Register as a system realtime clock.
184 clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ);
185 clock_schedule(sc->dev, 1);
189 isl12xx_probe(device_t dev)
193 if (!ofw_bus_status_okay(dev))
196 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
197 device_set_desc(dev, "Intersil ISL12xx RTC");
198 return (BUS_PROBE_DEFAULT);
205 isl12xx_attach(device_t dev)
207 struct isl12xx_softc *sc = device_get_softc(dev);
210 sc->busdev = device_get_parent(sc->dev);
213 * Chip init must wait until interrupts are enabled. Often i2c access
214 * works only when the interrupts are available.
216 sc->init_hook.ich_func = isl12xx_init;
217 sc->init_hook.ich_arg = sc;
218 if (config_intrhook_establish(&sc->init_hook) != 0)
225 isl12xx_detach(device_t dev)
228 clock_unregister(dev);
233 isl12xx_gettime(device_t dev, struct timespec *ts)
235 struct isl12xx_softc *sc = device_get_softc(dev);
237 struct time_regs tregs;
239 uint8_t hourmask, sreg;
242 * Read the status and time registers.
244 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) == 0) {
245 if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) {
246 err = iicdev_readfrom(sc->dev, ISL12XX_SC_REG, &tregs,
247 sizeof(tregs), WAITFLAGS);
249 iicbus_release_bus(sc->busdev, sc->dev);
254 /* If power failed, we can't provide valid time. */
255 if (sreg & ISL12XX_SR_RTCF)
258 /* If chip is in AM/PM mode remember that for when we set time. */
259 if (tregs.hour & ISL12XX_24HR_FLAG) {
260 hourmask = ISL12xx_24HR_MASK;
263 hourmask = ISL12xx_12HR_MASK;
267 ct.sec = FROMBCD(tregs.sec);
268 ct.min = FROMBCD(tregs.min);
269 ct.hour = FROMBCD(tregs.hour & hourmask);
270 ct.day = FROMBCD(tregs.day);
271 ct.mon = FROMBCD(tregs.month);
272 ct.year = FROMBCD(tregs.year);
277 if (tregs.hour & ISL12XX_PM_FLAG)
281 return (clock_ct_to_ts(&ct, ts));
285 isl12xx_settime(device_t dev, struct timespec *ts)
287 struct isl12xx_softc *sc = device_get_softc(dev);
289 struct time_regs tregs;
291 uint8_t ampmflags, sreg;
294 * We request a timespec with no resolution-adjustment. That also
295 * disables utc adjustment, so apply that ourselves.
297 ts->tv_sec -= utc_offset();
299 clock_ts_to_ct(ts, &ct);
301 /* If the chip is in AM/PM mode, adjust hour and set flags as needed. */
303 ampmflags = ISL12XX_24HR_FLAG;
308 ampmflags |= ISL12XX_PM_FLAG;
314 tregs.sec = TOBCD(ct.sec);
315 tregs.min = TOBCD(ct.min);
316 tregs.hour = TOBCD(ct.hour) | ampmflags;
317 tregs.day = TOBCD(ct.day);
318 tregs.month = TOBCD(ct.mon);
319 tregs.year = TOBCD(ct.year % 100);
322 * To set the time we have to set the WRTC enable bit in the control
323 * register, then write the time regs, then clear the WRTC bit. While
324 * doing so we have to be careful to not write a 0 to any sreg bit which
325 * is "write 0 to clear". One of those bits could get set between
326 * reading and writing the register. All those bits ignore attempts to
327 * write a 1, so just always OR-in all the W0C bits to be sure we never
328 * accidentally clear one. We hold ownership of the i2c bus for the
329 * whole read-modify-write sequence.
331 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0)
333 if ((err = isl12xx_read1(sc, ISL12XX_SR_REG, &sreg)) == 0) {
334 sreg |= ISL12XX_SR_WRTC | ISL12XX_SR_W0C_BITS;
335 if ((err = isl12xx_write1(sc, ISL12XX_SR_REG, sreg)) == 0) {
336 err = iicdev_writeto(sc->dev, ISL12XX_SC_REG, &tregs,
337 sizeof(tregs), WAITFLAGS);
338 sreg &= ~ISL12XX_SR_WRTC;
339 isl12xx_write1(sc, ISL12XX_SR_REG, sreg);
342 iicbus_release_bus(sc->busdev, sc->dev);
347 static device_method_t isl12xx_methods[] = {
348 /* device_if methods */
349 DEVMETHOD(device_probe, isl12xx_probe),
350 DEVMETHOD(device_attach, isl12xx_attach),
351 DEVMETHOD(device_detach, isl12xx_detach),
353 /* clock_if methods */
354 DEVMETHOD(clock_gettime, isl12xx_gettime),
355 DEVMETHOD(clock_settime, isl12xx_settime),
360 static driver_t isl12xx_driver = {
363 sizeof(struct isl12xx_softc),
365 static devclass_t isl12xx_devclass;
367 DRIVER_MODULE(isl12xx, iicbus, isl12xx_driver, isl12xx_devclass, NULL, NULL);
368 MODULE_VERSION(isl12xx, 1);
369 MODULE_DEPEND(isl12xx, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);