2 * Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * Driver for NXP real-time clock/calendar chips:
32 * - PCF8563 = low power, countdown timer
33 * - PCA8565 = like PCF8563, automotive temperature range
34 * - PCF8523 = low power, countdown timer, oscillator freq tuning, 2 timers
35 * - PCF2127 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, 512B ram
36 * - PCA2129 = like PCF8523, automotive, tcxo, tamper/ts, i2c & spi, no timer
37 * - PCF2129 = like PCF8523, industrial, tcxo, tamper/ts, i2c & spi, no timer
39 * Most chips have a countdown timer, ostensibly intended to generate periodic
40 * interrupt signals on an output pin. The timer is driven from the same
41 * divider chain that clocks the time of day registers, and they start counting
42 * in sync when the STOP bit is cleared after the time and timer registers are
43 * set. The timer register can also be read on the fly, so we use it to count
44 * fractional seconds and get a resolution of ~15ms.
47 #include "opt_platform.h"
49 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/clock.h>
53 #include <sys/kernel.h>
54 #include <sys/libkern.h>
55 #include <sys/module.h>
57 #include <dev/iicbus/iicbus.h>
58 #include <dev/iicbus/iiconf.h>
60 #include <dev/ofw/openfirm.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
66 #include "iicbus_if.h"
69 * I2C address 1010 001x : PCA2129 PCF2127 PCF2129 PCF8563 PCF8565
70 * I2C address 1101 000x : PCF8523
72 #define PCF8563_ADDR 0xa2
73 #define PCF8523_ADDR 0xd0
76 * Registers, bits within them, and masks that are common to all chip types.
78 #define PCF85xx_R_CS1 0x00 /* CS1 and CS2 control regs are in */
79 #define PCF85xx_R_CS2 0x01 /* the same location on all chips. */
81 #define PCF85xx_B_CS1_STOP 0x20 /* Stop time incrementing bit */
82 #define PCF85xx_B_SECOND_OS 0x80 /* Oscillator Stopped bit */
84 #define PCF85xx_M_SECOND 0x7f /* Masks for all BCD time regs... */
85 #define PCF85xx_M_MINUTE 0x7f
86 #define PCF85xx_M_12HOUR 0x1f
87 #define PCF85xx_M_24HOUR 0x3f
88 #define PCF85xx_M_DAY 0x3f
89 #define PCF85xx_M_MONTH 0x1f
90 #define PCF85xx_M_YEAR 0xff
93 * PCF2127-specific registers, bits, and masks.
95 #define PCF2127_R_TMR_CTL 0x10 /* Timer/watchdog control */
97 #define PCF2127_M_TMR_CTRL 0xe3 /* Mask off undef bits */
99 #define PCF2127_B_TMR_CD 0x40 /* Run in countdown mode */
100 #define PCF2127_B_TMR_64HZ 0x01 /* Timer frequency 64Hz */
103 * PCA/PCF2129-specific registers, bits, and masks.
105 #define PCF2129_B_CS1_12HR 0x04 /* Use 12-hour (AM/PM) mode bit */
106 #define PCF2129_B_CLKOUT_OTPR 0x20 /* OTP refresh command */
107 #define PCF2129_B_CLKOUT_HIGHZ 0x07 /* Clock Out Freq = disable */
110 * PCF8523-specific registers, bits, and masks.
112 #define PCF8523_R_CS3 0x02 /* Control and status reg 3 */
113 #define PCF8523_R_SECOND 0x03 /* Seconds */
114 #define PCF8523_R_TMR_CLKOUT 0x0F /* Timer and clockout control */
115 #define PCF8523_R_TMR_A_FREQ 0x10 /* Timer A frequency control */
116 #define PCF8523_R_TMR_A_COUNT 0x11 /* Timer A count */
118 #define PCF8523_M_TMR_A_FREQ 0x07 /* Mask off undef bits */
120 #define PCF8523_B_HOUR_PM 0x20 /* PM bit */
121 #define PCF8523_B_CS1_SOFTRESET 0x58 /* Initiate Soft Reset bits */
122 #define PCF8523_B_CS1_12HR 0x08 /* Use 12-hour (AM/PM) mode bit */
123 #define PCF8523_B_CLKOUT_TACD 0x02 /* TimerA runs in CountDown mode */
124 #define PCF8523_B_CLKOUT_HIGHZ 0x38 /* Clock Out Freq = disable */
125 #define PCF8523_B_TMR_A_64HZ 0x01 /* Timer A freq 64Hz */
127 #define PCF8523_M_CS3_PM 0xE0 /* Power mode mask */
128 #define PCF8523_B_CS3_PM_NOBAT 0xE0 /* PM bits: no battery usage */
129 #define PCF8523_B_CS3_PM_STD 0x00 /* PM bits: standard */
130 #define PCF8523_B_CS3_BLF 0x04 /* Battery Low Flag bit */
133 * PCF8563-specific registers, bits, and masks.
135 #define PCF8563_R_SECOND 0x02 /* Seconds */
136 #define PCF8563_R_TMR_CTRL 0x0e /* Timer control */
137 #define PCF8563_R_TMR_COUNT 0x0f /* Timer count */
139 #define PCF8563_M_TMR_CTRL 0x93 /* Mask off undef bits */
141 #define PCF8563_B_TMR_ENABLE 0x80 /* Enable countdown timer */
142 #define PCF8563_B_TMR_64HZ 0x01 /* Timer frequency 64Hz */
144 #define PCF8563_B_MONTH_C 0x80 /* Century bit */
147 * We use the countdown timer for fractional seconds. We program it for 64 Hz,
148 * the fastest available rate that doesn't roll over in less than a second.
150 #define TMR_TICKS_SEC 64
151 #define TMR_TICKS_HALFSEC 32
154 * The chip types we support.
167 static const char *desc_strings[] = {
176 CTASSERT(nitems(desc_strings) == TYPE_COUNT);
179 * The time registers in the order they are laid out in hardware.
182 uint8_t sec, min, hour, day, wday, month, year;
185 struct nxprtc_softc {
188 struct intr_config_hook
190 u_int flags; /* SC_F_* flags */
191 u_int chiptype; /* Type of PCF85xx chip */
192 uint8_t secaddr; /* Address of seconds register */
193 uint8_t tmcaddr; /* Address of timer count register */
194 bool use_timer; /* Use timer for fractional sec */
197 #define SC_F_CPOL (1 << 0) /* Century bit means 19xx */
198 #define SC_F_AMPM (1 << 1) /* Use PM flag in hours reg */
201 * We use the compat_data table to look up hint strings in the non-FDT case, so
202 * define the struct locally when we don't get it from ofw_bus_subr.h.
205 typedef struct ofw_compat_data nxprtc_compat_data;
210 } nxprtc_compat_data;
213 static nxprtc_compat_data compat_data[] = {
214 {"nxp,pca2129", TYPE_PCA2129},
215 {"nxp,pca8565", TYPE_PCA8565},
216 {"nxp,pcf2127", TYPE_PCF2127},
217 {"nxp,pcf2129", TYPE_PCF2129},
218 {"nxp,pcf8523", TYPE_PCF8523},
219 {"nxp,pcf8563", TYPE_PCF8563},
221 /* Undocumented compat strings known to exist in the wild... */
222 {"pcf8563", TYPE_PCF8563},
223 {"phg,pcf8563", TYPE_PCF8563},
224 {"philips,pcf8563", TYPE_PCF8563},
230 read_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t *val)
233 return (iicdev_readfrom(sc->dev, reg, val, sizeof(*val), IIC_WAIT));
237 write_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t val)
240 return (iicdev_writeto(sc->dev, reg, &val, sizeof(val), IIC_WAIT));
244 read_timeregs(struct nxprtc_softc *sc, struct time_regs *tregs, uint8_t *tmr)
247 uint8_t sec, tmr1, tmr2;
250 * The datasheet says loop to read the same timer value twice because it
251 * does not freeze while reading. To that we add our own logic that
252 * the seconds register must be the same before and after reading the
253 * timer, ensuring the fractional part is from the same second as tregs.
257 if ((err = read_reg(sc, sc->secaddr, &sec)) != 0)
259 if ((err = read_reg(sc, sc->tmcaddr, &tmr1)) != 0)
261 if ((err = read_reg(sc, sc->tmcaddr, &tmr2)) != 0)
266 if ((err = iicdev_readfrom(sc->dev, sc->secaddr, tregs,
267 sizeof(*tregs), IIC_WAIT)) != 0)
269 } while (sc->use_timer && tregs->sec != sec);
272 * If the timer value is greater than our hz rate (or is zero),
273 * something is wrong. Maybe some other OS used the timer differently?
274 * Just set it to zero. Likewise if we're not using the timer. After
275 * the offset calc below, the zero turns into 32, the mid-second point,
276 * which in effect performs 4/5 rounding, which is just the right thing
277 * to do if we don't have fine-grained time.
279 if (!sc->use_timer || tmr1 > TMR_TICKS_SEC)
283 * Turn the downcounter into an upcounter. The timer starts counting at
284 * and rolls over at mid-second, so add half a second worth of ticks to
285 * get its zero point back in sync with the tregs.sec rollover.
287 *tmr = (TMR_TICKS_SEC - tmr1 + TMR_TICKS_HALFSEC) % TMR_TICKS_SEC;
293 write_timeregs(struct nxprtc_softc *sc, struct time_regs *tregs)
296 return (iicdev_writeto(sc->dev, sc->secaddr, tregs,
297 sizeof(*tregs), IIC_WAIT));
301 pcf8523_start(struct nxprtc_softc *sc)
304 uint8_t cs1, cs3, clkout;
307 is2129 = (sc->chiptype == TYPE_PCA2129 || sc->chiptype == TYPE_PCF2129);
309 /* Read and sanity-check the control registers. */
310 if ((err = read_reg(sc, PCF85xx_R_CS1, &cs1)) != 0) {
311 device_printf(sc->dev, "cannot read RTC CS1 control\n");
314 if ((err = read_reg(sc, PCF8523_R_CS3, &cs3)) != 0) {
315 device_printf(sc->dev, "cannot read RTC CS3 control\n");
320 * Do a full init (soft-reset) if...
321 * - The chip is in battery-disable mode (fresh from the factory).
322 * - The clock-increment STOP flag is set (this is just insane).
323 * After reset, battery disable mode has to be overridden to "standard"
324 * mode. Also, turn off clock output to save battery power.
326 if ((cs3 & PCF8523_M_CS3_PM) == PCF8523_B_CS3_PM_NOBAT ||
327 (cs1 & PCF85xx_B_CS1_STOP)) {
328 cs1 = PCF8523_B_CS1_SOFTRESET;
329 if ((err = write_reg(sc, PCF85xx_R_CS1, cs1)) != 0) {
330 device_printf(sc->dev, "cannot write CS1 control\n");
333 cs3 = PCF8523_B_CS3_PM_STD;
334 if ((err = write_reg(sc, PCF8523_R_CS3, cs3)) != 0) {
335 device_printf(sc->dev, "cannot write CS3 control\n");
339 * For 2129 series, trigger OTP refresh by forcing the OTPR bit
340 * to zero then back to 1, then wait 100ms for the refresh, and
341 * finally set the bit back to zero with the COF_HIGHZ write.
344 clkout = PCF2129_B_CLKOUT_HIGHZ;
345 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT,
347 device_printf(sc->dev,
348 "cannot write CLKOUT control\n");
351 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT,
352 clkout | PCF2129_B_CLKOUT_OTPR)) != 0) {
353 device_printf(sc->dev,
354 "cannot write CLKOUT control\n");
357 pause_sbt("nxpotp", mstosbt(100), mstosbt(10), 0);
359 clkout = PCF8523_B_CLKOUT_HIGHZ;
360 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, clkout)) != 0) {
361 device_printf(sc->dev, "cannot write CLKOUT control\n");
364 device_printf(sc->dev,
365 "first time startup, enabled RTC battery operation\n");
368 * Sleep briefly so the battery monitor can make a measurement,
369 * then re-read CS3 so battery-low status can be reported below.
371 pause_sbt("nxpbat", mstosbt(100), 0, 0);
372 if ((err = read_reg(sc, PCF8523_R_CS3, &cs3)) != 0) {
373 device_printf(sc->dev, "cannot read RTC CS3 control\n");
378 /* Let someone know if the battery is weak. */
379 if (cs3 & PCF8523_B_CS3_BLF)
380 device_printf(sc->dev, "WARNING: RTC battery is low\n");
382 /* Remember whether we're running in AM/PM mode. */
384 if (cs1 & PCF2129_B_CS1_12HR)
385 sc->flags |= SC_F_AMPM;
387 if (cs1 & PCF8523_B_CS1_12HR)
388 sc->flags |= SC_F_AMPM;
395 pcf8523_start_timer(struct nxprtc_softc *sc)
398 uint8_t clkout, stdclk, stdfreq, tmrfreq;
401 * Read the timer control and frequency regs. If they don't have the
402 * values we normally program into them then the timer count doesn't
403 * contain a valid fractional second, so zero it to prevent using a bad
404 * value. Then program the normal timer values so that on the first
405 * settime call we'll begin to use fractional time.
407 if ((err = read_reg(sc, PCF8523_R_TMR_A_FREQ, &tmrfreq)) != 0)
409 if ((err = read_reg(sc, PCF8523_R_TMR_CLKOUT, &clkout)) != 0)
412 stdfreq = PCF8523_B_TMR_A_64HZ;
413 stdclk = PCF8523_B_CLKOUT_TACD | PCF8523_B_CLKOUT_HIGHZ;
415 if (clkout != stdclk || (tmrfreq & PCF8523_M_TMR_A_FREQ) != stdfreq) {
416 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0)
418 if ((err = write_reg(sc, PCF8523_R_TMR_A_FREQ, stdfreq)) != 0)
420 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, stdclk)) != 0)
427 pcf2127_start_timer(struct nxprtc_softc *sc)
430 uint8_t stdctl, tmrctl;
432 /* See comment in pcf8523_start_timer(). */
433 if ((err = read_reg(sc, PCF2127_R_TMR_CTL, &tmrctl)) != 0)
436 stdctl = PCF2127_B_TMR_CD | PCF8523_B_TMR_A_64HZ;
438 if ((tmrctl & PCF2127_M_TMR_CTRL) != stdctl) {
439 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0)
441 if ((err = write_reg(sc, PCF2127_R_TMR_CTL, stdctl)) != 0)
448 pcf8563_start_timer(struct nxprtc_softc *sc)
451 uint8_t stdctl, tmrctl;
453 /* See comment in pcf8523_start_timer(). */
454 if ((err = read_reg(sc, PCF8563_R_TMR_CTRL, &tmrctl)) != 0)
457 stdctl = PCF8563_B_TMR_ENABLE | PCF8563_B_TMR_64HZ;
459 if ((tmrctl & PCF8563_M_TMR_CTRL) != stdctl) {
460 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0)
462 if ((err = write_reg(sc, PCF8563_R_TMR_CTRL, stdctl)) != 0)
469 nxprtc_start(void *dev)
471 struct nxprtc_softc *sc;
472 int clockflags, resolution;
475 sc = device_get_softc((device_t)dev);
476 config_intrhook_disestablish(&sc->config_hook);
478 /* First do chip-specific inits. */
479 switch (sc->chiptype) {
482 if (pcf8523_start(sc) != 0)
484 /* No timer to start */
487 if (pcf8523_start(sc) != 0)
489 if (pcf2127_start_timer(sc) != 0) {
490 device_printf(sc->dev, "cannot set up timer\n");
495 if (pcf8523_start(sc) != 0)
497 if (pcf8523_start_timer(sc) != 0) {
498 device_printf(sc->dev, "cannot set up timer\n");
504 if (pcf8563_start_timer(sc) != 0) {
505 device_printf(sc->dev, "cannot set up timer\n");
510 device_printf(sc->dev, "missing init code for this chiptype\n");
515 * Common init. Read the seconds register so we can check the
516 * oscillator-stopped status bit in it.
518 if (read_reg(sc, sc->secaddr, &sec) != 0) {
519 device_printf(sc->dev, "cannot read RTC seconds\n");
522 if ((sec & PCF85xx_B_SECOND_OS) != 0) {
523 device_printf(sc->dev,
524 "WARNING: RTC battery failed; time is invalid\n");
528 * Everything looks good if we make it to here; register as an RTC. If
529 * we're using the timer to count fractional seconds, our resolution is
530 * 1e6/64, about 15.6ms. Without the timer we still align the RTC clock
531 * when setting it so our error is an average .5s when reading it.
532 * Schedule our clock_settime() method to be called at a .495ms offset
533 * into the second, because the clock hardware resets the divider chain
534 * to the mid-second point when you set the time and it takes about 5ms
535 * of i2c bus activity to set the clock.
537 resolution = sc->use_timer ? 1000000 / TMR_TICKS_SEC : 1000000 / 2;
538 clockflags = CLOCKF_GETTIME_NO_ADJ | CLOCKF_SETTIME_NO_TS;
539 clock_register_flags(sc->dev, resolution, clockflags);
540 clock_schedule(sc->dev, 495000000);
544 nxprtc_gettime(device_t dev, struct timespec *ts)
547 struct time_regs tregs;
548 struct nxprtc_softc *sc;
550 uint8_t cs1, hourmask, tmrcount;
552 sc = device_get_softc(dev);
555 * Read the time, but before using it, validate that the oscillator-
556 * stopped/power-fail bit is not set, and that the time-increment STOP
557 * bit is not set in the control reg. The latter can happen if there
558 * was an error when setting the time.
560 if ((err = read_timeregs(sc, &tregs, &tmrcount)) != 0) {
561 device_printf(dev, "cannot read RTC time\n");
564 if ((err = read_reg(sc, PCF85xx_R_CS1, &cs1)) != 0) {
565 device_printf(dev, "cannot read RTC time\n");
568 if ((tregs.sec & PCF85xx_B_SECOND_OS) || (cs1 & PCF85xx_B_CS1_STOP)) {
569 device_printf(dev, "RTC clock not running\n");
570 return (EINVAL); /* hardware is good, time is not. */
573 if (sc->flags & SC_F_AMPM)
574 hourmask = PCF85xx_M_12HOUR;
576 hourmask = PCF85xx_M_24HOUR;
578 ct.nsec = ((uint64_t)tmrcount * 1000000000) / TMR_TICKS_SEC;
579 ct.sec = FROMBCD(tregs.sec & PCF85xx_M_SECOND);
580 ct.min = FROMBCD(tregs.min & PCF85xx_M_MINUTE);
581 ct.hour = FROMBCD(tregs.hour & hourmask);
582 ct.day = FROMBCD(tregs.day & PCF85xx_M_DAY);
583 ct.mon = FROMBCD(tregs.month & PCF85xx_M_MONTH);
584 ct.year = FROMBCD(tregs.year & PCF85xx_M_YEAR);
586 if (ct.year < POSIX_BASE_YEAR)
587 ct.year += 100; /* assume [1970, 2069] */
590 * Old PCF8563 datasheets recommended that the C bit be 1 for 19xx and 0
591 * for 20xx; newer datasheets don't recommend that. We don't care,
592 * but we may co-exist with other OSes sharing the hardware. Determine
593 * existing polarity on a read so that we can preserve it on a write.
595 if (sc->chiptype == TYPE_PCF8563) {
596 if (tregs.month & PCF8563_B_MONTH_C) {
598 sc->flags |= SC_F_CPOL;
599 } else if (ct.year < 2000)
600 sc->flags |= SC_F_CPOL;
603 /* If this chip is running in 12-hour/AMPM mode, deal with it. */
604 if (sc->flags & SC_F_AMPM) {
607 if (tregs.hour & PCF8523_B_HOUR_PM)
611 err = clock_ct_to_ts(&ct, ts);
612 ts->tv_sec += utc_offset();
618 nxprtc_settime(device_t dev, struct timespec *ts)
621 struct time_regs tregs;
622 struct nxprtc_softc *sc;
624 uint8_t cflag, cs1, pmflag;
626 sc = device_get_softc(dev);
629 * We stop the clock, set the time, then restart the clock. Half a
630 * second after restarting the clock it ticks over to the next second.
631 * So to align the RTC, we schedule this function to be called when
632 * system time is roughly halfway (.495) through the current second.
634 * Reserve use of the i2c bus and stop the RTC clock. Note that if
635 * anything goes wrong from this point on, we leave the clock stopped,
636 * because we don't really know what state it's in.
638 if ((err = iicbus_request_bus(sc->busdev, sc->dev, IIC_WAIT)) != 0)
640 if ((err = read_reg(sc, PCF85xx_R_CS1, &cs1)) != 0)
642 cs1 |= PCF85xx_B_CS1_STOP;
643 if ((err = write_reg(sc, PCF85xx_R_CS1, cs1)) != 0)
646 /* Grab a fresh post-sleep idea of what time it is. */
648 ts->tv_sec -= utc_offset();
650 clock_ts_to_ct(ts, &ct);
652 /* If the chip is in AMPM mode deal with the PM flag. */
654 if (sc->flags & SC_F_AMPM) {
657 pmflag = PCF8523_B_HOUR_PM;
663 /* On 8563 set the century based on the polarity seen when reading. */
665 if (sc->chiptype == TYPE_PCF8563) {
666 if ((sc->flags & SC_F_CPOL) != 0) {
668 cflag = PCF8563_B_MONTH_C;
669 } else if (ct.year < 2000)
670 cflag = PCF8563_B_MONTH_C;
673 tregs.sec = TOBCD(ct.sec);
674 tregs.min = TOBCD(ct.min);
675 tregs.hour = TOBCD(ct.hour) | pmflag;
676 tregs.day = TOBCD(ct.day);
677 tregs.month = TOBCD(ct.mon);
678 tregs.year = TOBCD(ct.year % 100) | cflag;
682 * Set the time, reset the timer count register, then start the clocks.
684 if ((err = write_timeregs(sc, &tregs)) != 0)
687 if ((err = write_reg(sc, sc->tmcaddr, TMR_TICKS_SEC)) != 0)
690 cs1 &= ~PCF85xx_B_CS1_STOP;
691 err = write_reg(sc, PCF85xx_R_CS1, cs1);
695 iicbus_release_bus(sc->busdev, sc->dev);
698 device_printf(dev, "cannot write RTC time\n");
704 nxprtc_get_chiptype(device_t dev)
708 return (ofw_bus_search_compatible(dev, compat_data)->ocd_data);
710 nxprtc_compat_data *cdata;
715 * If given a chiptype hint string, loop through the ofw compat data
716 * comparing the hinted chip type to the compat strings. The table end
717 * marker ocd_data is TYPE_NONE.
719 if (resource_string_value(device_get_name(dev),
720 device_get_unit(dev), "compatible", &htype) == 0) {
721 for (cdata = compat_data; cdata->ocd_str != NULL; ++cdata) {
722 if (strcmp(htype, cdata->ocd_str) == 0)
725 chiptype = cdata->ocd_data;
727 chiptype = TYPE_NONE;
730 * On non-FDT systems the historical behavior of this driver was to
731 * assume a PCF8563; keep doing that for compatibility.
733 if (chiptype == TYPE_NONE)
734 return (TYPE_PCF8563);
741 nxprtc_probe(device_t dev)
746 if (!ofw_bus_status_okay(dev))
748 rv = BUS_PROBE_GENERIC;
750 rv = BUS_PROBE_NOWILDCARD;
752 if ((chiptype = nxprtc_get_chiptype(dev)) == TYPE_NONE)
755 device_set_desc(dev, desc_strings[chiptype]);
760 nxprtc_attach(device_t dev)
762 struct nxprtc_softc *sc;
764 sc = device_get_softc(dev);
766 sc->busdev = device_get_parent(dev);
768 /* We need to know what kind of chip we're driving. */
769 sc->chiptype = nxprtc_get_chiptype(dev);
771 /* The features and some register addresses vary by chip type. */
772 switch (sc->chiptype) {
775 sc->secaddr = PCF8523_R_SECOND;
777 sc->use_timer = false;
781 sc->secaddr = PCF8523_R_SECOND;
782 sc->tmcaddr = PCF8523_R_TMR_A_COUNT;
783 sc->use_timer = true;
787 sc->secaddr = PCF8563_R_SECOND;
788 sc->tmcaddr = PCF8563_R_TMR_COUNT;
789 sc->use_timer = true;
792 device_printf(dev, "impossible: cannot determine chip type\n");
797 * We have to wait until interrupts are enabled. Sometimes I2C read
798 * and write only works when the interrupts are available.
800 sc->config_hook.ich_func = nxprtc_start;
801 sc->config_hook.ich_arg = dev;
802 if (config_intrhook_establish(&sc->config_hook) != 0)
809 nxprtc_detach(device_t dev)
812 clock_unregister(dev);
816 static device_method_t nxprtc_methods[] = {
817 DEVMETHOD(device_probe, nxprtc_probe),
818 DEVMETHOD(device_attach, nxprtc_attach),
819 DEVMETHOD(device_detach, nxprtc_detach),
821 DEVMETHOD(clock_gettime, nxprtc_gettime),
822 DEVMETHOD(clock_settime, nxprtc_settime),
827 static driver_t nxprtc_driver = {
830 sizeof(struct nxprtc_softc),
833 static devclass_t nxprtc_devclass;
835 DRIVER_MODULE(nxprtc, iicbus, nxprtc_driver, nxprtc_devclass, NULL, NULL);
836 MODULE_VERSION(nxprtc, 1);
837 MODULE_DEPEND(nxprtc, iicbus, IICBB_MINVER, IICBB_PREFVER, IICBB_MAXVER);