3 * Copyright (c) 2000-04 ICP vortex GmbH
4 * Copyright (c) 2002-04 Intel Corporation
5 * Copyright (c) 2003-04 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * iir.h: Definitions/Constants used by the Intel Integrated RAID driver
38 * Written by: Achim Leubner <achim_leubner@adaptec.com>
39 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
41 * credits: Niklas Hallqvist; OpenBSD driver for the ICP Controllers.
42 * FreeBSD.ORG; Great O/S to work on and for.
44 * $Id: iir.h 1.6 2004/03/30 10:19:44 achim Exp $"
51 #error this file needs sys/cdefs.h as a prerequisite
54 #define IIR_DRIVER_VERSION 1
55 #define IIR_DRIVER_SUBVERSION 5
58 #define OEM_ID_ICP 0x941c
59 #define OEM_ID_INTEL 0x8000
61 #define GDT_VENDOR_ID 0x1119
62 #define GDT_DEVICE_ID_MIN 0x100
63 #define GDT_DEVICE_ID_MAX 0x2ff
64 #define GDT_DEVICE_ID_NEWRX 0x300
66 #define INTEL_VENDOR_ID 0x8086
67 #define INTEL_DEVICE_ID_IIR 0x600
69 #define GDT_MAXBUS 6 /* XXX Why not 5? */
70 #define GDT_MAX_HDRIVES 100 /* max 100 host drives */
71 #define GDT_MAXID_FC 127 /* Fibre-channel IDs */
72 #define GDT_MAXID 16 /* SCSI IDs */
73 #define GDT_MAXOFFSETS 128
74 #define GDT_MAXSG 32 /* Max. s/g elements */
75 #define GDT_PROTOCOL_VERSION 1
76 #define GDT_LINUX_OS 8 /* Used for cache optimization */
77 #define GDT_SCATTER_GATHER 1 /* s/g feature */
78 #define GDT_SECS32 0x1f /* round capacity */
79 #define GDT_LOCALBOARD 0 /* Board node always 0 */
80 #define GDT_MAXCMDS 124
81 #define GDT_SECTOR_SIZE 0x200 /* Always 512 bytes for cache devs */
82 #define GDT_MAX_EVENTS 0x100 /* event buffer */
85 #define GDT_MPR_MAGIC 0xc0ffee11
86 #define GDT_IC_HEADER_BYTES 48
87 #define GDT_IC_QUEUE_BYTES 4
88 #define GDT_DPMEM_COMMAND_OFFSET \
89 (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
91 /* geometry constants */
92 #define GDT_MAXCYLS 1024
94 #define GDT_SECS 32 /* mapping 64*32 */
95 #define GDT_MEDHEADS 127
96 #define GDT_MEDSECS 63 /* mapping 127*63 */
97 #define GDT_BIGHEADS 255
98 #define GDT_BIGSECS 63 /* mapping 255*63 */
100 /* data direction raw service */
101 #define GDT_DATA_IN 0x01000000L
102 #define GDT_DATA_OUT 0x00000000L
104 /* Cache/raw service commands */
105 #define GDT_INIT 0 /* service initialization */
106 #define GDT_READ 1 /* read command */
107 #define GDT_WRITE 2 /* write command */
108 #define GDT_INFO 3 /* information about devices */
109 #define GDT_FLUSH 4 /* flush dirty cache buffers */
110 #define GDT_IOCTL 5 /* ioctl command */
111 #define GDT_DEVTYPE 9 /* additional information */
112 #define GDT_MOUNT 10 /* mount cache device */
113 #define GDT_UNMOUNT 11 /* unmount cache device */
114 #define GDT_SET_FEAT 12 /* set features (scatter/gather) */
115 #define GDT_GET_FEAT 13 /* get features */
116 #define GDT_WRITE_THR 16 /* write through */
117 #define GDT_READ_THR 17 /* read through */
118 #define GDT_EXT_INFO 18 /* extended info */
119 #define GDT_RESET 19 /* controller reset */
120 #define GDT_FREEZE_IO 25 /* freeze all IOs */
121 #define GDT_UNFREEZE_IO 26 /* unfreeze all IOs */
123 /* Additional raw service commands */
124 #define GDT_RESERVE 14 /* reserve device to raw service */
125 #define GDT_RELEASE 15 /* release device */
126 #define GDT_RESERVE_ALL 16 /* reserve all devices */
127 #define GDT_RELEASE_ALL 17 /* release all devices */
128 #define GDT_RESET_BUS 18 /* reset bus */
129 #define GDT_SCAN_START 19 /* start device scan */
130 #define GDT_SCAN_END 20 /* stop device scan */
132 /* IOCTL command defines */
133 #define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */
134 #define GDT_SCSI_CHAN_CNT 0x05 /* SCSI channel count */
135 #define GDT_SCSI_DR_LIST 0x06 /* SCSI drive list */
136 #define GDT_SCSI_DEF_CNT 0x15 /* grown/primary defects */
137 #define GDT_DSK_STATISTICS 0x4b /* SCSI disk statistics */
138 #define GDT_IOCHAN_DESC 0x5d /* description of IO channel */
139 #define GDT_IOCHAN_RAW_DESC 0x5e /* description of raw IO channel */
141 #define GDT_L_CTRL_PATTERN 0x20000000 /* SCSI IOCTL mask */
142 #define GDT_ARRAY_INFO 0x12 /* array drive info */
143 #define GDT_ARRAY_DRV_LIST 0x0f /* array drive list */
144 #define GDT_LA_CTRL_PATTERN 0x10000000 /* array IOCTL mask */
145 #define GDT_CACHE_DRV_CNT 0x01 /* cache drive count */
146 #define GDT_CACHE_DRV_LIST 0x02 /* cache drive list */
147 #define GDT_CACHE_INFO 0x04 /* cache info */
148 #define GDT_CACHE_CONFIG 0x05 /* cache configuration */
149 #define GDT_CACHE_DRV_INFO 0x07 /* cache drive info */
150 #define GDT_BOARD_FEATURES 0x15 /* controller features */
151 #define GDT_BOARD_INFO 0x28 /* controller info */
152 #define GDT_OEM_STR_RECORD 0x84 /* OEM info */
153 #define GDT_HOST_GET 0x10001 /* get host drive list */
154 #define GDT_IO_CHANNEL 0x20000 /* default IO channel */
155 #define GDT_INVALID_CHANNEL 0xffff /* invalid channel */
158 #define GDT_IOCTL_GENERAL _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
159 #define GDT_IOCTL_DRVERS _IOR('J', 1, int) /* get driver version */
160 #define GDT_IOCTL_CTRTYPE _IOWR('J', 2, gdt_ctrt_t) /* get ctr. type */
161 #define GDT_IOCTL_DRVERS_OLD _IOWR('J', 1, int) /* get driver version */
162 #define GDT_IOCTL_CTRTYPE_OLD _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
163 #define GDT_IOCTL_OSVERS _IOR('J', 3, gdt_osv_t) /* get OS version */
164 #define GDT_IOCTL_CTRCNT _IOR('J', 5, int) /* get ctr. count */
165 #define GDT_IOCTL_EVENT _IOWR('J', 8, gdt_event_t) /* get event */
166 #define GDT_IOCTL_STATIST _IOR('J', 9, gdt_statist_t) /* get statistics */
169 #define GDT_S_OK 1 /* no error */
170 #define GDT_S_BSY 7 /* controller busy */
171 #define GDT_S_RAW_SCSI 12 /* raw service: target error */
172 #define GDT_S_RAW_ILL 0xff /* raw service: illegal */
173 #define GDT_S_NO_STATUS 0x1000 /* got no status (driver-generated) */
175 /* Controller services */
176 #define GDT_SCSIRAWSERVICE 3
177 #define GDT_CACHESERVICE 9
178 #define GDT_SCREENSERVICE 11
180 /* Scatter/gather element */
181 #define GDT_SG_PTR 0x00 /* u_int32_t, address */
182 #define GDT_SG_LEN 0x04 /* u_int32_t, length */
183 #define GDT_SG_SZ 0x08
185 /* Cache service command */
186 #define GDT_CACHE_DEVICENO 0x00 /* u_int16_t, number of cache drive */
187 #define GDT_CACHE_BLOCKNO 0x02 /* u_int32_t, block number */
188 #define GDT_CACHE_BLOCKCNT 0x06 /* u_int32_t, block count */
189 #define GDT_CACHE_DESTADDR 0x0a /* u_int32_t, dest. addr. (-1: s/g) */
190 #define GDT_CACHE_SG_CANZ 0x0e /* u_int32_t, s/g element count */
191 #define GDT_CACHE_SG_LST 0x12 /* [GDT_MAXSG], s/g list */
192 #define GDT_CACHE_SZ (0x12 + GDT_MAXSG * GDT_SG_SZ)
195 #define GDT_IOCTL_PARAM_SIZE 0x00 /* u_int16_t, size of buffer */
196 #define GDT_IOCTL_SUBFUNC 0x02 /* u_int32_t, ioctl function */
197 #define GDT_IOCTL_CHANNEL 0x06 /* u_int32_t, device */
198 #define GDT_IOCTL_P_PARAM 0x0a /* u_int32_t, buffer */
199 #define GDT_IOCTL_SZ 0x0e
201 /* Screen service defines */
202 #define GDT_MSG_INV_HANDLE -1 /* special message handle */
203 #define GDT_MSGLEN 16 /* size of message text */
204 #define GDT_MSG_SIZE 34 /* size of message structure */
205 #define GDT_MSG_REQUEST 0 /* async. event. message */
207 /* Screen service command */
208 #define GDT_SCREEN_MSG_HANDLE 0x02 /* u_int32_t, message handle */
209 #define GDT_SCREEN_MSG_ADDR 0x06 /* u_int32_t, message buffer address */
210 #define GDT_SCREEN_SZ 0x0a
212 /* Screen service message */
213 #define GDT_SCR_MSG_HANDLE 0x00 /* u_int32_t, message handle */
214 #define GDT_SCR_MSG_LEN 0x04 /* u_int32_t, size of message */
215 #define GDT_SCR_MSG_ALEN 0x08 /* u_int32_t, answer length */
216 #define GDT_SCR_MSG_ANSWER 0x0c /* u_int8_t, answer flag */
217 #define GDT_SCR_MSG_EXT 0x0d /* u_int8_t, more messages? */
218 #define GDT_SCR_MSG_RES 0x0e /* u_int16_t, reserved */
219 #define GDT_SCR_MSG_TEXT 0x10 /* GDT_MSGLEN+2, message text */
220 #define GDT_SCR_MSG_SZ (0x12 + GDT_MSGLEN)
222 /* Raw service command */
223 #define GDT_RAW_DIRECTION 0x02 /* u_int32_t, data direction */
224 #define GDT_RAW_MDISC_TIME 0x06 /* u_int32_t, disc. time (0: none) */
225 #define GDT_RAW_MCON_TIME 0x0a /* u_int32_t, conn. time (0: none) */
226 #define GDT_RAW_SDATA 0x0e /* u_int32_t, dest. addr. (-1: s/g) */
227 #define GDT_RAW_SDLEN 0x12 /* u_int32_t, data length */
228 #define GDT_RAW_CLEN 0x16 /* u_int32_t, SCSI cmd len (6/10/12) */
229 #define GDT_RAW_CMD 0x1a /* u_int8_t [12], SCSI command */
230 #define GDT_RAW_TARGET 0x26 /* u_int8_t, target ID */
231 #define GDT_RAW_LUN 0x27 /* u_int8_t, LUN */
232 #define GDT_RAW_BUS 0x28 /* u_int8_t, SCSI bus number */
233 #define GDT_RAW_PRIORITY 0x29 /* u_int8_t, only 0 used */
234 #define GDT_RAW_SENSE_LEN 0x2a /* u_int32_t, sense data length */
235 #define GDT_RAW_SENSE_DATA 0x2e /* u_int32_t, sense data address */
236 #define GDT_RAW_SG_RANZ 0x36 /* u_int32_t, s/g element count */
237 #define GDT_RAW_SG_LST 0x3a /* [GDT_MAXSG], s/g list */
238 #define GDT_RAW_SZ (0x3a + GDT_MAXSG * GDT_SG_SZ)
240 /* Command structure */
241 #define GDT_CMD_BOARDNODE 0x00 /* u_int32_t, board node (always 0) */
242 #define GDT_CMD_COMMANDINDEX 0x04 /* u_int32_t, command number */
243 #define GDT_CMD_OPCODE 0x08 /* u_int16_t, opcode (READ, ...) */
244 #define GDT_CMD_UNION 0x0a /* cache/screen/raw service command */
245 #define GDT_CMD_UNION_SZ GDT_RAW_SZ
246 #define GDT_CMD_SZ (0x0a + GDT_CMD_UNION_SZ)
248 /* Command queue entries */
249 #define GDT_OFFSET 0x00 /* u_int16_t, command offset in the DP RAM */
250 #define GDT_SERV_ID 0x02 /* u_int16_t, service */
251 #define GDT_COMM_Q_SZ 0x04
254 #define GDT_S_CMD_INDX 0x00 /* u_int8_t, special command */
255 #define GDT_S_STATUS 0x01 /* volatile u_int8_t, status special command */
256 #define GDT_S_INFO 0x04 /* u_int32_t [4], add. info special command */
257 #define GDT_SEMA0 0x14 /* volatile u_int8_t, command semaphore */
258 #define GDT_CMD_INDEX 0x18 /* u_int8_t, command number */
259 #define GDT_STATUS 0x1c /* volatile u_int16_t, command status */
260 #define GDT_SERVICE 0x1e /* u_int16_t, service (for asynch. events) */
261 #define GDT_DPR_INFO 0x20 /* u_int32_t [2], additional info */
262 #define GDT_COMM_QUEUE 0x28 /* command queue */
263 #define GDT_DPR_CMD (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
264 /* u_int8_t [], commands */
266 /* I/O channel header */
267 #define GDT_IOC_VERSION 0x00 /* u_int32_t, version (~0: newest) */
268 #define GDT_IOC_LIST_ENTRIES 0x04 /* u_int8_t, list entry count */
269 #define GDT_IOC_FIRST_CHAN 0x05 /* u_int8_t, first channel number */
270 #define GDT_IOC_LAST_CHAN 0x06 /* u_int8_t, last channel number */
271 #define GDT_IOC_CHAN_COUNT 0x07 /* u_int8_t, (R) channel count */
272 #define GDT_IOC_LIST_OFFSET 0x08 /* u_int32_t, offset of list[0] */
273 #define GDT_IOC_HDR_SZ 0x0c
275 #define GDT_IOC_NEWEST 0xffffffff /* goes into GDT_IOC_VERSION */
277 /* Get I/O channel description */
278 #define GDT_IOC_ADDRESS 0x00 /* u_int32_t, channel address */
279 #define GDT_IOC_TYPE 0x04 /* u_int8_t, type (SCSI/FCSL) */
280 #define GDT_IOC_LOCAL_NO 0x05 /* u_int8_t, local number */
281 #define GDT_IOC_FEATURES 0x06 /* u_int16_t, channel features */
282 #define GDT_IOC_SZ 0x08
284 /* Get raw I/O channel description */
285 #define GDT_RAWIOC_PROC_ID 0x00 /* u_int8_t, processor id */
286 #define GDT_RAWIOC_PROC_DEFECT 0x01 /* u_int8_t, defect? */
287 #define GDT_RAWIOC_SZ 0x04
289 /* Get SCSI channel count */
290 #define GDT_GETCH_CHANNEL_NO 0x00 /* u_int32_t, channel number */
291 #define GDT_GETCH_DRIVE_CNT 0x04 /* u_int32_t, drive count */
292 #define GDT_GETCH_SIOP_ID 0x08 /* u_int8_t, SCSI processor ID */
293 #define GDT_GETCH_SIOP_STATE 0x09 /* u_int8_t, SCSI processor state */
294 #define GDT_GETCH_SZ 0x0a
296 /* Cache info/config IOCTL structures */
297 #define GDT_CPAR_VERSION 0x00 /* u_int32_t, firmware version */
298 #define GDT_CPAR_STATE 0x04 /* u_int16_t, cache state (on/off) */
299 #define GDT_CPAR_STRATEGY 0x06 /* u_int16_t, cache strategy */
300 #define GDT_CPAR_WRITE_BACK 0x08 /* u_int16_t, write back (on/off) */
301 #define GDT_CPAR_BLOCK_SIZE 0x0a /* u_int16_t, cache block size */
302 #define GDT_CPAR_SZ 0x0c
304 #define GDT_CSTAT_CSIZE 0x00 /* u_int32_t, cache size */
305 #define GDT_CSTAT_READ_CNT 0x04 /* u_int32_t, read counter */
306 #define GDT_CSTAT_WRITE_CNT 0x08 /* u_int32_t, write counter */
307 #define GDT_CSTAT_TR_HITS 0x0c /* u_int32_t, track hits */
308 #define GDT_CSTAT_SEC_HITS 0x10 /* u_int32_t, sector hits */
309 #define GDT_CSTAT_SEC_MISS 0x14 /* u_int32_t, sector misses */
310 #define GDT_CSTAT_SZ 0x18
313 #define GDT_CINFO_CPAR 0x00
314 #define GDT_CINFO_CSTAT GDT_CPAR_SZ
315 #define GDT_CINFO_SZ (GDT_CPAR_SZ + GDT_CSTAT_SZ)
318 #define GDT_BINFO_SER_NO 0x00 /* u_int32_t, serial number */
319 #define GDT_BINFO_OEM_ID 0x04 /* u_int8_t [2], OEM ID */
320 #define GDT_BINFO_EP_FLAGS 0x06 /* u_int16_t, eprom flags */
321 #define GDT_BINFO_PROC_ID 0x08 /* u_int32_t, processor ID */
322 #define GDT_BINFO_MEMSIZE 0x0c /* u_int32_t, memory size (bytes) */
323 #define GDT_BINFO_MEM_BANKS 0x10 /* u_int8_t, memory banks */
324 #define GDT_BINFO_CHAN_TYPE 0x11 /* u_int8_t, channel type */
325 #define GDT_BINFO_CHAN_COUNT 0x12 /* u_int8_t, channel count */
326 #define GDT_BINFO_RDONGLE_PRES 0x13 /* u_int8_t, dongle present */
327 #define GDT_BINFO_EPR_FW_VER 0x14 /* u_int32_t, (eprom) firmware ver */
328 #define GDT_BINFO_UPD_FW_VER 0x18 /* u_int32_t, (update) firmware ver */
329 #define GDT_BINFO_UPD_REVISION 0x1c /* u_int32_t, update revision */
330 #define GDT_BINFO_TYPE_STRING 0x20 /* char [16], controller name */
331 #define GDT_BINFO_RAID_STRING 0x30 /* char [16], RAID firmware name */
332 #define GDT_BINFO_UPDATE_PRES 0x40 /* u_int8_t, update present? */
333 #define GDT_BINFO_XOR_PRES 0x41 /* u_int8_t, XOR engine present */
334 #define GDT_BINFO_PROM_TYPE 0x42 /* u_int8_t, ROM type (eprom/flash) */
335 #define GDT_BINFO_PROM_COUNT 0x43 /* u_int8_t, number of ROM devices */
336 #define GDT_BINFO_DUP_PRES 0x44 /* u_int32_t, duplexing module pres? */
337 #define GDT_BINFO_CHAN_PRES 0x48 /* u_int32_t, # of exp. channels */
338 #define GDT_BINFO_MEM_PRES 0x4c /* u_int32_t, memory expansion inst? */
339 #define GDT_BINFO_FT_BUS_SYSTEM 0x50 /* u_int8_t, fault bus supported? */
340 #define GDT_BINFO_SUBTYPE_VALID 0x51 /* u_int8_t, board_subtype valid */
341 #define GDT_BINFO_BOARD_SUBTYPE 0x52 /* u_int8_t, subtype/hardware level */
342 #define GDT_BINFO_RAMPAR_PRES 0x53 /* u_int8_t, RAM parity check hw? */
343 #define GDT_BINFO_SZ 0x54
345 /* Get board features */
346 #define GDT_BFEAT_CHAINING 0x00 /* u_int8_t, chaining supported */
347 #define GDT_BFEAT_STRIPING 0x01 /* u_int8_t, striping (RAID-0) supp. */
348 #define GDT_BFEAT_MIRRORING 0x02 /* u_int8_t, mirroring (RAID-1) supp */
349 #define GDT_BFEAT_RAID 0x03 /* u_int8_t, RAID-4/5/10 supported */
350 #define GDT_BFEAT_SZ 0x04
353 #define GDT_ASYNCINDEX 0 /* command index asynchronous event */
354 #define GDT_SPEZINDEX 1 /* command index unknown service */
358 #define GDT_D_INTR 0x01
359 #define GDT_D_MISC 0x02
360 #define GDT_D_CMD 0x04
361 #define GDT_D_QUEUE 0x08
362 #define GDT_D_TIMEOUT 0x10
363 #define GDT_D_INIT 0x20
364 #define GDT_D_INVALID 0x40
365 #define GDT_D_DEBUG 0x80
366 extern int gdt_debug;
368 extern int ser_printf(const char *fmt, ...);
369 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_printf args
371 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
374 #define GDT_DPRINTF(mask, args)
377 /* Miscellaneous constants */
378 #define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
379 #define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
380 #define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
381 #define GDT_WATCH_TIMEOUT 10000000 /* 10000 * 1us = 10s */
382 #define GDT_SCRATCH_SZ 3072 /* 3KB scratch buffer */
384 /* Map minor numbers to device identity */
385 #define LUN_MASK 0x0007
386 #define TARGET_MASK 0x03f8
387 #define BUS_MASK 0x1c00
388 #define HBA_MASK 0xe000
390 #define minor2lun(minor) ( minor & LUN_MASK )
391 #define minor2target(minor) ( (minor & TARGET_MASK) >> 3 )
392 #define minor2bus(minor) ( (minor & BUS_MASK) >> 10 )
393 #define minor2hba(minor) ( (minor & HBA_MASK) >> 13 )
394 #define hba2minor(hba) ( (hba << 13) & HBA_MASK )
397 /* struct for GDT_IOCTL_GENERAL */
399 typedef struct gdt_ucmd {
406 u_int32_t BoardNode; /* board node (always 0) */
407 u_int32_t CommandIndex; /* command number */
408 u_int16_t OpCode; /* the command (READ,..) */
411 u_int16_t DeviceNo; /* number of cache drive */
412 u_int32_t BlockNo; /* block number */
413 u_int32_t BlockCnt; /* block count */
414 void *DestAddr; /* data */
415 } cache; /* cache service cmd. str. */
417 u_int16_t param_size; /* size of p_param buffer */
418 u_int32_t subfunc; /* IOCTL function */
419 u_int32_t channel; /* device */
420 void *p_param; /* data */
421 } ioctl; /* IOCTL command structure */
424 u_int32_t direction; /* data direction */
425 u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
426 u_int32_t mcon_time; /* connect time(0: no to.) */
427 void *sdata; /* dest. addr. (if s/g: -1) */
428 u_int32_t sdlen; /* data length (bytes) */
429 u_int32_t clen; /* SCSI cmd. length(6,10,12) */
430 u_int8_t cmd[12]; /* SCSI command */
431 u_int8_t target; /* target ID */
432 u_int8_t lun; /* LUN */
433 u_int8_t bus; /* SCSI bus number */
434 u_int8_t priority; /* only 0 used */
435 u_int32_t sense_len; /* sense data length */
436 void *sense_data; /* sense data addr. */
437 u_int32_t link_p; /* linked cmds (not supp.) */
438 } raw; /* raw service cmd. struct. */
440 u_int8_t data[GDT_SCRATCH_SZ];
442 TAILQ_ENTRY(gdt_ucmd) links;
445 /* struct for GDT_IOCTL_CTRTYPE */
446 typedef struct gdt_ctrt {
455 u_int16_t sub_device_id;
458 /* struct for GDT_IOCTL_OSVERS */
459 typedef struct gdt_osv {
468 #define GDT_OEM_VERSION 0x00
469 #define GDT_OEM_BUFSIZE 0x0c
471 u_int32_t ctl_version;
472 u_int32_t file_major_version;
473 u_int32_t file_minor_version;
474 u_int32_t buffer_size;
482 char product_0_1_name[16];
483 char product_4_5_name[16];
484 char product_cluster_name[16];
485 char product_reserved[16];
486 char scsi_cluster_target_vendor_id[16];
487 char cluster_raid_fw_name[16];
488 char oem_brand_name[16];
489 char oem_raid_type[16];
492 char oem_company_name[37];
495 char validation_status[80];
497 char scsi_host_drive_inquiry_vendor_id[16];
498 char library_file_template[32];
499 char tool_name_1[32];
500 char tool_name_2[32];
501 char tool_name_3[32];
502 char oem_contact_1[84];
503 char oem_contact_2[84];
504 char oem_contact_3[84];
508 gdt_oem_param_t parameters;
509 gdt_oem_record_t text;
510 } gdt_oem_str_record_t;
513 /* controller event structure */
514 #define GDT_ES_ASYNC 1
515 #define GDT_ES_DRIVER 2
516 #define GDT_ES_TEST 3
517 #define GDT_ES_SYNC 4
519 u_int16_t size; /* size of structure */
532 u_int8_t scsi_coord[3];
540 u_int8_t scsi_coord[3];
544 u_int32_t l1, l2, l3, l4;
548 u_int8_t event_string[256];
551 /* dvrevt structure */
553 u_int32_t first_stamp;
554 u_int32_t last_stamp;
555 u_int16_t same_count;
556 u_int16_t event_source;
558 u_int8_t application;
560 gdt_evt_data event_data;
563 /* struct for GDT_IOCTL_EVENT */
564 typedef struct gdt_event {
570 /* struct for GDT_IOCTL_STATIST */
571 typedef struct gdt_statist {
572 u_int16_t io_count_act;
573 u_int16_t io_count_max;
574 u_int16_t req_queue_act;
575 u_int16_t req_queue_max;
576 u_int16_t cmd_index_act;
577 u_int16_t cmd_index_max;
578 u_int16_t sg_count_act;
579 u_int16_t sg_count_max;
584 /* Context structure for interrupt services */
585 struct gdt_intr_ctx {
586 u_int32_t info, info2;
587 u_int16_t cmd_status, service;
591 /* softc structure */
594 int sc_class; /* Controller class */
596 #define GDT_CLASS_MASK 0x07
598 #define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
601 u_int16_t sc_device, sc_subdevice;
602 u_int16_t sc_fw_vers;
605 #define GDT_NORMAL 0x00
606 #define GDT_POLLING 0x01
607 #define GDT_SHUTDOWN 0x02
608 #define GDT_POLL_WAIT 0x80
610 bus_space_tag_t sc_dpmemt;
611 bus_space_handle_t sc_dpmemh;
612 bus_addr_t sc_dpmembase;
613 bus_dma_tag_t sc_parent_dmat;
614 bus_dma_tag_t sc_buffer_dmat;
615 bus_dma_tag_t sc_gccb_dmat;
616 bus_dmamap_t sc_gccb_dmamap;
617 bus_addr_t sc_gccb_busbase;
619 struct gdt_ccb *sc_gccbs;
620 SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
621 TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
622 TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
624 u_int16_t sc_ic_all_size;
625 u_int16_t sc_cmd_len;
626 u_int16_t sc_cmd_off;
627 u_int16_t sc_cmd_cnt;
628 u_int8_t sc_cmd[GDT_CMD_SZ];
633 u_int16_t sc_service;
636 u_int8_t sc_virt_bus;
637 u_int8_t sc_bus_id[GDT_MAXBUS];
638 u_int8_t sc_more_proc;
642 u_int8_t hd_is_logdrv;
643 u_int8_t hd_is_arraydrv;
644 u_int8_t hd_is_master;
645 u_int8_t hd_is_parity;
646 u_int8_t hd_is_hotfix;
647 u_int8_t hd_master_no;
651 u_int16_t hd_devtype;
654 u_int8_t hd_rw_attribs;
655 u_int32_t hd_start_sec;
656 } sc_hdr[GDT_MAX_HDRIVES];
658 u_int16_t sc_raw_feat;
659 u_int16_t sc_cache_feat;
664 struct cam_sim *sims[GDT_MAXBUS];
665 struct cam_path *paths[GDT_MAXBUS];
667 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
668 u_int8_t (*sc_get_status)(struct gdt_softc *);
669 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
670 void (*sc_release_event)(struct gdt_softc *);
671 void (*sc_set_sema0)(struct gdt_softc *);
672 int (*sc_test_busy)(struct gdt_softc *);
674 TAILQ_ENTRY(gdt_softc) links;
678 * A command control block, one for each corresponding command index of the
682 u_int8_t gc_scratch[GDT_SCRATCH_SZ];
685 bus_dmamap_t gc_dmamap;
690 u_int8_t gc_cmd_index;
692 #define GDT_GCF_UNUSED 0
693 #define GDT_GCF_INTERNAL 1
694 #define GDT_GCF_SCREEN 2
695 #define GDT_GCF_SCSI 3
696 #define GDT_GCF_IOCTL 4
697 SLIST_ENTRY(gdt_ccb) sle;
701 int iir_init(struct gdt_softc *);
702 void iir_free(struct gdt_softc *);
703 void iir_attach(struct gdt_softc *);
704 void iir_intr(void *arg);
706 #ifdef __CC_SUPPORTS___INLINE__
707 /* These all require correctly aligned buffers */
708 static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
709 static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
710 static __inline__ u_int16_t gdt_dec16(u_int8_t *);
711 static __inline__ u_int32_t gdt_dec32(u_int8_t *);
713 static __inline__ void
714 gdt_enc16(addr, value)
718 *(u_int16_t *)addr = htole16(value);
721 static __inline__ void
722 gdt_enc32(addr, value)
726 *(u_int32_t *)addr = htole32(value);
729 static __inline__ u_int16_t
733 return le16toh(*(u_int16_t *)addr);
736 static __inline__ u_int32_t
740 return le32toh(*(u_int32_t *)addr);
744 extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
745 extern u_int8_t gdt_polling;
747 struct cdev *gdt_make_dev(int unit);
748 void gdt_destroy_dev(struct cdev *dev);
749 void gdt_next(struct gdt_softc *gdt);
750 void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
752 gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
754 int gdt_read_event(int handle, gdt_evt_str *estr);
755 void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
756 void gdt_clear_events(void);