2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
6 * Copyright (c) 2017-2018 Panasas
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/endian.h>
38 #include <sys/errno.h>
40 #include <sys/mutex.h>
41 #include <sys/syslog.h>
44 #include <machine/bus.h>
45 #include <machine/atomic.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
50 #include <dev/smbus/smbconf.h>
52 #include "imcsmb_reg.h"
53 #include "imcsmb_var.h"
55 /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two
56 * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
57 * SMBus controllers. These are used for reading SPD data from the DIMMs, and
58 * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
59 * are very simple devices, and have limited functionality compared to
60 * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs.
62 * The publicly available documentation for the iMC SMBus controllers can be
63 * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and
64 * (Has,broad)well-Xeon, respectively:
66 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/
67 * Sandybridge xeon-e5-1600-2600-vol-2-datasheet.pdf
68 * Ivybridge xeon-e5-v2-datasheet-vol-2.pdf
69 * Haswell xeon-e5-v3-datasheet-vol-2.pdf
70 * Broadwell xeon-e5-v4-datasheet-vol-2.pdf
72 * Another useful resource is the Linux driver. It is not in the main tree.
74 * https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html
76 * The iMC SMBus controllers do not support interrupts (thus, they must be
77 * polled for IO completion). All of the iMC registers are in PCI configuration
78 * space; there is no support for PIO or MMIO. As a result, this driver does
79 * not need to perform and newbus resource manipulation.
81 * Because there are multiple SMBus controllers sharing the same PCI device,
82 * this driver is actually *two* drivers:
84 * - "imcsmb" is an smbus(4)-compliant SMBus controller driver
86 * - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of
87 * PCI config registers to a specific "imcsmb" instance.
90 /* Depending on the motherboard and firmware, the TSODs might be polled by
91 * firmware. Therefore, when this driver accesses these SMBus controllers, the
92 * firmware polling must be disabled as part of requesting the bus, and
93 * re-enabled when releasing the bus. Unfortunately, the details of how to do
94 * this are vendor-specific. Contact your motherboard vendor to get the
95 * information you need to do proper implementations.
97 * For NVDIMMs which conform to the ACPI "NFIT" standard, the ACPI firmware
98 * manages the NVDIMM; for those which pre-date the standard, the operating
99 * system interacts with the NVDIMM controller using a vendor-proprietary API
100 * over the SMBus. In that case, the NVDIMM driver would be an SMBus slave
101 * device driver, and would interface with the hardware via an SMBus controller
102 * driver such as this one.
105 /* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */
106 #define PCI_VENDOR_INTEL 0x8086
107 #define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8
108 #define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8
109 #define IMCSMB_PCI_DEV_ID_IMC0_HSX 0x2fa8
110 #define IMCSMB_PCI_DEV_ID_IMC0_BDX 0x6fa8
111 /* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */
112 #define IMCSMB_PCI_DEV_ID_IMC1_HSX 0x2f68
113 #define IMCSMB_PCI_DEV_ID_IMC1_BDX 0x6f68
115 /* There are two SMBus controllers in each device. These define the registers
116 * for each of these devices.
118 static struct imcsmb_reg_set imcsmb_regs[] = {
120 .smb_stat = IMCSMB_REG_STATUS0,
121 .smb_cmd = IMCSMB_REG_COMMAND0,
122 .smb_cntl = IMCSMB_REG_CONTROL0
125 .smb_stat = IMCSMB_REG_STATUS1,
126 .smb_cmd = IMCSMB_REG_COMMAND1,
127 .smb_cntl = IMCSMB_REG_CONTROL1
131 static struct imcsmb_pci_device {
134 } imcsmb_pci_devices[] = {
135 {IMCSMB_PCI_DEV_ID_IMC0_SBX,
136 "Intel Sandybridge Xeon iMC 0 SMBus controllers" },
137 {IMCSMB_PCI_DEV_ID_IMC0_IBX,
138 "Intel Ivybridge Xeon iMC 0 SMBus controllers" },
139 {IMCSMB_PCI_DEV_ID_IMC0_HSX,
140 "Intel Haswell Xeon iMC 0 SMBus controllers" },
141 {IMCSMB_PCI_DEV_ID_IMC1_HSX,
142 "Intel Haswell Xeon iMC 1 SMBus controllers" },
143 {IMCSMB_PCI_DEV_ID_IMC0_BDX,
144 "Intel Broadwell Xeon iMC 0 SMBus controllers" },
145 {IMCSMB_PCI_DEV_ID_IMC1_BDX,
146 "Intel Broadwell Xeon iMC 1 SMBus controllers" },
150 /* Device methods. */
151 static int imcsmb_pci_attach(device_t dev);
152 static int imcsmb_pci_detach(device_t dev);
153 static int imcsmb_pci_probe(device_t dev);
156 * device_attach() method. Set up the PCI device's softc, then explicitly create
157 * children for the actual imcsmbX controllers. Set up the child's ivars to
158 * point to the proper set of the PCI device's config registers.
160 * @author Joe Kloss, rpokala
163 * Device being attached.
166 imcsmb_pci_attach(device_t dev)
168 struct imcsmb_pci_softc *sc;
173 /* Initialize private state */
174 sc = device_get_softc(dev);
178 /* Create the imcsmbX children */
179 for (unit = 0; unit < 2; unit++) {
180 child = device_add_child(dev, "imcsmb", -1);
182 /* Nothing has been allocated, so there's no cleanup. */
183 device_printf(dev, "Child imcsmb not added\n");
187 /* Set the child's ivars to point to the appropriate set of
188 * the PCI device's registers.
190 device_set_ivars(child, &imcsmb_regs[unit]);
193 /* Attach the imcsmbX children. */
194 if ((rc = bus_generic_attach(dev)) != 0) {
195 device_printf(dev, "failed to attach children: %d\n", rc);
204 * device_detach() method. attach() didn't do any allocations, so all that's
205 * needed here is to free up any downstream drivers and children.
210 * Device being detached.
213 imcsmb_pci_detach(device_t dev)
217 /* Detach any attached drivers */
218 rc = bus_generic_detach(dev);
220 /* Remove all children */
221 rc = device_delete_children(dev);
228 * device_probe() method. Look for the right PCI vendor/device IDs.
230 * @author Joe Kloss, rpokala
233 * Device being probed.
236 imcsmb_pci_probe(device_t dev)
238 struct imcsmb_pci_device *pci_device;
244 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL) {
248 pci_dev_id = pci_get_device(dev);
249 for (pci_device = imcsmb_pci_devices;
250 pci_device->name != NULL;
252 if (pci_dev_id == pci_device->id) {
253 device_set_desc(dev, pci_device->name);
254 rc = BUS_PROBE_DEFAULT;
264 * Invoked via smbus_callback() -> imcsmb_callback(); clear the semaphore, and
265 * re-enable motherboard-specific DIMM temperature monitoring if needed. This
266 * gets called after the transaction completes.
271 * The device whose busses to release.
274 imcsmb_pci_release_bus(device_t dev)
276 struct imcsmb_pci_softc *sc;
278 sc = device_get_softc(dev);
281 * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO RE-ENABLE DIMM
282 * TEMPERATURE MONITORING HERE.
285 atomic_store_rel_int(&sc->semaphore, 0);
289 * Invoked via smbus_callback() -> imcsmb_callback(); set the semaphore, and
290 * disable motherboard-specific DIMM temperature monitoring if needed. This gets
291 * called before the transaction starts.
296 * The device whose busses to request.
299 imcsmb_pci_request_bus(device_t dev)
301 struct imcsmb_pci_softc *sc;
304 sc = device_get_softc(dev);
307 /* We don't want to block. Use a simple test-and-set semaphore to
310 if (atomic_cmpset_acq_int(&sc->semaphore, 0, 1) == 0) {
315 * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO DISABLE DIMM
316 * TEMPERATURE MONITORING HERE.
322 /* Our device class */
323 static devclass_t imcsmb_pci_devclass;
326 static device_method_t imcsmb_pci_methods[] = {
327 /* Device interface */
328 DEVMETHOD(device_attach, imcsmb_pci_attach),
329 DEVMETHOD(device_detach, imcsmb_pci_detach),
330 DEVMETHOD(device_probe, imcsmb_pci_probe),
335 static driver_t imcsmb_pci_driver = {
336 .name = "imcsmb_pci",
337 .methods = imcsmb_pci_methods,
338 .size = sizeof(struct imcsmb_pci_softc),
341 DRIVER_MODULE(imcsmb_pci, pci, imcsmb_pci_driver, imcsmb_pci_devclass, 0, 0);
342 MODULE_DEPEND(imcsmb_pci, pci, 1, 1, 1);
343 MODULE_VERSION(imcsmb_pci, 1);
345 /* vi: set ts=8 sw=4 sts=8 noet: */