2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
6 * Copyright (c) 2017-2018 Panasas
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef _DEV__IMCSMB__IMCSMB_REG_H_
34 #define _DEV__IMCSMB__IMCSMB_REG_H_
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/errno.h>
43 #include <sys/mutex.h>
44 #include <sys/syslog.h>
47 #include <machine/bus.h>
48 #include <machine/atomic.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
53 #include <dev/smbus/smbconf.h>
55 /* Intel (Sandy,Ivy)bridge and (Has,Broad)well CPUs have integrated memory
56 * controllers (iMCs), each of which having up to two SMBus controllers. They
57 * are programmed via sets of registers in the same PCI device, which are
58 * identical other than the register numbers.
60 * The full documentation for these registers can be found in volume two of the
61 * datasheets for the CPUs. Refer to the links in imcsmb_pci.c
64 #define IMCSMB_REG_STATUS0 0x0180
65 #define IMCSMB_REG_STATUS1 0x0190
66 #define IMCSMB_STATUS_BUSY_BIT 0x10000000
67 #define IMCSMB_STATUS_BUS_ERROR_BIT 0x20000000
68 #define IMCSMB_STATUS_WRITE_DATA_DONE 0x40000000
69 #define IMCSMB_STATUS_READ_DATA_VALID 0x80000000
71 #define IMCSMB_REG_COMMAND0 0x0184
72 #define IMCSMB_REG_COMMAND1 0x0194
73 #define IMCSMB_CMD_WORD_ACCESS 0x20000000
74 #define IMCSMB_CMD_WRITE_BIT 0x08000000
75 #define IMCSMB_CMD_TRIGGER_BIT 0x80000000
77 #define IMCSMB_REG_CONTROL0 0x0188
78 #define IMCSMB_REG_CONTROL1 0x0198
79 #define IMCSMB_CNTL_POLL_EN 0x00000100
80 #define IMCSMB_CNTL_CLK_OVERRIDE 0x08000000
81 #define IMCSMB_CNTL_DTI_MASK 0xf0000000
82 #define IMCSMB_CNTL_WRITE_DISABLE_BIT 0x04000000
84 #endif /* _DEV__IMCSMB__IMCSMB_REG_H_ */
86 /* vi: set ts=8 sw=4 sts=8 noet: */