2 * Copyright (c) 2016 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
39 #include <machine/bus.h>
40 #include <machine/resource.h>
42 #include <dev/spibus/spi.h>
43 #include <dev/spibus/spibusvar.h>
45 #include <contrib/dev/acpica/include/acpi.h>
46 #include <contrib/dev/acpica/include/accommon.h>
48 #include <dev/acpica/acpivar.h>
50 #include "spibus_if.h"
53 * Macros for driver mutex locking
55 #define INTELSPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
56 #define INTELSPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
57 #define INTELSPI_LOCK_INIT(_sc) \
58 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
60 #define INTELSPI_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
61 #define INTELSPI_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
62 #define INTELSPI_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
64 #define INTELSPI_WRITE(_sc, _off, _val) \
65 bus_write_4((_sc)->sc_mem_res, (_off), (_val))
66 #define INTELSPI_READ(_sc, _off) \
67 bus_read_4((_sc)->sc_mem_res, (_off))
69 #define INTELSPI_BUSY 0x1
70 #define TX_FIFO_THRESHOLD 2
71 #define RX_FIFO_THRESHOLD 2
72 #define CLOCK_DIV_10MHZ 5
73 #define DATA_SIZE_8BITS 8
78 #define INTELSPI_SSPREG_SSCR0 0x0
79 #define SSCR0_SCR(n) (((n) - 1) << 8)
80 #define SSCR0_SSE (1 << 7)
81 #define SSCR0_FRF_SPI (0 << 4)
82 #define SSCR0_DSS(n) (((n) - 1) << 0)
83 #define INTELSPI_SSPREG_SSCR1 0x4
84 #define SSCR1_TINTE (1 << 19)
85 #define SSCR1_RFT(n) (((n) - 1) << 10)
86 #define SSCR1_RFT_MASK (0xf << 10)
87 #define SSCR1_TFT(n) (((n) - 1) << 6)
88 #define SSCR1_SPI_SPH (1 << 4)
89 #define SSCR1_SPI_SPO (1 << 3)
90 #define SSCR1_MODE_MASK (SSCR1_SPI_SPO | SSCR1_SPI_SPH)
91 #define SSCR1_MODE_0 (0)
92 #define SSCR1_MODE_1 (SSCR1_SPI_SPH)
93 #define SSCR1_MODE_2 (SSCR1_SPI_SPO)
94 #define SSCR1_MODE_3 (SSCR1_SPI_SPO | SSCR1_SPI_SPH)
95 #define SSCR1_TIE (1 << 1)
96 #define SSCR1_RIE (1 << 0)
97 #define INTELSPI_SSPREG_SSSR 0x8
98 #define SSSR_RFL_MASK (0xf << 12)
99 #define SSSR_TFL_MASK (0xf << 8)
100 #define SSSR_RNE (1 << 3)
101 #define SSSR_TNF (1 << 2)
102 #define INTELSPI_SSPREG_SSITR 0xC
103 #define INTELSPI_SSPREG_SSDR 0x10
104 #define INTELSPI_SSPREG_SSTO 0x28
105 #define INTELSPI_SSPREG_SSPSP 0x2C
106 #define INTELSPI_SSPREG_SSTSA 0x30
107 #define INTELSPI_SSPREG_SSRSA 0x34
108 #define INTELSPI_SSPREG_SSTSS 0x38
109 #define INTELSPI_SSPREG_SSACD 0x3C
110 #define INTELSPI_SSPREG_ITF 0x40
111 #define INTELSPI_SSPREG_SITF 0x44
112 #define INTELSPI_SSPREG_SIRF 0x48
113 #define INTELSPI_SSPREG_PRV_CLOCK_PARAMS 0x400
114 #define INTELSPI_SSPREG_RESETS 0x404
115 #define INTELSPI_SSPREG_GENERAL 0x408
116 #define INTELSPI_SSPREG_SSP_REG 0x40C
117 #define INTELSPI_SSPREG_SPI_CS_CTRL 0x418
118 #define SPI_CS_CTRL_CS_MASK (3)
119 #define SPI_CS_CTRL_SW_MODE (1 << 0)
120 #define SPI_CS_CTRL_HW_MODE (1 << 0)
121 #define SPI_CS_CTRL_CS_HIGH (1 << 1)
122 #define SPI_CS_CTRL_CS_LOW (0 << 1)
124 struct intelspi_softc {
125 ACPI_HANDLE sc_handle;
129 struct resource *sc_mem_res;
131 struct resource *sc_irq_res;
133 struct spi_command *sc_cmd;
140 static int intelspi_probe(device_t dev);
141 static int intelspi_attach(device_t dev);
142 static int intelspi_detach(device_t dev);
143 static void intelspi_intr(void *);
146 intelspi_txfifo_full(struct intelspi_softc *sc)
150 INTELSPI_ASSERT_LOCKED(sc);
152 sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
160 intelspi_rxfifo_empty(struct intelspi_softc *sc)
164 INTELSPI_ASSERT_LOCKED(sc);
166 sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
174 intelspi_fill_tx_fifo(struct intelspi_softc *sc)
176 struct spi_command *cmd;
180 INTELSPI_ASSERT_LOCKED(sc);
183 while (sc->sc_written < sc->sc_len &&
184 !intelspi_txfifo_full(sc)) {
185 data = (uint8_t *)cmd->tx_cmd;
186 written = sc->sc_written++;
188 if (written >= cmd->tx_cmd_sz) {
189 data = (uint8_t *)cmd->tx_data;
190 written -= cmd->tx_cmd_sz;
192 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSDR, data[written]);
197 intelspi_drain_rx_fifo(struct intelspi_softc *sc)
199 struct spi_command *cmd;
203 INTELSPI_ASSERT_LOCKED(sc);
206 while (sc->sc_read < sc->sc_len &&
207 !intelspi_rxfifo_empty(sc)) {
208 data = (uint8_t *)cmd->rx_cmd;
209 read = sc->sc_read++;
210 if (read >= cmd->rx_cmd_sz) {
211 data = (uint8_t *)cmd->rx_data;
212 read -= cmd->rx_cmd_sz;
214 data[read] = INTELSPI_READ(sc, INTELSPI_SSPREG_SSDR) & 0xff;
219 intelspi_transaction_done(struct intelspi_softc *sc)
224 INTELSPI_ASSERT_LOCKED(sc);
226 if (sc->sc_written != sc->sc_len ||
227 sc->sc_read != sc->sc_len)
230 sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
231 txfifo_empty = ((sssr & SSSR_TFL_MASK) == 0) &&
234 if (txfifo_empty && !(sssr & SSSR_RNE))
241 intelspi_transact(struct intelspi_softc *sc)
244 INTELSPI_ASSERT_LOCKED(sc);
246 /* TX - Fill up the FIFO. */
247 intelspi_fill_tx_fifo(sc);
249 /* RX - Drain the FIFO. */
250 intelspi_drain_rx_fifo(sc);
252 /* Check for end of transfer. */
253 return intelspi_transaction_done(sc);
257 intelspi_intr(void *arg)
259 struct intelspi_softc *sc;
262 sc = (struct intelspi_softc *)arg;
265 if ((sc->sc_flags & INTELSPI_BUSY) == 0) {
270 /* Check if SSP if off */
271 reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
272 if (reg == 0xffffffffU) {
277 /* Check for end of transfer. */
278 if (intelspi_transact(sc)) {
279 /* Disable interrupts */
280 reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
281 reg &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);
282 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg);
290 intelspi_init(struct intelspi_softc *sc)
294 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, 0);
296 /* Manual CS control */
297 reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SPI_CS_CTRL);
298 reg &= ~(SPI_CS_CTRL_CS_MASK);
299 reg |= (SPI_CS_CTRL_SW_MODE | SPI_CS_CTRL_CS_HIGH);
300 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SPI_CS_CTRL, reg);
302 /* Set TX/RX FIFO IRQ threshold levels */
303 reg = SSCR1_TFT(TX_FIFO_THRESHOLD) | SSCR1_RFT(RX_FIFO_THRESHOLD);
305 * Set SPI mode. This should be part of transaction or sysctl
308 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg);
311 * Parent clock on Minowboard Turbot is 50MHz
312 * divide it by 5 to set to more or less reasonable
313 * value. But this should be part of transaction config
316 reg = SSCR0_SCR(CLOCK_DIV_10MHZ);
317 /* Put SSP in SPI mode */
318 reg |= SSCR0_FRF_SPI;
320 reg |= SSCR0_DSS(DATA_SIZE_8BITS);
323 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, reg);
327 intelspi_set_cs(struct intelspi_softc *sc, int level)
331 reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SPI_CS_CTRL);
332 reg &= ~(SPI_CS_CTRL_CS_MASK);
333 reg |= SPI_CS_CTRL_SW_MODE;
335 if (level == CS_HIGH)
336 reg |= SPI_CS_CTRL_CS_HIGH;
338 reg |= SPI_CS_CTRL_CS_LOW;
340 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SPI_CS_CTRL, reg);
344 intelspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
346 struct intelspi_softc *sc;
350 sc = device_get_softc(dev);
353 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
354 ("TX/RX command sizes should be equal"));
355 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
356 ("TX/RX data sizes should be equal"));
360 /* If the controller is in use wait until it is available. */
361 while (sc->sc_flags & INTELSPI_BUSY) {
362 err = mtx_sleep(dev, &sc->sc_mtx, 0, "intelspi", 0);
369 /* Now we have control over SPI controller. */
370 sc->sc_flags = INTELSPI_BUSY;
372 /* Save a pointer to the SPI command. */
376 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
379 intelspi_set_cs(sc, CS_LOW);
380 /* Transfer as much as possible to FIFOs */
381 if (!intelspi_transact(sc)) {
382 /* If FIFO is not large enough - enable interrupts */
383 sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
384 sscr1 |= (SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);
385 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1);
387 /* and wait for transaction to complete */
388 err = mtx_sleep(dev, &sc->sc_mtx, 0, "intelspi", hz * 2);
392 intelspi_set_cs(sc, CS_HIGH);
394 /* Clear transaction details */
400 /* Make sure the SPI engine and interrupts are disabled. */
401 sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
402 sscr1 &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);
403 INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1);
405 /* Release the controller and wakeup the next thread waiting for it. */
411 * Check for transfer timeout. The SPI controller doesn't
414 if (err == EWOULDBLOCK) {
415 device_printf(sc->sc_dev, "transfer timeout\n");
423 intelspi_probe(device_t dev)
425 static char *gpio_ids[] = { "80860F0E", NULL };
428 if (acpi_disabled("spi") )
430 rv = ACPI_ID_PROBE(device_get_parent(dev), dev, gpio_ids, NULL);
432 device_set_desc(dev, "Intel SPI Controller");
437 intelspi_attach(device_t dev)
439 struct intelspi_softc *sc;
441 sc = device_get_softc(dev);
443 sc->sc_handle = acpi_get_handle(dev);
445 INTELSPI_LOCK_INIT(sc);
448 sc->sc_mem_res = bus_alloc_resource_any(sc->sc_dev,
449 SYS_RES_MEMORY, &sc->sc_mem_rid, RF_ACTIVE);
450 if (sc->sc_mem_res == NULL) {
451 device_printf(dev, "can't allocate memory resource\n");
456 sc->sc_irq_res = bus_alloc_resource_any(sc->sc_dev,
457 SYS_RES_IRQ, &sc->sc_irq_rid, RF_ACTIVE);
458 if (sc->sc_irq_res == NULL) {
459 device_printf(dev, "can't allocate IRQ resource\n");
463 /* Hook up our interrupt handler. */
464 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
465 NULL, intelspi_intr, sc, &sc->sc_irq_ih)) {
466 device_printf(dev, "cannot setup the interrupt handler\n");
472 device_add_child(dev, "spibus", -1);
474 return (bus_generic_attach(dev));
477 INTELSPI_LOCK_DESTROY(sc);
479 if (sc->sc_mem_res != NULL)
480 bus_release_resource(dev, SYS_RES_MEMORY,
481 sc->sc_mem_rid, sc->sc_mem_res);
483 if (sc->sc_irq_res != NULL)
484 bus_release_resource(dev, SYS_RES_IRQ,
485 sc->sc_irq_rid, sc->sc_irq_res);
491 intelspi_detach(device_t dev)
493 struct intelspi_softc *sc;
495 sc = device_get_softc(dev);
497 INTELSPI_LOCK_DESTROY(sc);
500 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_ih);
502 if (sc->sc_mem_res != NULL)
503 bus_release_resource(dev, SYS_RES_MEMORY,
504 sc->sc_mem_rid, sc->sc_mem_res);
506 if (sc->sc_irq_res != NULL)
507 bus_release_resource(dev, SYS_RES_IRQ,
508 sc->sc_irq_rid, sc->sc_irq_res);
510 return (bus_generic_detach(dev));
513 static device_method_t intelspi_methods[] = {
514 /* Device interface */
515 DEVMETHOD(device_probe, intelspi_probe),
516 DEVMETHOD(device_attach, intelspi_attach),
517 DEVMETHOD(device_detach, intelspi_detach),
520 DEVMETHOD(spibus_transfer, intelspi_transfer),
525 static driver_t intelspi_driver = {
528 sizeof(struct intelspi_softc),
531 static devclass_t intelspi_devclass;
532 DRIVER_MODULE(intelspi, acpi, intelspi_driver, intelspi_devclass, 0, 0);
533 MODULE_DEPEND(intelspi, acpi, 1, 1, 1);
534 MODULE_DEPEND(intelspi, spibus, 1, 1, 1);