2 * Copyright (c) 1998, 1999 Takanori Watanabe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <machine/bus.h>
39 #include <dev/smbus/smbconf.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/intpm/intpmreg.h>
46 #include <dev/amdsbwd/amd_chipset.h>
48 #include "opt_intpm.h"
52 struct resource *io_res;
53 struct resource *irq_res;
64 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock)
65 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock)
66 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED)
68 static int intsmb_probe(device_t);
69 static int intsmb_attach(device_t);
70 static int intsmb_detach(device_t);
71 static int intsmb_intr(struct intsmb_softc *sc);
72 static int intsmb_slvintr(struct intsmb_softc *sc);
73 static void intsmb_alrintr(struct intsmb_softc *sc);
74 static int intsmb_callback(device_t dev, int index, void *data);
75 static int intsmb_quick(device_t dev, u_char slave, int how);
76 static int intsmb_sendb(device_t dev, u_char slave, char byte);
77 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
78 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
79 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
80 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
81 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
82 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
83 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
84 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
85 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr);
86 static int intsmb_stop(struct intsmb_softc *sc);
87 static int intsmb_stop_poll(struct intsmb_softc *sc);
88 static int intsmb_free(struct intsmb_softc *sc);
89 static void intsmb_rawintr(void *arg);
91 const struct intsmb_device {
93 const char *description;
94 } intsmb_products[] = {
95 { 0x71138086, "Intel PIIX4 SMBUS Interface" },
96 { 0x719b8086, "Intel PIIX4 SMBUS Interface" },
98 /* Not a good idea yet, this stops isab0 functioning */
99 { 0x02001166, "ServerWorks OSB4" },
101 { 0x43721002, "ATI IXP400 SMBus Controller" },
102 { AMDSB_SMBUS_DEVID, "AMD SB600/7xx/8xx/9xx SMBus Controller" },
103 { AMDFCH_SMBUS_DEVID, "AMD FCH SMBus Controller" },
104 { AMDCZ_SMBUS_DEVID, "AMD FCH SMBus Controller" },
105 { HYGONCZ_SMBUS_DEVID, "Hygon FCH SMBus Controller" },
109 intsmb_probe(device_t dev)
111 const struct intsmb_device *isd;
115 devid = pci_get_devid(dev);
116 for (i = 0; i < nitems(intsmb_products); i++) {
117 isd = &intsmb_products[i];
118 if (isd->devid == devid) {
119 device_set_desc(dev, isd->description);
120 return (BUS_PROBE_DEFAULT);
127 amd_pmio_read(struct resource *res, uint8_t reg)
129 bus_write_1(res, 0, reg); /* Index */
130 return (bus_read_1(res, 1)); /* Data */
134 sb8xx_attach(device_t dev)
136 static const int AMDSB_SMBIO_WIDTH = 0x10;
137 struct intsmb_softc *sc;
138 struct resource *res;
146 sc = device_get_softc(dev);
148 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX,
151 device_printf(dev, "bus_set_resource for PM IO failed\n");
154 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
157 device_printf(dev, "bus_alloc_resource for PM IO failed\n");
161 devid = pci_get_devid(dev);
162 revid = pci_get_revid(dev);
163 if (devid == AMDSB_SMBUS_DEVID ||
164 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
165 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) {
166 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1);
168 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN);
169 enabled = (addr & AMDSB8_SMBUS_EN) != 0;
170 addr &= AMDSB8_SMBUS_ADDR_MASK;
172 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0);
173 enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
174 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1);
178 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
179 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
182 device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n");
187 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr,
190 device_printf(dev, "bus_set_resource for SMBus IO failed\n");
193 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
195 if (sc->io_res == NULL) {
196 device_printf(dev, "Could not allocate I/O space\n");
204 intsmb_release_resources(device_t dev)
206 struct intsmb_softc *sc = device_get_softc(dev);
209 device_delete_child(dev, sc->smbus);
211 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
213 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
215 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid,
217 mtx_destroy(&sc->lock);
221 intsmb_attach(device_t dev)
223 struct intsmb_softc *sc = device_get_softc(dev);
224 int error, rid, value;
230 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
233 switch (pci_get_devid(dev)) {
234 #ifndef NO_CHANGE_PCICONF
235 case 0x71138086: /* Intel 82371AB */
236 case 0x719b8086: /* Intel 82443MX */
237 /* Changing configuration is allowed. */
241 case AMDSB_SMBUS_DEVID:
242 if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID)
245 case AMDFCH_SMBUS_DEVID:
246 case AMDCZ_SMBUS_DEVID:
247 case HYGONCZ_SMBUS_DEVID:
253 error = sb8xx_attach(dev);
260 sc->io_rid = PCI_BASE_ADDR_SMB;
261 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
263 if (sc->io_res == NULL) {
264 device_printf(dev, "Could not allocate I/O space\n");
270 pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
271 pci_write_config(dev, PCI_HST_CFG_SMB,
272 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
274 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
275 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
276 intr = value & PCI_INTR_SMB_MASK;
278 case PCI_INTR_SMB_SMI:
281 case PCI_INTR_SMB_IRQ9:
284 case PCI_INTR_SMB_IRQ_PCI:
291 device_printf(dev, "intr %s %s ", str,
292 sc->poll == 0 ? "enabled" : "disabled");
293 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
295 if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
297 "using polling mode when configured interrupt is SMI\n");
304 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
305 device_printf(dev, "Unsupported interrupt mode\n");
313 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
315 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
316 RF_SHAREABLE | RF_ACTIVE);
317 if (sc->irq_res == NULL) {
318 device_printf(dev, "Could not allocate irq\n");
323 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
324 NULL, intsmb_rawintr, sc, &sc->irq_hand);
326 device_printf(dev, "Failed to map intr\n");
332 sc->smbus = device_add_child(dev, "smbus", -1);
333 if (sc->smbus == NULL) {
334 device_printf(dev, "failed to add smbus child\n");
338 error = device_probe_and_attach(sc->smbus);
340 device_printf(dev, "failed to probe+attach smbus child\n");
346 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
351 intsmb_release_resources(dev);
356 intsmb_detach(device_t dev)
360 error = bus_generic_detach(dev);
362 device_printf(dev, "bus detach failed\n");
366 intsmb_release_resources(dev);
371 intsmb_rawintr(void *arg)
373 struct intsmb_softc *sc = arg;
382 intsmb_callback(device_t dev, int index, void *data)
387 case SMB_REQUEST_BUS:
389 case SMB_RELEASE_BUS:
398 /* Counterpart of smbtx_smb_free(). */
400 intsmb_free(struct intsmb_softc *sc)
403 INTSMB_LOCK_ASSERT(sc);
404 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
406 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
412 /* Disable Interrupt in slave part. */
414 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
416 /* Reset INTR Flag to prepare INTR. */
417 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
418 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
419 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
424 intsmb_intr(struct intsmb_softc *sc)
428 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
429 if (status & PIIX4_SMBHSTSTAT_BUSY)
432 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
433 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
435 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
436 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
437 tmp & ~PIIX4_SMBHSTCNT_INTREN);
444 return (1); /* Not Completed */
448 intsmb_slvintr(struct intsmb_softc *sc)
452 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
453 if (status & PIIX4_SMBSLVSTS_BUSY)
455 if (status & PIIX4_SMBSLVSTS_ALART)
457 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
458 | PIIX4_SMBSLVSTS_SDW1)) {
461 /* Reset Status Register */
462 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
463 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
464 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
469 intsmb_alrintr(struct intsmb_softc *sc)
477 /* Stop generating INTR from ALART. */
478 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
480 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
481 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
485 /* Ask bus who asserted it and then ask it what's the matter. */
487 error = intsmb_free(sc);
491 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
492 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
493 error = intsmb_stop_poll(sc);
495 device_printf(sc->dev, "ALART: ERROR\n");
497 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
498 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
501 /* Re-enable INTR from ALART. */
502 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
503 slvcnt | PIIX4_SMBSLVCNT_ALTEN);
509 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
513 INTSMB_LOCK_ASSERT(sc);
514 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
517 tmp |= PIIX4_SMBHSTCNT_START;
519 /* While not in autoconfiguration enable interrupts. */
520 if (!sc->poll && !cold && !nointr)
521 tmp |= PIIX4_SMBHSTCNT_INTREN;
522 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
526 intsmb_error(device_t dev, int status)
531 * PIIX4_SMBHSTSTAT_ERR can mean either of
532 * - SMB_ENOACK ("Unclaimed cycle"),
533 * - SMB_ETIMEOUT ("Host device time-out"),
534 * - SMB_EINVAL ("Illegal command field").
535 * SMB_ENOACK seems to be most typical.
537 if (status & PIIX4_SMBHSTSTAT_ERR)
539 if (status & PIIX4_SMBHSTSTAT_BUSC)
541 if (status & PIIX4_SMBHSTSTAT_FAIL)
544 if (error != 0 && bootverbose)
545 device_printf(dev, "error = %d, status = %#x\n", error, status);
553 * Polling is not encouraged because it requires waiting for the
554 * device if it is busy.
555 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
559 intsmb_stop_poll(struct intsmb_softc *sc)
561 int error, i, status, tmp;
563 INTSMB_LOCK_ASSERT(sc);
565 /* First, wait for busy to be set. */
566 for (i = 0; i < 0x7fff; i++)
567 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
568 PIIX4_SMBHSTSTAT_BUSY)
571 /* Wait for busy to clear. */
572 for (i = 0; i < 0x7fff; i++) {
573 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
574 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
576 error = intsmb_error(sc->dev, status);
581 /* Timed out waiting for busy to clear. */
583 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
584 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
585 return (SMB_ETIMEOUT);
589 * Wait for completion and return result.
592 intsmb_stop(struct intsmb_softc *sc)
596 INTSMB_LOCK_ASSERT(sc);
598 if (sc->poll || cold)
599 /* So that it can use device during device probe on SMBus. */
600 return (intsmb_stop_poll(sc));
602 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8);
604 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
605 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
606 error = intsmb_error(sc->dev, status);
607 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
608 device_printf(sc->dev, "unknown cause why?\n");
610 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
611 PIIX4_SMBSLVCNT_ALTEN);
617 /* Timeout Procedure. */
620 /* Re-enable suppressed interrupt from slave part. */
621 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
622 if (error == EWOULDBLOCK)
623 return (SMB_ETIMEOUT);
629 intsmb_quick(device_t dev, u_char slave, int how)
631 struct intsmb_softc *sc = device_get_softc(dev);
637 /* Quick command is part of Address, I think. */
650 error = intsmb_free(sc);
655 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
656 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0);
657 error = intsmb_stop(sc);
663 intsmb_sendb(device_t dev, u_char slave, char byte)
665 struct intsmb_softc *sc = device_get_softc(dev);
669 error = intsmb_free(sc);
674 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
675 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
676 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
677 error = intsmb_stop(sc);
683 intsmb_recvb(device_t dev, u_char slave, char *byte)
685 struct intsmb_softc *sc = device_get_softc(dev);
689 error = intsmb_free(sc);
694 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
695 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
696 error = intsmb_stop(sc);
698 #ifdef RECV_IS_IN_CMD
700 * Linux SMBus stuff also troubles
701 * Because Intel's datasheet does not make clear.
703 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
705 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
713 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
715 struct intsmb_softc *sc = device_get_softc(dev);
719 error = intsmb_free(sc);
724 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
725 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
726 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
727 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
728 error = intsmb_stop(sc);
734 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
736 struct intsmb_softc *sc = device_get_softc(dev);
740 error = intsmb_free(sc);
745 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
746 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
747 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
748 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
749 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
750 error = intsmb_stop(sc);
756 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
758 struct intsmb_softc *sc = device_get_softc(dev);
762 error = intsmb_free(sc);
767 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
768 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
769 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
770 error = intsmb_stop(sc);
772 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
778 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
780 struct intsmb_softc *sc = device_get_softc(dev);
784 error = intsmb_free(sc);
789 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
790 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
791 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
792 error = intsmb_stop(sc);
794 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
795 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
802 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
805 return (SMB_ENOTSUPP);
809 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
811 struct intsmb_softc *sc = device_get_softc(dev);
814 if (count > SMBBLOCKTRANS_MAX || count == 0)
818 error = intsmb_free(sc);
824 /* Reset internal array index. */
825 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
827 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
828 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
829 for (i = 0; i < count; i++)
830 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
831 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
832 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
833 error = intsmb_stop(sc);
839 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
841 struct intsmb_softc *sc = device_get_softc(dev);
846 error = intsmb_free(sc);
852 /* Reset internal array index. */
853 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
855 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
856 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
857 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
858 error = intsmb_stop(sc);
860 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
861 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
863 for (i = 0; i < nread; i++)
864 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
872 static devclass_t intsmb_devclass;
874 static device_method_t intsmb_methods[] = {
875 /* Device interface */
876 DEVMETHOD(device_probe, intsmb_probe),
877 DEVMETHOD(device_attach, intsmb_attach),
878 DEVMETHOD(device_detach, intsmb_detach),
880 /* SMBus interface */
881 DEVMETHOD(smbus_callback, intsmb_callback),
882 DEVMETHOD(smbus_quick, intsmb_quick),
883 DEVMETHOD(smbus_sendb, intsmb_sendb),
884 DEVMETHOD(smbus_recvb, intsmb_recvb),
885 DEVMETHOD(smbus_writeb, intsmb_writeb),
886 DEVMETHOD(smbus_writew, intsmb_writew),
887 DEVMETHOD(smbus_readb, intsmb_readb),
888 DEVMETHOD(smbus_readw, intsmb_readw),
889 DEVMETHOD(smbus_pcall, intsmb_pcall),
890 DEVMETHOD(smbus_bwrite, intsmb_bwrite),
891 DEVMETHOD(smbus_bread, intsmb_bread),
896 static driver_t intsmb_driver = {
899 sizeof(struct intsmb_softc),
902 DRIVER_MODULE_ORDERED(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0,
904 DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0);
905 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
906 MODULE_VERSION(intsmb, 1);
907 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, intpm, intsmb_products,
908 nitems(intsmb_products));