2 * Copyright (c) 1998, 1999 Takanori Watanabe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <machine/bus.h>
39 #include <dev/smbus/smbconf.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/intpm/intpmreg.h>
46 #include <dev/amdsbwd/amd_chipset.h>
48 #include "opt_intpm.h"
52 struct resource *io_res;
53 struct resource *irq_res;
64 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock)
65 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock)
66 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED)
68 static int intsmb_probe(device_t);
69 static int intsmb_attach(device_t);
70 static int intsmb_detach(device_t);
71 static int intsmb_intr(struct intsmb_softc *sc);
72 static int intsmb_slvintr(struct intsmb_softc *sc);
73 static void intsmb_alrintr(struct intsmb_softc *sc);
74 static int intsmb_callback(device_t dev, int index, void *data);
75 static int intsmb_quick(device_t dev, u_char slave, int how);
76 static int intsmb_sendb(device_t dev, u_char slave, char byte);
77 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
78 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
79 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
80 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
81 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
82 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
83 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
84 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
85 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr);
86 static int intsmb_stop(struct intsmb_softc *sc);
87 static int intsmb_stop_poll(struct intsmb_softc *sc);
88 static int intsmb_free(struct intsmb_softc *sc);
89 static void intsmb_rawintr(void *arg);
91 const struct intsmb_device {
93 const char *description;
94 } intsmb_products[] = {
95 { 0x71138086, "Intel PIIX4 SMBUS Interface" },
96 { 0x719b8086, "Intel PIIX4 SMBUS Interface" },
98 /* Not a good idea yet, this stops isab0 functioning */
99 { 0x02001166, "ServerWorks OSB4" },
101 { 0x43721002, "ATI IXP400 SMBus Controller" },
102 { AMDSB_SMBUS_DEVID, "AMD SB600/7xx/8xx/9xx SMBus Controller" },
103 { AMDFCH_SMBUS_DEVID, "AMD FCH SMBus Controller" },
104 { AMDCZ_SMBUS_DEVID, "AMD FCH SMBus Controller" },
108 intsmb_probe(device_t dev)
110 const struct intsmb_device *isd;
114 devid = pci_get_devid(dev);
115 for (i = 0; i < nitems(intsmb_products); i++) {
116 isd = &intsmb_products[i];
117 if (isd->devid == devid) {
118 device_set_desc(dev, isd->description);
119 return (BUS_PROBE_DEFAULT);
126 amd_pmio_read(struct resource *res, uint8_t reg)
128 bus_write_1(res, 0, reg); /* Index */
129 return (bus_read_1(res, 1)); /* Data */
133 sb8xx_attach(device_t dev)
135 static const int AMDSB_SMBIO_WIDTH = 0x10;
136 struct intsmb_softc *sc;
137 struct resource *res;
145 sc = device_get_softc(dev);
147 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX,
150 device_printf(dev, "bus_set_resource for PM IO failed\n");
153 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
156 device_printf(dev, "bus_alloc_resource for PM IO failed\n");
160 devid = pci_get_devid(dev);
161 revid = pci_get_revid(dev);
162 if (devid == AMDSB_SMBUS_DEVID ||
163 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
164 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) {
165 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1);
167 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN);
168 enabled = (addr & AMDSB8_SMBUS_EN) != 0;
169 addr &= AMDSB8_SMBUS_ADDR_MASK;
171 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0);
172 enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
173 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1);
177 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
178 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
181 device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n");
186 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr,
189 device_printf(dev, "bus_set_resource for SMBus IO failed\n");
192 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
194 if (sc->io_res == NULL) {
195 device_printf(dev, "Could not allocate I/O space\n");
203 intsmb_release_resources(device_t dev)
205 struct intsmb_softc *sc = device_get_softc(dev);
208 device_delete_child(dev, sc->smbus);
210 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
214 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid,
216 mtx_destroy(&sc->lock);
220 intsmb_attach(device_t dev)
222 struct intsmb_softc *sc = device_get_softc(dev);
223 int error, rid, value;
229 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
232 switch (pci_get_devid(dev)) {
233 #ifndef NO_CHANGE_PCICONF
234 case 0x71138086: /* Intel 82371AB */
235 case 0x719b8086: /* Intel 82443MX */
236 /* Changing configuration is allowed. */
240 case AMDSB_SMBUS_DEVID:
241 if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID)
244 case AMDFCH_SMBUS_DEVID:
245 case AMDCZ_SMBUS_DEVID:
251 error = sb8xx_attach(dev);
258 sc->io_rid = PCI_BASE_ADDR_SMB;
259 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
261 if (sc->io_res == NULL) {
262 device_printf(dev, "Could not allocate I/O space\n");
268 pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
269 pci_write_config(dev, PCI_HST_CFG_SMB,
270 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
272 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
273 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
274 intr = value & PCI_INTR_SMB_MASK;
276 case PCI_INTR_SMB_SMI:
279 case PCI_INTR_SMB_IRQ9:
282 case PCI_INTR_SMB_IRQ_PCI:
289 device_printf(dev, "intr %s %s ", str,
290 sc->poll == 0 ? "enabled" : "disabled");
291 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
293 if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
295 "using polling mode when configured interrupt is SMI\n");
302 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
303 device_printf(dev, "Unsupported interrupt mode\n");
311 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
313 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
314 RF_SHAREABLE | RF_ACTIVE);
315 if (sc->irq_res == NULL) {
316 device_printf(dev, "Could not allocate irq\n");
321 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
322 NULL, intsmb_rawintr, sc, &sc->irq_hand);
324 device_printf(dev, "Failed to map intr\n");
330 sc->smbus = device_add_child(dev, "smbus", -1);
331 if (sc->smbus == NULL) {
332 device_printf(dev, "failed to add smbus child\n");
336 error = device_probe_and_attach(sc->smbus);
338 device_printf(dev, "failed to probe+attach smbus child\n");
344 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
349 intsmb_release_resources(dev);
354 intsmb_detach(device_t dev)
358 error = bus_generic_detach(dev);
360 device_printf(dev, "bus detach failed\n");
364 intsmb_release_resources(dev);
369 intsmb_rawintr(void *arg)
371 struct intsmb_softc *sc = arg;
380 intsmb_callback(device_t dev, int index, void *data)
385 case SMB_REQUEST_BUS:
387 case SMB_RELEASE_BUS:
396 /* Counterpart of smbtx_smb_free(). */
398 intsmb_free(struct intsmb_softc *sc)
401 INTSMB_LOCK_ASSERT(sc);
402 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
404 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
410 /* Disable Interrupt in slave part. */
412 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
414 /* Reset INTR Flag to prepare INTR. */
415 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
416 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
417 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
422 intsmb_intr(struct intsmb_softc *sc)
426 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
427 if (status & PIIX4_SMBHSTSTAT_BUSY)
430 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
431 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
433 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
434 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
435 tmp & ~PIIX4_SMBHSTCNT_INTREN);
442 return (1); /* Not Completed */
446 intsmb_slvintr(struct intsmb_softc *sc)
450 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
451 if (status & PIIX4_SMBSLVSTS_BUSY)
453 if (status & PIIX4_SMBSLVSTS_ALART)
455 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
456 | PIIX4_SMBSLVSTS_SDW1)) {
459 /* Reset Status Register */
460 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
461 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
462 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
467 intsmb_alrintr(struct intsmb_softc *sc)
475 /* Stop generating INTR from ALART. */
476 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
478 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
479 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
483 /* Ask bus who asserted it and then ask it what's the matter. */
485 error = intsmb_free(sc);
489 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
490 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
491 error = intsmb_stop_poll(sc);
493 device_printf(sc->dev, "ALART: ERROR\n");
495 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
496 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
499 /* Re-enable INTR from ALART. */
500 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
501 slvcnt | PIIX4_SMBSLVCNT_ALTEN);
507 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
511 INTSMB_LOCK_ASSERT(sc);
512 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
515 tmp |= PIIX4_SMBHSTCNT_START;
517 /* While not in autoconfiguration enable interrupts. */
518 if (!sc->poll && !cold && !nointr)
519 tmp |= PIIX4_SMBHSTCNT_INTREN;
520 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
524 intsmb_error(device_t dev, int status)
528 if (status & PIIX4_SMBHSTSTAT_ERR)
529 error |= SMB_EBUSERR;
530 if (status & PIIX4_SMBHSTSTAT_BUSC)
532 if (status & PIIX4_SMBHSTSTAT_FAIL)
535 if (error != 0 && bootverbose)
536 device_printf(dev, "error = %d, status = %#x\n", error, status);
544 * Polling is not encouraged because it requires waiting for the
545 * device if it is busy.
546 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
550 intsmb_stop_poll(struct intsmb_softc *sc)
552 int error, i, status, tmp;
554 INTSMB_LOCK_ASSERT(sc);
556 /* First, wait for busy to be set. */
557 for (i = 0; i < 0x7fff; i++)
558 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
559 PIIX4_SMBHSTSTAT_BUSY)
562 /* Wait for busy to clear. */
563 for (i = 0; i < 0x7fff; i++) {
564 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
565 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
567 error = intsmb_error(sc->dev, status);
572 /* Timed out waiting for busy to clear. */
574 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
575 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
576 return (SMB_ETIMEOUT);
580 * Wait for completion and return result.
583 intsmb_stop(struct intsmb_softc *sc)
587 INTSMB_LOCK_ASSERT(sc);
589 if (sc->poll || cold)
590 /* So that it can use device during device probe on SMBus. */
591 return (intsmb_stop_poll(sc));
593 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8);
595 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
596 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
597 error = intsmb_error(sc->dev, status);
598 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
599 device_printf(sc->dev, "unknown cause why?\n");
601 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
602 PIIX4_SMBSLVCNT_ALTEN);
608 /* Timeout Procedure. */
611 /* Re-enable suppressed interrupt from slave part. */
612 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
613 if (error == EWOULDBLOCK)
614 return (SMB_ETIMEOUT);
620 intsmb_quick(device_t dev, u_char slave, int how)
622 struct intsmb_softc *sc = device_get_softc(dev);
628 /* Quick command is part of Address, I think. */
641 error = intsmb_free(sc);
646 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
647 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0);
648 error = intsmb_stop(sc);
654 intsmb_sendb(device_t dev, u_char slave, char byte)
656 struct intsmb_softc *sc = device_get_softc(dev);
660 error = intsmb_free(sc);
665 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
666 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
667 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
668 error = intsmb_stop(sc);
674 intsmb_recvb(device_t dev, u_char slave, char *byte)
676 struct intsmb_softc *sc = device_get_softc(dev);
680 error = intsmb_free(sc);
685 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
686 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
687 error = intsmb_stop(sc);
689 #ifdef RECV_IS_IN_CMD
691 * Linux SMBus stuff also troubles
692 * Because Intel's datasheet does not make clear.
694 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
696 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
704 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
706 struct intsmb_softc *sc = device_get_softc(dev);
710 error = intsmb_free(sc);
715 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
716 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
717 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
718 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
719 error = intsmb_stop(sc);
725 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
727 struct intsmb_softc *sc = device_get_softc(dev);
731 error = intsmb_free(sc);
736 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
737 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
738 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
739 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
740 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
741 error = intsmb_stop(sc);
747 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
749 struct intsmb_softc *sc = device_get_softc(dev);
753 error = intsmb_free(sc);
758 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
759 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
760 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
761 error = intsmb_stop(sc);
763 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
769 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
771 struct intsmb_softc *sc = device_get_softc(dev);
775 error = intsmb_free(sc);
780 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
781 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
782 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
783 error = intsmb_stop(sc);
785 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
786 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
793 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
796 return (SMB_ENOTSUPP);
800 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
802 struct intsmb_softc *sc = device_get_softc(dev);
805 if (count > SMBBLOCKTRANS_MAX || count == 0)
809 error = intsmb_free(sc);
815 /* Reset internal array index. */
816 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
818 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
819 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
820 for (i = 0; i < count; i++)
821 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
822 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
823 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
824 error = intsmb_stop(sc);
830 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
832 struct intsmb_softc *sc = device_get_softc(dev);
837 error = intsmb_free(sc);
843 /* Reset internal array index. */
844 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
846 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
847 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
848 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
849 error = intsmb_stop(sc);
851 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
852 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
854 for (i = 0; i < nread; i++)
855 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
863 static devclass_t intsmb_devclass;
865 static device_method_t intsmb_methods[] = {
866 /* Device interface */
867 DEVMETHOD(device_probe, intsmb_probe),
868 DEVMETHOD(device_attach, intsmb_attach),
869 DEVMETHOD(device_detach, intsmb_detach),
871 /* SMBus interface */
872 DEVMETHOD(smbus_callback, intsmb_callback),
873 DEVMETHOD(smbus_quick, intsmb_quick),
874 DEVMETHOD(smbus_sendb, intsmb_sendb),
875 DEVMETHOD(smbus_recvb, intsmb_recvb),
876 DEVMETHOD(smbus_writeb, intsmb_writeb),
877 DEVMETHOD(smbus_writew, intsmb_writew),
878 DEVMETHOD(smbus_readb, intsmb_readb),
879 DEVMETHOD(smbus_readw, intsmb_readw),
880 DEVMETHOD(smbus_pcall, intsmb_pcall),
881 DEVMETHOD(smbus_bwrite, intsmb_bwrite),
882 DEVMETHOD(smbus_bread, intsmb_bread),
887 static driver_t intsmb_driver = {
890 sizeof(struct intsmb_softc),
893 DRIVER_MODULE_ORDERED(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0,
895 DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0);
896 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
897 MODULE_VERSION(intsmb, 1);
898 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, intpm, intsmb_products,
899 sizeof(intsmb_products[0]), nitems(intsmb_products));