2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/ioccom.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/sysctl.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47 #include <machine/stdarg.h>
51 #include "ioat_internal.h"
53 static int ioat_probe(device_t device);
54 static int ioat_attach(device_t device);
55 static int ioat_detach(device_t device);
56 static int ioat3_attach(device_t device);
57 static int ioat_map_pci_bar(struct ioat_softc *ioat);
58 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg,
60 static int ioat_interrupt_setup(struct ioat_softc *ioat);
61 static void ioat_interrupt_handler(void *arg);
62 static void ioat_process_events(struct ioat_softc *ioat);
63 static inline uint32_t ioat_get_active(struct ioat_softc *ioat);
64 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat);
65 static void ioat_free_ring_entry(struct ioat_softc *ioat,
66 struct ioat_descriptor *desc);
67 static struct ioat_descriptor * ioat_alloc_ring_entry(struct ioat_softc *ioat);
68 static int ioat_reserve_space_and_lock(struct ioat_softc *ioat, int num_descs);
69 static struct ioat_descriptor * ioat_get_ring_entry(struct ioat_softc *ioat,
71 static boolean_t resize_ring(struct ioat_softc *ioat, int order);
72 static void ioat_timer_callback(void *arg);
73 static void dump_descriptor(void *hw_desc);
74 static void ioat_submit_single(struct ioat_softc *ioat);
75 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg,
77 static int ioat_reset_hw(struct ioat_softc *ioat);
78 static void ioat_setup_sysctl(device_t device);
80 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations");
81 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node");
83 static int g_force_legacy_interrupts;
84 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN,
85 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
87 static int g_ioat_debug_level = 0;
88 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level,
89 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
92 * OS <-> Driver interface structures
94 static device_method_t ioat_pci_methods[] = {
95 /* Device interface */
96 DEVMETHOD(device_probe, ioat_probe),
97 DEVMETHOD(device_attach, ioat_attach),
98 DEVMETHOD(device_detach, ioat_detach),
102 static driver_t ioat_pci_driver = {
105 sizeof(struct ioat_softc),
108 static devclass_t ioat_devclass;
109 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0);
112 * Private data structures
114 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS];
115 static int ioat_channel_index = 0;
116 SYSCTL_INT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0,
117 "Number of IOAT channels attached");
124 { 0x34308086, "TBG IOAT Ch0" },
125 { 0x34318086, "TBG IOAT Ch1" },
126 { 0x34328086, "TBG IOAT Ch2" },
127 { 0x34338086, "TBG IOAT Ch3" },
128 { 0x34298086, "TBG IOAT Ch4" },
129 { 0x342a8086, "TBG IOAT Ch5" },
130 { 0x342b8086, "TBG IOAT Ch6" },
131 { 0x342c8086, "TBG IOAT Ch7" },
133 { 0x37108086, "JSF IOAT Ch0" },
134 { 0x37118086, "JSF IOAT Ch1" },
135 { 0x37128086, "JSF IOAT Ch2" },
136 { 0x37138086, "JSF IOAT Ch3" },
137 { 0x37148086, "JSF IOAT Ch4" },
138 { 0x37158086, "JSF IOAT Ch5" },
139 { 0x37168086, "JSF IOAT Ch6" },
140 { 0x37178086, "JSF IOAT Ch7" },
141 { 0x37188086, "JSF IOAT Ch0 (RAID)" },
142 { 0x37198086, "JSF IOAT Ch1 (RAID)" },
144 { 0x3c208086, "SNB IOAT Ch0" },
145 { 0x3c218086, "SNB IOAT Ch1" },
146 { 0x3c228086, "SNB IOAT Ch2" },
147 { 0x3c238086, "SNB IOAT Ch3" },
148 { 0x3c248086, "SNB IOAT Ch4" },
149 { 0x3c258086, "SNB IOAT Ch5" },
150 { 0x3c268086, "SNB IOAT Ch6" },
151 { 0x3c278086, "SNB IOAT Ch7" },
152 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" },
153 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" },
155 { 0x0e208086, "IVB IOAT Ch0" },
156 { 0x0e218086, "IVB IOAT Ch1" },
157 { 0x0e228086, "IVB IOAT Ch2" },
158 { 0x0e238086, "IVB IOAT Ch3" },
159 { 0x0e248086, "IVB IOAT Ch4" },
160 { 0x0e258086, "IVB IOAT Ch5" },
161 { 0x0e268086, "IVB IOAT Ch6" },
162 { 0x0e278086, "IVB IOAT Ch7" },
163 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" },
164 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" },
166 { 0x2f208086, "HSW IOAT Ch0" },
167 { 0x2f218086, "HSW IOAT Ch1" },
168 { 0x2f228086, "HSW IOAT Ch2" },
169 { 0x2f238086, "HSW IOAT Ch3" },
170 { 0x2f248086, "HSW IOAT Ch4" },
171 { 0x2f258086, "HSW IOAT Ch5" },
172 { 0x2f268086, "HSW IOAT Ch6" },
173 { 0x2f278086, "HSW IOAT Ch7" },
174 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" },
175 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" },
177 { 0x0c508086, "BWD IOAT Ch0" },
178 { 0x0c518086, "BWD IOAT Ch1" },
179 { 0x0c528086, "BWD IOAT Ch2" },
180 { 0x0c538086, "BWD IOAT Ch3" },
182 { 0x6f508086, "BDXDE IOAT Ch0" },
183 { 0x6f518086, "BDXDE IOAT Ch1" },
184 { 0x6f528086, "BDXDE IOAT Ch2" },
185 { 0x6f538086, "BDXDE IOAT Ch3" },
191 * OS <-> Driver linkage functions
194 ioat_probe(device_t device)
199 type = pci_get_devid(device);
200 for (ep = pci_ids; ep->type; ep++) {
201 if (ep->type == type) {
202 device_set_desc(device, ep->desc);
210 ioat_attach(device_t device)
212 struct ioat_softc *ioat;
215 ioat = DEVICE2SOFTC(device);
216 ioat->device = device;
218 error = ioat_map_pci_bar(ioat);
222 ioat->version = ioat_read_cbver(ioat);
223 ioat_interrupt_setup(ioat);
225 if (ioat->version < IOAT_VER_3_0) {
230 error = ioat3_attach(device);
234 error = pci_enable_busmaster(device);
238 ioat_channel[ioat_channel_index++] = ioat;
247 ioat_detach(device_t device)
249 struct ioat_softc *ioat;
252 ioat = DEVICE2SOFTC(device);
253 callout_drain(&ioat->timer);
255 pci_disable_busmaster(device);
257 if (ioat->pci_resource != NULL)
258 bus_release_resource(device, SYS_RES_MEMORY,
259 ioat->pci_resource_id, ioat->pci_resource);
261 if (ioat->ring != NULL) {
262 for (i = 0; i < (1 << ioat->ring_size_order); i++)
263 ioat_free_ring_entry(ioat, ioat->ring[i]);
264 free(ioat->ring, M_IOAT);
267 if (ioat->comp_update != NULL) {
268 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map);
269 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update,
270 ioat->comp_update_map);
271 bus_dma_tag_destroy(ioat->comp_update_tag);
274 bus_dma_tag_destroy(ioat->hw_desc_tag);
276 if (ioat->tag != NULL)
277 bus_teardown_intr(device, ioat->res, ioat->tag);
279 if (ioat->res != NULL)
280 bus_release_resource(device, SYS_RES_IRQ,
281 rman_get_rid(ioat->res), ioat->res);
283 pci_release_msi(device);
289 ioat3_selftest(struct ioat_softc *ioat)
295 ioat_acquire(&ioat->dmaengine);
296 ioat_null(&ioat->dmaengine, NULL, NULL, 0);
297 ioat_release(&ioat->dmaengine);
299 for (i = 0; i < 100; i++) {
301 status = ioat_get_chansts(ioat);
302 if (is_ioat_idle(status))
306 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
307 ioat_log_message(0, "could not start channel: "
308 "status = %#jx error = %x\n", (uintmax_t)status, chanerr);
313 * Initialize Hardware
316 ioat3_attach(device_t device)
318 struct ioat_softc *ioat;
319 struct ioat_descriptor **ring;
320 struct ioat_descriptor *next;
321 struct ioat_dma_hw_descriptor *dma_hw_desc;
322 uint32_t capabilities;
323 int i, num_descriptors;
328 ioat = DEVICE2SOFTC(device);
329 capabilities = ioat_read_dmacapability(ioat);
331 xfercap = ioat_read_xfercap(ioat);
333 /* Only bits [4:0] are valid. */
335 ioat->max_xfer_size = 1 << xfercap;
337 /* TODO: need to check DCA here if we ever do XOR/PQ */
339 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
340 mtx_init(&ioat->cleanup_lock, "ioat_process_events", NULL, MTX_DEF);
341 callout_init(&ioat->timer, CALLOUT_MPSAFE);
343 ioat->is_resize_pending = FALSE;
344 ioat->is_completion_pending = FALSE;
345 ioat->is_reset_pending = FALSE;
346 ioat->is_channel_running = FALSE;
347 ioat->is_waiting_for_ack = FALSE;
349 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0,
350 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
351 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
352 &ioat->comp_update_tag);
354 error = bus_dmamem_alloc(ioat->comp_update_tag,
355 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map);
356 if (ioat->comp_update == NULL)
359 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
360 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
365 ioat->ring_size_order = IOAT_MIN_ORDER;
367 num_descriptors = 1 << ioat->ring_size_order;
369 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0,
370 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
371 sizeof(struct ioat_dma_hw_descriptor), 1,
372 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL,
375 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT,
377 if (ioat->ring == NULL)
381 for (i = 0; i < num_descriptors; i++) {
382 ring[i] = ioat_alloc_ring_entry(ioat);
389 for (i = 0; i < num_descriptors - 1; i++) {
391 dma_hw_desc = ring[i]->u.dma;
393 dma_hw_desc->next = next->hw_desc_bus_addr;
396 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr;
402 error = ioat_reset_hw(ioat);
406 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
407 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);
408 ioat_write_chainaddr(ioat, ring[0]->hw_desc_bus_addr);
410 error = ioat3_selftest(ioat);
414 ioat_process_events(ioat);
415 ioat_setup_sysctl(device);
420 ioat_map_pci_bar(struct ioat_softc *ioat)
423 ioat->pci_resource_id = PCIR_BAR(0);
424 ioat->pci_resource = bus_alloc_resource(ioat->device, SYS_RES_MEMORY,
425 &ioat->pci_resource_id, 0, ~0, 1, RF_ACTIVE);
427 if (ioat->pci_resource == NULL) {
428 ioat_log_message(0, "unable to allocate pci resource\n");
432 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource);
433 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource);
438 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
440 struct ioat_softc *ioat = arg;
442 ioat->comp_update_bus_addr = seg[0].ds_addr;
446 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
451 *baddr = segs->ds_addr;
455 * Interrupt setup and handlers
458 ioat_interrupt_setup(struct ioat_softc *ioat)
460 uint32_t num_vectors;
463 boolean_t force_legacy_interrupts;
466 force_legacy_interrupts = FALSE;
468 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) {
470 pci_alloc_msix(ioat->device, &num_vectors);
471 if (num_vectors == 1)
477 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
478 &ioat->rid, RF_ACTIVE);
481 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
482 &ioat->rid, RF_SHAREABLE | RF_ACTIVE);
484 if (ioat->res == NULL) {
485 ioat_log_message(0, "bus_alloc_resource failed\n");
490 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE |
491 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag);
493 ioat_log_message(0, "bus_setup_intr failed\n");
497 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN);
502 ioat_interrupt_handler(void *arg)
504 struct ioat_softc *ioat = arg;
506 ioat_process_events(ioat);
510 ioat_process_events(struct ioat_softc *ioat)
512 struct ioat_descriptor *desc;
513 struct bus_dmadesc *dmadesc;
514 uint64_t comp_update, status;
517 mtx_lock(&ioat->cleanup_lock);
520 comp_update = *ioat->comp_update;
521 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK;
523 ioat_log_message(3, "%s\n", __func__);
525 if (status == ioat->last_seen) {
526 mtx_unlock(&ioat->cleanup_lock);
531 desc = ioat_get_ring_entry(ioat, ioat->tail);
532 dmadesc = &desc->bus_dmadesc;
533 ioat_log_message(3, "completing desc %d\n", ioat->tail);
535 if (dmadesc->callback_fn)
536 (*dmadesc->callback_fn)(dmadesc->callback_arg);
539 if (desc->hw_desc_bus_addr == status)
543 ioat->last_seen = desc->hw_desc_bus_addr;
545 if (ioat->head == ioat->tail) {
546 ioat->is_completion_pending = FALSE;
547 callout_reset(&ioat->timer, 5 * hz, ioat_timer_callback, ioat);
550 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
551 mtx_unlock(&ioat->cleanup_lock);
558 ioat_get_dmaengine(uint32_t index)
561 if (index < ioat_channel_index)
562 return (&ioat_channel[index]->dmaengine);
567 ioat_acquire(bus_dmaengine_t dmaengine)
569 struct ioat_softc *ioat;
571 ioat = to_ioat_softc(dmaengine);
572 mtx_lock(&ioat->submit_lock);
573 ioat_log_message(3, "%s\n", __func__);
577 ioat_release(bus_dmaengine_t dmaengine)
579 struct ioat_softc *ioat;
581 ioat_log_message(3, "%s\n", __func__);
582 ioat = to_ioat_softc(dmaengine);
583 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->head);
584 mtx_unlock(&ioat->submit_lock);
588 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn,
589 void *callback_arg, uint32_t flags)
591 struct ioat_softc *ioat;
592 struct ioat_descriptor *desc;
593 struct ioat_dma_hw_descriptor *hw_desc;
595 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x",
596 flags & ~DMA_ALL_FLAGS));
598 ioat = to_ioat_softc(dmaengine);
600 if (ioat_reserve_space_and_lock(ioat, 1) != 0)
603 ioat_log_message(3, "%s\n", __func__);
605 desc = ioat_get_ring_entry(ioat, ioat->head);
606 hw_desc = desc->u.dma;
608 hw_desc->u.control_raw = 0;
609 hw_desc->u.control.null = 1;
610 hw_desc->u.control.completion_update = 1;
612 if ((flags & DMA_INT_EN) != 0)
613 hw_desc->u.control.int_enable = 1;
616 hw_desc->src_addr = 0;
617 hw_desc->dest_addr = 0;
619 desc->bus_dmadesc.callback_fn = callback_fn;
620 desc->bus_dmadesc.callback_arg = callback_arg;
622 ioat_submit_single(ioat);
623 return (&desc->bus_dmadesc);
627 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
628 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
629 void *callback_arg, uint32_t flags)
631 struct ioat_descriptor *desc;
632 struct ioat_dma_hw_descriptor *hw_desc;
633 struct ioat_softc *ioat;
635 KASSERT((flags & ~DMA_ALL_FLAGS) == 0, ("Unrecognized flag(s): %#x",
636 flags & ~DMA_ALL_FLAGS));
638 ioat = to_ioat_softc(dmaengine);
640 if (len > ioat->max_xfer_size) {
641 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %d\n",
642 __func__, ioat->max_xfer_size, (int)len);
646 if (ioat_reserve_space_and_lock(ioat, 1) != 0)
649 ioat_log_message(3, "%s\n", __func__);
651 desc = ioat_get_ring_entry(ioat, ioat->head);
652 hw_desc = desc->u.dma;
654 hw_desc->u.control_raw = 0;
655 hw_desc->u.control.completion_update = 1;
657 if ((flags & DMA_INT_EN) != 0)
658 hw_desc->u.control.int_enable = 1;
661 hw_desc->src_addr = src;
662 hw_desc->dest_addr = dst;
664 if (g_ioat_debug_level >= 3)
665 dump_descriptor(hw_desc);
667 desc->bus_dmadesc.callback_fn = callback_fn;
668 desc->bus_dmadesc.callback_arg = callback_arg;
670 ioat_submit_single(ioat);
671 return (&desc->bus_dmadesc);
677 static inline uint32_t
678 ioat_get_active(struct ioat_softc *ioat)
681 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1));
684 static inline uint32_t
685 ioat_get_ring_space(struct ioat_softc *ioat)
688 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1);
691 static struct ioat_descriptor *
692 ioat_alloc_ring_entry(struct ioat_softc *ioat)
694 struct ioat_dma_hw_descriptor *hw_desc;
695 struct ioat_descriptor *desc;
697 desc = malloc(sizeof(struct ioat_descriptor), M_IOAT, M_NOWAIT);
701 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc, BUS_DMA_ZERO,
703 if (hw_desc == NULL) {
708 bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc,
709 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr, 0);
711 desc->u.dma = hw_desc;
716 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc)
723 bus_dmamem_free(ioat->hw_desc_tag, desc->u.dma,
729 ioat_reserve_space_and_lock(struct ioat_softc *ioat, int num_descs)
734 if (ioat_get_ring_space(ioat) >= num_descs)
737 mtx_lock(&ioat->cleanup_lock);
738 retry = resize_ring(ioat, ioat->ring_size_order + 1);
739 mtx_unlock(&ioat->cleanup_lock);
746 static struct ioat_descriptor *
747 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index)
750 return (ioat->ring[index % (1 << ioat->ring_size_order)]);
754 resize_ring(struct ioat_softc *ioat, int order)
756 struct ioat_descriptor **ring;
757 struct ioat_descriptor *next;
758 struct ioat_dma_hw_descriptor *hw;
759 struct ioat_descriptor *ent;
760 uint32_t current_size, active, new_size, i, new_idx, current_idx;
763 current_size = 1 << ioat->ring_size_order;
764 active = (ioat->head - ioat->tail) & (current_size - 1);
765 new_size = 1 << order;
767 if (order > IOAT_MAX_ORDER)
771 * when shrinking, verify that we can hold the current active
772 * set in the new ring
774 if (active >= new_size)
777 /* allocate the array to hold the software ring */
778 ring = malloc(new_size * sizeof(*ring), M_IOAT, M_ZERO | M_NOWAIT);
782 ioat_log_message(2, "ring resize: new: %d old: %d\n",
783 new_size, current_size);
785 /* allocate/trim descriptors as needed */
786 if (new_size > current_size) {
787 /* copy current descriptors to the new ring */
788 for (i = 0; i < current_size; i++) {
789 current_idx = (ioat->tail + i) & (current_size - 1);
790 new_idx = (ioat->tail + i) & (new_size - 1);
792 ring[new_idx] = ioat->ring[current_idx];
793 ring[new_idx]->id = new_idx;
796 /* add new descriptors to the ring */
797 for (i = current_size; i < new_size; i++) {
798 new_idx = (ioat->tail + i) & (new_size - 1);
800 ring[new_idx] = ioat_alloc_ring_entry(ioat);
801 if (!ring[new_idx]) {
803 new_idx2 = (ioat->tail + i) &
806 ioat_free_ring_entry(ioat,
812 ring[new_idx]->id = new_idx;
815 for (i = current_size - 1; i < new_size; i++) {
816 new_idx = (ioat->tail + i) & (new_size - 1);
817 next = ring[(new_idx + 1) & (new_size - 1)];
818 hw = ring[new_idx]->u.dma;
820 hw->next = next->hw_desc_bus_addr;
824 * copy current descriptors to the new ring, dropping the
825 * removed descriptors
827 for (i = 0; i < new_size; i++) {
828 current_idx = (ioat->tail + i) & (current_size - 1);
829 new_idx = (ioat->tail + i) & (new_size - 1);
831 ring[new_idx] = ioat->ring[current_idx];
832 ring[new_idx]->id = new_idx;
835 /* free deleted descriptors */
836 for (i = new_size; i < current_size; i++) {
837 ent = ioat_get_ring_entry(ioat, ioat->tail + i);
838 ioat_free_ring_entry(ioat, ent);
841 /* fix up hardware ring */
842 hw = ring[(ioat->tail + new_size - 1) & (new_size - 1)]->u.dma;
843 next = ring[(ioat->tail + new_size) & (new_size - 1)];
844 hw->next = next->hw_desc_bus_addr;
847 free(ioat->ring, M_IOAT);
849 ioat->ring_size_order = order;
855 ioat_timer_callback(void *arg)
857 struct ioat_descriptor *desc;
858 struct ioat_softc *ioat;
863 ioat_log_message(2, "%s\n", __func__);
865 if (ioat->is_completion_pending) {
866 status = ioat_get_chansts(ioat);
869 * When halted due to errors, check for channel programming
870 * errors before advancing the completion state.
872 if (is_ioat_halted(status)) {
873 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
874 ioat_log_message(0, "Channel halted (%x)\n", chanerr);
876 desc = ioat_get_ring_entry(ioat, ioat->tail + 0);
877 dump_descriptor(desc->u.raw);
879 desc = ioat_get_ring_entry(ioat, ioat->tail + 1);
880 dump_descriptor(desc->u.raw);
882 ioat_process_events(ioat);
884 mtx_lock(&ioat->submit_lock);
885 mtx_lock(&ioat->cleanup_lock);
887 if (ioat_get_active(ioat) == 0 &&
888 ioat->ring_size_order > IOAT_MIN_ORDER)
889 resize_ring(ioat, ioat->ring_size_order - 1);
891 mtx_unlock(&ioat->cleanup_lock);
892 mtx_unlock(&ioat->submit_lock);
894 if (ioat->ring_size_order > IOAT_MIN_ORDER)
895 callout_reset(&ioat->timer, 5 * hz,
896 ioat_timer_callback, ioat);
904 ioat_submit_single(struct ioat_softc *ioat)
907 atomic_add_rel_int(&ioat->head, 1);
909 if (!ioat->is_completion_pending) {
910 ioat->is_completion_pending = TRUE;
911 callout_reset(&ioat->timer, 10 * hz, ioat_timer_callback,
917 ioat_reset_hw(struct ioat_softc *ioat)
923 status = ioat_get_chansts(ioat);
924 if (is_ioat_active(status) || is_ioat_idle(status))
927 /* Wait at most 20 ms */
928 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) &&
929 timeout < 20; timeout++) {
931 status = ioat_get_chansts(ioat);
936 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
937 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
940 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors
941 * that can cause stability issues for IOAT v3.
943 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07,
945 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4);
946 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4);
950 /* Wait at most 20 ms */
951 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++)
960 dump_descriptor(void *hw_desc)
964 for (i = 0; i < 2; i++) {
965 for (j = 0; j < 8; j++)
966 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]);
972 ioat_setup_sysctl(device_t device)
974 struct sysctl_ctx_list *sysctl_ctx;
975 struct sysctl_oid *sysctl_tree;
976 struct ioat_softc *ioat;
978 ioat = DEVICE2SOFTC(device);
979 sysctl_ctx = device_get_sysctl_ctx(device);
980 sysctl_tree = device_get_sysctl_tree(device);
982 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
983 "ring_size_order", CTLFLAG_RD, &ioat->ring_size_order,
984 0, "HW descriptor ring size order");
985 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
986 "head", CTLFLAG_RD, &ioat->head,
987 0, "HW descriptor head pointer index");
988 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
989 "tail", CTLFLAG_RD, &ioat->tail,
990 0, "HW descriptor tail pointer index");
994 ioat_log_message(int verbosity, char *fmt, ...)
1000 if (verbosity > g_ioat_debug_level)
1003 va_start(argp, fmt);
1004 vsnprintf(buffer, sizeof(buffer) - 1, fmt, argp);
1008 printf("[%d:%06d] ioat: %s", (int)tv.tv_sec, (int)tv.tv_usec, buffer);