2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
37 #include <sys/ioccom.h>
38 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcivar.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
52 #include <machine/stdarg.h>
60 #include "ioat_internal.h"
62 #ifndef BUS_SPACE_MAXADDR_40BIT
63 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL
65 #define IOAT_REFLK (&ioat->submit_lock)
67 static int ioat_probe(device_t device);
68 static int ioat_attach(device_t device);
69 static int ioat_detach(device_t device);
70 static int ioat_setup_intr(struct ioat_softc *ioat);
71 static int ioat_teardown_intr(struct ioat_softc *ioat);
72 static int ioat3_attach(device_t device);
73 static int ioat_start_channel(struct ioat_softc *ioat);
74 static int ioat_map_pci_bar(struct ioat_softc *ioat);
75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg,
77 static void ioat_interrupt_handler(void *arg);
78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat);
79 static int chanerr_to_errno(uint32_t);
80 static void ioat_process_events(struct ioat_softc *ioat);
81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat);
82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat);
83 static void ioat_free_ring(struct ioat_softc *, uint32_t size,
84 struct ioat_descriptor *);
85 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags);
86 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *,
88 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *,
90 static void ioat_halted_debug(struct ioat_softc *, uint32_t);
91 static void ioat_poll_timer_callback(void *arg);
92 static void dump_descriptor(void *hw_desc);
93 static void ioat_submit_single(struct ioat_softc *ioat);
94 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg,
96 static int ioat_reset_hw(struct ioat_softc *ioat);
97 static void ioat_reset_hw_task(void *, int);
98 static void ioat_setup_sysctl(device_t device);
99 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS);
100 static inline struct ioat_softc *ioat_get(struct ioat_softc *,
102 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind);
103 static inline void _ioat_putn(struct ioat_softc *, uint32_t,
104 enum ioat_ref_kind, boolean_t);
105 static inline void ioat_putn(struct ioat_softc *, uint32_t,
107 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t,
109 static void ioat_drain_locked(struct ioat_softc *);
111 #define ioat_log_message(v, ...) do { \
112 if ((v) <= g_ioat_debug_level) { \
113 device_printf(ioat->device, __VA_ARGS__); \
117 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations");
118 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node");
120 static int g_force_legacy_interrupts;
121 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN,
122 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
124 int g_ioat_debug_level = 0;
125 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level,
126 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
128 unsigned g_ioat_ring_order = 13;
129 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order,
130 0, "Set IOAT ring order. (1 << this) == ring size.");
133 * OS <-> Driver interface structures
135 static device_method_t ioat_pci_methods[] = {
136 /* Device interface */
137 DEVMETHOD(device_probe, ioat_probe),
138 DEVMETHOD(device_attach, ioat_attach),
139 DEVMETHOD(device_detach, ioat_detach),
143 static driver_t ioat_pci_driver = {
146 sizeof(struct ioat_softc),
149 static devclass_t ioat_devclass;
150 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0);
151 MODULE_VERSION(ioat, 1);
154 * Private data structures
156 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS];
157 static unsigned ioat_channel_index = 0;
158 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0,
159 "Number of IOAT channels attached");
166 { 0x34308086, "TBG IOAT Ch0" },
167 { 0x34318086, "TBG IOAT Ch1" },
168 { 0x34328086, "TBG IOAT Ch2" },
169 { 0x34338086, "TBG IOAT Ch3" },
170 { 0x34298086, "TBG IOAT Ch4" },
171 { 0x342a8086, "TBG IOAT Ch5" },
172 { 0x342b8086, "TBG IOAT Ch6" },
173 { 0x342c8086, "TBG IOAT Ch7" },
175 { 0x37108086, "JSF IOAT Ch0" },
176 { 0x37118086, "JSF IOAT Ch1" },
177 { 0x37128086, "JSF IOAT Ch2" },
178 { 0x37138086, "JSF IOAT Ch3" },
179 { 0x37148086, "JSF IOAT Ch4" },
180 { 0x37158086, "JSF IOAT Ch5" },
181 { 0x37168086, "JSF IOAT Ch6" },
182 { 0x37178086, "JSF IOAT Ch7" },
183 { 0x37188086, "JSF IOAT Ch0 (RAID)" },
184 { 0x37198086, "JSF IOAT Ch1 (RAID)" },
186 { 0x3c208086, "SNB IOAT Ch0" },
187 { 0x3c218086, "SNB IOAT Ch1" },
188 { 0x3c228086, "SNB IOAT Ch2" },
189 { 0x3c238086, "SNB IOAT Ch3" },
190 { 0x3c248086, "SNB IOAT Ch4" },
191 { 0x3c258086, "SNB IOAT Ch5" },
192 { 0x3c268086, "SNB IOAT Ch6" },
193 { 0x3c278086, "SNB IOAT Ch7" },
194 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" },
195 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" },
197 { 0x0e208086, "IVB IOAT Ch0" },
198 { 0x0e218086, "IVB IOAT Ch1" },
199 { 0x0e228086, "IVB IOAT Ch2" },
200 { 0x0e238086, "IVB IOAT Ch3" },
201 { 0x0e248086, "IVB IOAT Ch4" },
202 { 0x0e258086, "IVB IOAT Ch5" },
203 { 0x0e268086, "IVB IOAT Ch6" },
204 { 0x0e278086, "IVB IOAT Ch7" },
205 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" },
206 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" },
208 { 0x2f208086, "HSW IOAT Ch0" },
209 { 0x2f218086, "HSW IOAT Ch1" },
210 { 0x2f228086, "HSW IOAT Ch2" },
211 { 0x2f238086, "HSW IOAT Ch3" },
212 { 0x2f248086, "HSW IOAT Ch4" },
213 { 0x2f258086, "HSW IOAT Ch5" },
214 { 0x2f268086, "HSW IOAT Ch6" },
215 { 0x2f278086, "HSW IOAT Ch7" },
216 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" },
217 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" },
219 { 0x0c508086, "BWD IOAT Ch0" },
220 { 0x0c518086, "BWD IOAT Ch1" },
221 { 0x0c528086, "BWD IOAT Ch2" },
222 { 0x0c538086, "BWD IOAT Ch3" },
224 { 0x6f508086, "BDXDE IOAT Ch0" },
225 { 0x6f518086, "BDXDE IOAT Ch1" },
226 { 0x6f528086, "BDXDE IOAT Ch2" },
227 { 0x6f538086, "BDXDE IOAT Ch3" },
229 { 0x6f208086, "BDX IOAT Ch0" },
230 { 0x6f218086, "BDX IOAT Ch1" },
231 { 0x6f228086, "BDX IOAT Ch2" },
232 { 0x6f238086, "BDX IOAT Ch3" },
233 { 0x6f248086, "BDX IOAT Ch4" },
234 { 0x6f258086, "BDX IOAT Ch5" },
235 { 0x6f268086, "BDX IOAT Ch6" },
236 { 0x6f278086, "BDX IOAT Ch7" },
237 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" },
238 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" },
240 { 0x20218086, "SKX IOAT" },
243 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids,
247 * OS <-> Driver linkage functions
250 ioat_probe(device_t device)
255 type = pci_get_devid(device);
256 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) {
257 if (ep->type == type) {
258 device_set_desc(device, ep->desc);
266 ioat_attach(device_t device)
268 struct ioat_softc *ioat;
271 ioat = DEVICE2SOFTC(device);
272 ioat->device = device;
274 error = ioat_map_pci_bar(ioat);
278 ioat->version = ioat_read_cbver(ioat);
279 if (ioat->version < IOAT_VER_3_0) {
284 error = ioat3_attach(device);
288 error = pci_enable_busmaster(device);
292 error = ioat_setup_intr(ioat);
296 error = ioat_reset_hw(ioat);
300 ioat_process_events(ioat);
301 ioat_setup_sysctl(device);
303 ioat->chan_idx = ioat_channel_index;
304 ioat_channel[ioat_channel_index++] = ioat;
314 ioat_detach(device_t device)
316 struct ioat_softc *ioat;
318 ioat = DEVICE2SOFTC(device);
321 taskqueue_drain(taskqueue_thread, &ioat->reset_task);
323 mtx_lock(IOAT_REFLK);
324 ioat->quiescing = TRUE;
325 ioat->destroying = TRUE;
326 wakeup(&ioat->quiescing);
327 wakeup(&ioat->resetting);
329 ioat_channel[ioat->chan_idx] = NULL;
331 ioat_drain_locked(ioat);
332 mtx_unlock(IOAT_REFLK);
334 ioat_teardown_intr(ioat);
335 callout_drain(&ioat->poll_timer);
337 pci_disable_busmaster(device);
339 if (ioat->pci_resource != NULL)
340 bus_release_resource(device, SYS_RES_MEMORY,
341 ioat->pci_resource_id, ioat->pci_resource);
343 if (ioat->ring != NULL)
344 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
346 if (ioat->comp_update != NULL) {
347 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map);
348 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update,
349 ioat->comp_update_map);
350 bus_dma_tag_destroy(ioat->comp_update_tag);
353 if (ioat->hw_desc_ring != NULL) {
354 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map);
355 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring,
357 bus_dma_tag_destroy(ioat->hw_desc_tag);
364 ioat_teardown_intr(struct ioat_softc *ioat)
367 if (ioat->tag != NULL)
368 bus_teardown_intr(ioat->device, ioat->res, ioat->tag);
370 if (ioat->res != NULL)
371 bus_release_resource(ioat->device, SYS_RES_IRQ,
372 rman_get_rid(ioat->res), ioat->res);
374 pci_release_msi(ioat->device);
379 ioat_start_channel(struct ioat_softc *ioat)
381 struct ioat_dma_hw_descriptor *hw_desc;
382 struct ioat_descriptor *desc;
383 struct bus_dmadesc *dmadesc;
388 ioat_acquire(&ioat->dmaengine);
390 /* Submit 'NULL' operation manually to avoid quiescing flag */
391 desc = ioat_get_ring_entry(ioat, ioat->head);
392 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma;
393 dmadesc = &desc->bus_dmadesc;
395 dmadesc->callback_fn = NULL;
396 dmadesc->callback_arg = NULL;
398 hw_desc->u.control_raw = 0;
399 hw_desc->u.control_generic.op = IOAT_OP_COPY;
400 hw_desc->u.control_generic.completion_update = 1;
402 hw_desc->src_addr = 0;
403 hw_desc->dest_addr = 0;
404 hw_desc->u.control.null = 1;
406 ioat_submit_single(ioat);
407 ioat_release(&ioat->dmaengine);
409 for (i = 0; i < 100; i++) {
411 status = ioat_get_chansts(ioat);
412 if (is_ioat_idle(status))
416 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
417 ioat_log_message(0, "could not start channel: "
418 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr,
424 * Initialize Hardware
427 ioat3_attach(device_t device)
429 struct ioat_softc *ioat;
430 struct ioat_descriptor *ring;
431 struct ioat_dma_hw_descriptor *dma_hw_desc;
434 int i, num_descriptors;
439 ioat = DEVICE2SOFTC(device);
440 ioat->capabilities = ioat_read_dmacapability(ioat);
442 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities,
445 xfercap = ioat_read_xfercap(ioat);
446 ioat->max_xfer_size = 1 << xfercap;
448 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) &
449 IOAT_INTRDELAY_SUPPORTED) != 0;
450 if (ioat->intrdelay_supported)
451 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK;
453 /* TODO: need to check DCA here if we ever do XOR/PQ */
455 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
456 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF);
457 callout_init(&ioat->poll_timer, 1);
458 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat);
460 /* Establish lock order for Witness */
461 mtx_lock(&ioat->submit_lock);
462 mtx_lock(&ioat->cleanup_lock);
463 mtx_unlock(&ioat->cleanup_lock);
464 mtx_unlock(&ioat->submit_lock);
466 ioat->is_submitter_processing = FALSE;
467 ioat->is_completion_pending = FALSE;
468 ioat->is_reset_pending = FALSE;
469 ioat->is_channel_running = FALSE;
471 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0,
472 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
473 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
474 &ioat->comp_update_tag);
476 error = bus_dmamem_alloc(ioat->comp_update_tag,
477 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map);
478 if (ioat->comp_update == NULL)
481 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
482 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
487 ioat->ring_size_order = g_ioat_ring_order;
488 num_descriptors = 1 << ioat->ring_size_order;
489 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors;
491 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
492 2 * 1024 * 1024, 0x0, (bus_addr_t)BUS_SPACE_MAXADDR_40BIT,
493 BUS_SPACE_MAXADDR, NULL, NULL, ringsz, 1, ringsz, 0, NULL, NULL,
498 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc,
499 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map);
503 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc,
504 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_WAITOK);
508 ioat->hw_desc_ring = hw_desc;
510 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT,
514 for (i = 0; i < num_descriptors; i++) {
515 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc));
519 for (i = 0; i < num_descriptors; i++) {
520 dma_hw_desc = &ioat->hw_desc_ring[i].dma;
521 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1);
524 ioat->head = ioat->hw_head = 0;
527 *ioat->comp_update = 0;
532 ioat_map_pci_bar(struct ioat_softc *ioat)
535 ioat->pci_resource_id = PCIR_BAR(0);
536 ioat->pci_resource = bus_alloc_resource_any(ioat->device,
537 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE);
539 if (ioat->pci_resource == NULL) {
540 ioat_log_message(0, "unable to allocate pci resource\n");
544 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource);
545 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource);
550 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
552 struct ioat_softc *ioat = arg;
554 KASSERT(error == 0, ("%s: error:%d", __func__, error));
555 ioat->comp_update_bus_addr = seg[0].ds_addr;
559 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
563 KASSERT(error == 0, ("%s: error:%d", __func__, error));
565 *baddr = segs->ds_addr;
569 * Interrupt setup and handlers
572 ioat_setup_intr(struct ioat_softc *ioat)
574 uint32_t num_vectors;
577 boolean_t force_legacy_interrupts;
580 force_legacy_interrupts = FALSE;
582 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) {
584 pci_alloc_msix(ioat->device, &num_vectors);
585 if (num_vectors == 1)
591 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
592 &ioat->rid, RF_ACTIVE);
595 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
596 &ioat->rid, RF_SHAREABLE | RF_ACTIVE);
598 if (ioat->res == NULL) {
599 ioat_log_message(0, "bus_alloc_resource failed\n");
604 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE |
605 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag);
607 ioat_log_message(0, "bus_setup_intr failed\n");
611 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN);
616 ioat_model_resets_msix(struct ioat_softc *ioat)
620 pciid = pci_get_devid(ioat->device);
639 ioat_interrupt_handler(void *arg)
641 struct ioat_softc *ioat = arg;
643 ioat->stats.interrupts++;
644 ioat_process_events(ioat);
648 chanerr_to_errno(uint32_t chanerr)
653 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0)
655 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0)
657 /* This one is probably our fault: */
658 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0)
664 ioat_process_events(struct ioat_softc *ioat)
666 struct ioat_descriptor *desc;
667 struct bus_dmadesc *dmadesc;
668 uint64_t comp_update, status;
669 uint32_t completed, chanerr;
673 mtx_lock(&ioat->cleanup_lock);
676 * Don't run while the hardware is being reset. Reset is responsible
677 * for blocking new work and draining & completing existing work, so
678 * there is nothing to do until new work is queued after reset anyway.
680 if (ioat->resetting_cleanup) {
681 mtx_unlock(&ioat->cleanup_lock);
686 comp_update = *ioat->comp_update;
687 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK;
689 if (status < ioat->hw_desc_bus_addr ||
690 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) *
691 sizeof(struct ioat_generic_hw_descriptor))
692 panic("Bogus completion address %jx (channel %u)",
693 (uintmax_t)status, ioat->chan_idx);
695 if (status == ioat->last_seen) {
697 * If we landed in process_events and nothing has been
698 * completed, check for a timeout due to channel halt.
702 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx",
703 __func__, ioat->chan_idx, comp_update, ioat->last_seen);
705 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) {
706 desc = ioat_get_ring_entry(ioat, ioat->tail);
707 dmadesc = &desc->bus_dmadesc;
708 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)",
709 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
710 dmadesc->callback_arg);
712 if (dmadesc->callback_fn != NULL)
713 dmadesc->callback_fn(dmadesc->callback_arg, 0);
718 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
719 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
721 if (completed != 0) {
722 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1);
723 ioat->stats.descriptors_processed += completed;
727 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
729 /* Perform a racy check first; only take the locks if it passes. */
730 pending = (ioat_get_active(ioat) != 0);
731 if (!pending && ioat->is_completion_pending) {
732 mtx_unlock(&ioat->cleanup_lock);
733 mtx_lock(&ioat->submit_lock);
734 mtx_lock(&ioat->cleanup_lock);
736 pending = (ioat_get_active(ioat) != 0);
737 if (!pending && ioat->is_completion_pending) {
738 ioat->is_completion_pending = FALSE;
739 callout_stop(&ioat->poll_timer);
741 mtx_unlock(&ioat->submit_lock);
743 mtx_unlock(&ioat->cleanup_lock);
746 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback,
749 if (completed != 0) {
750 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF);
755 * The device doesn't seem to reliably push suspend/halt statuses to
756 * the channel completion memory address, so poll the device register
759 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
760 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update))
763 ioat->stats.channel_halts++;
766 * Fatal programming error on this DMA channel. Flush any outstanding
767 * work with error status and restart the engine.
769 mtx_lock(&ioat->submit_lock);
770 mtx_lock(&ioat->cleanup_lock);
771 ioat->quiescing = TRUE;
773 * This is safe to do here because we have both locks and the submit
774 * queue is quiesced. We know that we will drain all outstanding
775 * events, so ioat_reset_hw can't deadlock. It is necessary to
776 * protect other ioat_process_event threads from racing ioat_reset_hw,
777 * reading an indeterminate hw state, and attempting to continue
778 * issuing completions.
780 ioat->resetting_cleanup = TRUE;
782 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
783 if (1 <= g_ioat_debug_level)
784 ioat_halted_debug(ioat, chanerr);
785 ioat->stats.last_halt_chanerr = chanerr;
787 while (ioat_get_active(ioat) > 0) {
788 desc = ioat_get_ring_entry(ioat, ioat->tail);
789 dmadesc = &desc->bus_dmadesc;
790 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)",
791 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
792 dmadesc->callback_arg);
794 if (dmadesc->callback_fn != NULL)
795 dmadesc->callback_fn(dmadesc->callback_arg,
796 chanerr_to_errno(chanerr));
798 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF);
800 ioat->stats.descriptors_processed++;
801 ioat->stats.descriptors_error++;
803 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
804 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
806 if (ioat->is_completion_pending) {
807 ioat->is_completion_pending = FALSE;
808 callout_stop(&ioat->poll_timer);
811 /* Clear error status */
812 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
814 mtx_unlock(&ioat->cleanup_lock);
815 mtx_unlock(&ioat->submit_lock);
817 ioat_log_message(0, "Resetting channel to recover from error\n");
818 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task);
820 ("%s: taskqueue_enqueue failed: %d", __func__, error));
824 ioat_reset_hw_task(void *ctx, int pending __unused)
826 struct ioat_softc *ioat;
830 ioat_log_message(1, "%s: Resetting channel\n", __func__);
832 error = ioat_reset_hw(ioat);
833 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error));
841 ioat_get_nchannels(void)
844 return (ioat_channel_index);
848 ioat_get_dmaengine(uint32_t index, int flags)
850 struct ioat_softc *ioat;
852 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0,
853 ("invalid flags: 0x%08x", flags));
854 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK),
855 ("invalid wait | nowait"));
857 if (index >= ioat_channel_index)
860 ioat = ioat_channel[index];
861 if (ioat == NULL || ioat->destroying)
864 if (ioat->quiescing) {
865 if ((flags & M_NOWAIT) != 0)
868 mtx_lock(IOAT_REFLK);
869 while (ioat->quiescing && !ioat->destroying)
870 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0);
871 mtx_unlock(IOAT_REFLK);
873 if (ioat->destroying)
878 * There's a race here between the quiescing check and HW reset or
881 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine);
885 ioat_put_dmaengine(bus_dmaengine_t dmaengine)
887 struct ioat_softc *ioat;
889 ioat = to_ioat_softc(dmaengine);
890 ioat_put(ioat, IOAT_DMAENGINE_REF);
894 ioat_get_hwversion(bus_dmaengine_t dmaengine)
896 struct ioat_softc *ioat;
898 ioat = to_ioat_softc(dmaengine);
899 return (ioat->version);
903 ioat_get_max_io_size(bus_dmaengine_t dmaengine)
905 struct ioat_softc *ioat;
907 ioat = to_ioat_softc(dmaengine);
908 return (ioat->max_xfer_size);
912 ioat_get_capabilities(bus_dmaengine_t dmaengine)
914 struct ioat_softc *ioat;
916 ioat = to_ioat_softc(dmaengine);
917 return (ioat->capabilities);
921 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
923 struct ioat_softc *ioat;
925 ioat = to_ioat_softc(dmaengine);
926 if (!ioat->intrdelay_supported)
928 if (delay > ioat->intrdelay_max)
931 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay);
932 ioat->cached_intrdelay =
933 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK;
938 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)
940 struct ioat_softc *ioat;
942 ioat = to_ioat_softc(dmaengine);
943 return (ioat->intrdelay_max);
947 ioat_acquire(bus_dmaengine_t dmaengine)
949 struct ioat_softc *ioat;
951 ioat = to_ioat_softc(dmaengine);
952 mtx_lock(&ioat->submit_lock);
953 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
954 ioat->acq_head = ioat->head;
958 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags)
960 struct ioat_softc *ioat;
963 ioat = to_ioat_softc(dmaengine);
964 ioat_acquire(dmaengine);
966 error = ioat_reserve_space(ioat, n, mflags);
968 ioat_release(dmaengine);
973 ioat_release(bus_dmaengine_t dmaengine)
975 struct ioat_softc *ioat;
977 ioat = to_ioat_softc(dmaengine);
978 CTR4(KTR_IOAT, "%s channel=%u dispatch1 hw_head=%u head=%u", __func__,
979 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head);
980 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */);
981 CTR4(KTR_IOAT, "%s channel=%u dispatch2 hw_head=%u head=%u", __func__,
982 ioat->chan_idx, ioat->hw_head & UINT16_MAX, ioat->head);
984 if (ioat->acq_head != ioat->head) {
985 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET,
986 (uint16_t)ioat->hw_head);
988 if (!ioat->is_completion_pending) {
989 ioat->is_completion_pending = TRUE;
990 callout_reset(&ioat->poll_timer, 1,
991 ioat_poll_timer_callback, ioat);
994 mtx_unlock(&ioat->submit_lock);
997 static struct ioat_descriptor *
998 ioat_op_generic(struct ioat_softc *ioat, uint8_t op,
999 uint32_t size, uint64_t src, uint64_t dst,
1000 bus_dmaengine_callback_t callback_fn, void *callback_arg,
1003 struct ioat_generic_hw_descriptor *hw_desc;
1004 struct ioat_descriptor *desc;
1007 mtx_assert(&ioat->submit_lock, MA_OWNED);
1009 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0,
1010 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS));
1011 if ((flags & DMA_NO_WAIT) != 0)
1016 if (size > ioat->max_xfer_size) {
1017 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n",
1018 __func__, ioat->max_xfer_size, (unsigned)size);
1022 if (ioat_reserve_space(ioat, 1, mflags) != 0)
1025 desc = ioat_get_ring_entry(ioat, ioat->head);
1026 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic;
1028 hw_desc->u.control_raw = 0;
1029 hw_desc->u.control_generic.op = op;
1030 hw_desc->u.control_generic.completion_update = 1;
1032 if ((flags & DMA_INT_EN) != 0)
1033 hw_desc->u.control_generic.int_enable = 1;
1034 if ((flags & DMA_FENCE) != 0)
1035 hw_desc->u.control_generic.fence = 1;
1037 hw_desc->size = size;
1038 hw_desc->src_addr = src;
1039 hw_desc->dest_addr = dst;
1041 desc->bus_dmadesc.callback_fn = callback_fn;
1042 desc->bus_dmadesc.callback_arg = callback_arg;
1046 struct bus_dmadesc *
1047 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn,
1048 void *callback_arg, uint32_t flags)
1050 struct ioat_dma_hw_descriptor *hw_desc;
1051 struct ioat_descriptor *desc;
1052 struct ioat_softc *ioat;
1054 ioat = to_ioat_softc(dmaengine);
1055 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1057 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn,
1058 callback_arg, flags);
1062 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1063 hw_desc->u.control.null = 1;
1064 ioat_submit_single(ioat);
1065 return (&desc->bus_dmadesc);
1068 struct bus_dmadesc *
1069 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
1070 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
1071 void *callback_arg, uint32_t flags)
1073 struct ioat_dma_hw_descriptor *hw_desc;
1074 struct ioat_descriptor *desc;
1075 struct ioat_softc *ioat;
1077 ioat = to_ioat_softc(dmaengine);
1079 if (((src | dst) & (0xffffull << 48)) != 0) {
1080 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n",
1085 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
1086 callback_arg, flags);
1090 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1091 if (g_ioat_debug_level >= 3)
1092 dump_descriptor(hw_desc);
1094 ioat_submit_single(ioat);
1095 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx",
1096 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len);
1097 return (&desc->bus_dmadesc);
1100 struct bus_dmadesc *
1101 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
1102 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
1103 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1105 struct ioat_dma_hw_descriptor *hw_desc;
1106 struct ioat_descriptor *desc;
1107 struct ioat_softc *ioat;
1109 ioat = to_ioat_softc(dmaengine);
1110 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1112 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) {
1113 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n",
1117 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) {
1118 ioat_log_message(0, "%s: Addresses must be page-aligned\n",
1123 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1,
1124 callback_fn, callback_arg, flags);
1128 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1129 if (src2 != src1 + PAGE_SIZE) {
1130 hw_desc->u.control.src_page_break = 1;
1131 hw_desc->next_src_addr = src2;
1133 if (dst2 != dst1 + PAGE_SIZE) {
1134 hw_desc->u.control.dest_page_break = 1;
1135 hw_desc->next_dest_addr = dst2;
1138 if (g_ioat_debug_level >= 3)
1139 dump_descriptor(hw_desc);
1141 ioat_submit_single(ioat);
1142 return (&desc->bus_dmadesc);
1145 struct bus_dmadesc *
1146 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
1147 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
1148 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1150 struct ioat_crc32_hw_descriptor *hw_desc;
1151 struct ioat_descriptor *desc;
1152 struct ioat_softc *ioat;
1156 ioat = to_ioat_softc(dmaengine);
1157 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1159 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) {
1160 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n",
1164 if (((src | dst) & (0xffffffull << 40)) != 0) {
1165 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n",
1169 teststore = (flags & _DMA_CRC_TESTSTORE);
1170 if (teststore == _DMA_CRC_TESTSTORE) {
1171 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
1174 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
1175 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
1180 switch (teststore) {
1182 op = IOAT_OP_MOVECRC_STORE;
1185 op = IOAT_OP_MOVECRC_TEST;
1188 KASSERT(teststore == 0, ("bogus"));
1189 op = IOAT_OP_MOVECRC;
1193 if ((flags & DMA_CRC_INLINE) == 0 &&
1194 (crcptr & (0xffffffull << 40)) != 0) {
1196 "%s: High 24 bits of crcptr invalid\n", __func__);
1200 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
1201 callback_arg, flags & ~_DMA_CRC_FLAGS);
1205 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1207 if ((flags & DMA_CRC_INLINE) == 0)
1208 hw_desc->crc_address = crcptr;
1210 hw_desc->u.control.crc_location = 1;
1212 if (initialseed != NULL) {
1213 hw_desc->u.control.use_seed = 1;
1214 hw_desc->seed = *initialseed;
1217 if (g_ioat_debug_level >= 3)
1218 dump_descriptor(hw_desc);
1220 ioat_submit_single(ioat);
1221 return (&desc->bus_dmadesc);
1224 struct bus_dmadesc *
1225 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
1226 uint32_t *initialseed, bus_addr_t crcptr,
1227 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1229 struct ioat_crc32_hw_descriptor *hw_desc;
1230 struct ioat_descriptor *desc;
1231 struct ioat_softc *ioat;
1235 ioat = to_ioat_softc(dmaengine);
1236 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1238 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) {
1239 ioat_log_message(0, "%s: Device lacks CRC capability\n",
1243 if ((src & (0xffffffull << 40)) != 0) {
1244 ioat_log_message(0, "%s: High 24 bits of src invalid\n",
1248 teststore = (flags & _DMA_CRC_TESTSTORE);
1249 if (teststore == _DMA_CRC_TESTSTORE) {
1250 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
1253 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
1254 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
1259 switch (teststore) {
1261 op = IOAT_OP_CRC_STORE;
1264 op = IOAT_OP_CRC_TEST;
1267 KASSERT(teststore == 0, ("bogus"));
1272 if ((flags & DMA_CRC_INLINE) == 0 &&
1273 (crcptr & (0xffffffull << 40)) != 0) {
1275 "%s: High 24 bits of crcptr invalid\n", __func__);
1279 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
1280 callback_arg, flags & ~_DMA_CRC_FLAGS);
1284 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1286 if ((flags & DMA_CRC_INLINE) == 0)
1287 hw_desc->crc_address = crcptr;
1289 hw_desc->u.control.crc_location = 1;
1291 if (initialseed != NULL) {
1292 hw_desc->u.control.use_seed = 1;
1293 hw_desc->seed = *initialseed;
1296 if (g_ioat_debug_level >= 3)
1297 dump_descriptor(hw_desc);
1299 ioat_submit_single(ioat);
1300 return (&desc->bus_dmadesc);
1303 struct bus_dmadesc *
1304 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
1305 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg,
1308 struct ioat_fill_hw_descriptor *hw_desc;
1309 struct ioat_descriptor *desc;
1310 struct ioat_softc *ioat;
1312 ioat = to_ioat_softc(dmaengine);
1313 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1315 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) {
1316 ioat_log_message(0, "%s: Device lacks BFILL capability\n",
1321 if ((dst & (0xffffull << 48)) != 0) {
1322 ioat_log_message(0, "%s: High 16 bits of dst invalid\n",
1327 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst,
1328 callback_fn, callback_arg, flags);
1332 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill;
1333 if (g_ioat_debug_level >= 3)
1334 dump_descriptor(hw_desc);
1336 ioat_submit_single(ioat);
1337 return (&desc->bus_dmadesc);
1343 static inline uint32_t
1344 ioat_get_active(struct ioat_softc *ioat)
1347 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1));
1350 static inline uint32_t
1351 ioat_get_ring_space(struct ioat_softc *ioat)
1354 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1);
1358 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain
1361 * If mflags contains M_WAITOK, blocks until enough space is available.
1363 * Returns zero on success, or an errno on error. If num_descs is beyond the
1364 * maximum ring size, returns EINVAl; if allocation would block and mflags
1365 * contains M_NOWAIT, returns EAGAIN.
1367 * Must be called with the submit_lock held; returns with the lock held. The
1368 * lock may be dropped to allocate the ring.
1370 * (The submit_lock is needed to add any entries to the ring, so callers are
1371 * assured enough room is available.)
1374 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags)
1379 mtx_assert(&ioat->submit_lock, MA_OWNED);
1383 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) {
1389 if (ioat->quiescing) {
1394 if (ioat_get_ring_space(ioat) >= num_descs)
1397 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__,
1398 ioat->chan_idx, num_descs);
1400 if (!dug && !ioat->is_submitter_processing) {
1401 ioat->is_submitter_processing = TRUE;
1402 mtx_unlock(&ioat->submit_lock);
1404 CTR2(KTR_IOAT, "%s channel=%u attempting to process events",
1405 __func__, ioat->chan_idx);
1406 ioat_process_events(ioat);
1408 mtx_lock(&ioat->submit_lock);
1410 KASSERT(ioat->is_submitter_processing == TRUE,
1411 ("is_submitter_processing"));
1412 ioat->is_submitter_processing = FALSE;
1413 wakeup(&ioat->tail);
1417 if ((mflags & M_WAITOK) == 0) {
1421 CTR2(KTR_IOAT, "%s channel=%u blocking on completions",
1422 __func__, ioat->chan_idx);
1423 msleep(&ioat->tail, &ioat->submit_lock, 0,
1429 mtx_assert(&ioat->submit_lock, MA_OWNED);
1430 KASSERT(!ioat->quiescing || error == ENXIO,
1431 ("reserved during quiesce"));
1436 ioat_free_ring(struct ioat_softc *ioat, uint32_t size,
1437 struct ioat_descriptor *ring)
1443 static struct ioat_descriptor *
1444 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index)
1447 return (&ioat->ring[index % (1 << ioat->ring_size_order)]);
1450 static union ioat_hw_descriptor *
1451 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index)
1454 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]);
1458 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr)
1460 union ioat_hw_descriptor *desc;
1462 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr,
1467 mtx_assert(&ioat->cleanup_lock, MA_OWNED);
1469 desc = ioat_get_descriptor(ioat, ioat->tail + 0);
1470 dump_descriptor(desc);
1472 desc = ioat_get_descriptor(ioat, ioat->tail + 1);
1473 dump_descriptor(desc);
1477 ioat_poll_timer_callback(void *arg)
1479 struct ioat_softc *ioat;
1482 ioat_log_message(3, "%s\n", __func__);
1484 ioat_process_events(ioat);
1491 ioat_submit_single(struct ioat_softc *ioat)
1494 mtx_assert(&ioat->submit_lock, MA_OWNED);
1496 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF);
1497 atomic_add_rel_int(&ioat->head, 1);
1498 atomic_add_rel_int(&ioat->hw_head, 1);
1499 CTR5(KTR_IOAT, "%s channel=%u head=%u hw_head=%u tail=%u", __func__,
1500 ioat->chan_idx, ioat->head, ioat->hw_head & UINT16_MAX,
1503 ioat->stats.descriptors_submitted++;
1507 ioat_reset_hw(struct ioat_softc *ioat)
1514 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1516 mtx_lock(IOAT_REFLK);
1517 while (ioat->resetting && !ioat->destroying)
1518 msleep(&ioat->resetting, IOAT_REFLK, 0, "IRH_drain", 0);
1519 if (ioat->destroying) {
1520 mtx_unlock(IOAT_REFLK);
1523 ioat->resetting = TRUE;
1525 ioat->quiescing = TRUE;
1526 ioat_drain_locked(ioat);
1527 mtx_unlock(IOAT_REFLK);
1530 * Suspend ioat_process_events while the hardware and softc are in an
1531 * indeterminate state.
1533 mtx_lock(&ioat->cleanup_lock);
1534 ioat->resetting_cleanup = TRUE;
1535 mtx_unlock(&ioat->cleanup_lock);
1537 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__,
1540 status = ioat_get_chansts(ioat);
1541 if (is_ioat_active(status) || is_ioat_idle(status))
1544 /* Wait at most 20 ms */
1545 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) &&
1546 timeout < 20; timeout++) {
1548 status = ioat_get_chansts(ioat);
1550 if (timeout == 20) {
1555 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce"));
1557 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1558 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
1560 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__,
1564 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors
1565 * that can cause stability issues for IOAT v3.
1567 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07,
1569 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4);
1570 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4);
1573 * BDXDE and BWD models reset MSI-X registers on device reset.
1574 * Save/restore their contents manually.
1576 if (ioat_model_resets_msix(ioat)) {
1577 ioat_log_message(1, "device resets MSI-X registers; saving\n");
1578 pci_save_state(ioat->device);
1582 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__,
1585 /* Wait at most 20 ms */
1586 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++)
1588 if (timeout == 20) {
1593 if (ioat_model_resets_msix(ioat)) {
1594 ioat_log_message(1, "device resets registers; restored\n");
1595 pci_restore_state(ioat->device);
1598 /* Reset attempts to return the hardware to "halted." */
1599 status = ioat_get_chansts(ioat);
1600 if (is_ioat_active(status) || is_ioat_idle(status)) {
1601 /* So this really shouldn't happen... */
1602 ioat_log_message(0, "Device is active after a reset?\n");
1603 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1608 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1610 mtx_lock(&ioat->cleanup_lock);
1611 ioat_halted_debug(ioat, chanerr);
1612 mtx_unlock(&ioat->cleanup_lock);
1618 * Bring device back online after reset. Writing CHAINADDR brings the
1619 * device back to active.
1621 * The internal ring counter resets to zero, so we have to start over
1624 ioat->tail = ioat->head = ioat->hw_head = 0;
1625 ioat->last_seen = 0;
1626 *ioat->comp_update = 0;
1627 KASSERT(!ioat->is_completion_pending, ("bogus completion_pending"));
1629 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1630 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);
1631 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0));
1633 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__,
1637 /* Enqueues a null operation and ensures it completes. */
1639 error = ioat_start_channel(ioat);
1640 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__,
1645 * Resume completions now that ring state is consistent.
1647 mtx_lock(&ioat->cleanup_lock);
1648 ioat->resetting_cleanup = FALSE;
1649 mtx_unlock(&ioat->cleanup_lock);
1651 /* Unblock submission of new work */
1652 mtx_lock(IOAT_REFLK);
1653 ioat->quiescing = FALSE;
1654 wakeup(&ioat->quiescing);
1656 ioat->resetting = FALSE;
1657 wakeup(&ioat->resetting);
1659 if (ioat->is_completion_pending)
1660 callout_reset(&ioat->poll_timer, 1, ioat_poll_timer_callback,
1662 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx);
1663 mtx_unlock(IOAT_REFLK);
1669 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)
1671 struct ioat_softc *ioat;
1678 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
1680 sbuf_new_for_sysctl(&sb, NULL, 256, req);
1682 case IOAT_CHANSTS_ACTIVE:
1683 sbuf_printf(&sb, "ACTIVE");
1685 case IOAT_CHANSTS_IDLE:
1686 sbuf_printf(&sb, "IDLE");
1688 case IOAT_CHANSTS_SUSPENDED:
1689 sbuf_printf(&sb, "SUSPENDED");
1691 case IOAT_CHANSTS_HALTED:
1692 sbuf_printf(&sb, "HALTED");
1694 case IOAT_CHANSTS_ARMED:
1695 sbuf_printf(&sb, "ARMED");
1698 sbuf_printf(&sb, "UNKNOWN");
1701 error = sbuf_finish(&sb);
1704 if (error != 0 || req->newptr == NULL)
1710 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)
1712 struct ioat_softc *ioat;
1714 #define PRECISION "1"
1715 const uintmax_t factor = 10;
1720 sbuf_new_for_sysctl(&sb, NULL, 16, req);
1722 if (ioat->stats.interrupts == 0) {
1723 sbuf_printf(&sb, "NaN");
1726 rate = ioat->stats.descriptors_processed * factor /
1727 ioat->stats.interrupts;
1728 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor,
1732 error = sbuf_finish(&sb);
1734 if (error != 0 || req->newptr == NULL)
1740 sysctl_handle_reset(SYSCTL_HANDLER_ARGS)
1742 struct ioat_softc *ioat;
1748 error = SYSCTL_OUT(req, &arg, sizeof(arg));
1749 if (error != 0 || req->newptr == NULL)
1752 error = SYSCTL_IN(req, &arg, sizeof(arg));
1757 error = ioat_reset_hw(ioat);
1763 dump_descriptor(void *hw_desc)
1767 for (i = 0; i < 2; i++) {
1768 for (j = 0; j < 8; j++)
1769 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]);
1775 ioat_setup_sysctl(device_t device)
1777 struct sysctl_oid_list *par, *statpar, *state, *hammer;
1778 struct sysctl_ctx_list *ctx;
1779 struct sysctl_oid *tree, *tmp;
1780 struct ioat_softc *ioat;
1782 ioat = DEVICE2SOFTC(device);
1783 ctx = device_get_sysctl_ctx(device);
1784 tree = device_get_sysctl_tree(device);
1785 par = SYSCTL_CHILDREN(tree);
1787 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD,
1788 &ioat->version, 0, "HW version (0xMM form)");
1789 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD,
1790 &ioat->max_xfer_size, 0, "HW maximum transfer size");
1791 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD,
1792 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported");
1793 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD,
1794 &ioat->intrdelay_max, 0,
1795 "Maximum configurable INTRDELAY on this channel (microseconds)");
1797 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL,
1798 "IOAT channel internal state");
1799 state = SYSCTL_CHILDREN(tmp);
1801 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD,
1802 &ioat->ring_size_order, 0, "SW descriptor ring size order");
1803 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head,
1804 0, "SW descriptor head pointer index");
1805 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail,
1806 0, "SW descriptor tail pointer index");
1807 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD,
1808 &ioat->hw_head, 0, "HW DMACOUNT");
1810 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD,
1811 ioat->comp_update, "HW addr of last completion");
1813 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing",
1814 CTLFLAG_RD, &ioat->is_submitter_processing, 0,
1815 "submitter processing");
1816 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending",
1817 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending");
1818 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD,
1819 &ioat->is_reset_pending, 0, "reset pending");
1820 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD,
1821 &ioat->is_channel_running, 0, "channel running");
1823 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts",
1824 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A",
1825 "String of the channel status");
1827 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD,
1828 &ioat->cached_intrdelay, 0,
1829 "Current INTRDELAY on this channel (cached, microseconds)");
1831 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL,
1832 "Big hammers (mostly for testing)");
1833 hammer = SYSCTL_CHILDREN(tmp);
1835 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset",
1836 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I",
1837 "Set to non-zero to reset the hardware");
1839 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL,
1840 "IOAT channel statistics");
1841 statpar = SYSCTL_CHILDREN(tmp);
1843 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW,
1844 &ioat->stats.interrupts,
1845 "Number of interrupts processed on this channel");
1846 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW,
1847 &ioat->stats.descriptors_processed,
1848 "Number of descriptors processed on this channel");
1849 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW,
1850 &ioat->stats.descriptors_submitted,
1851 "Number of descriptors submitted to this channel");
1852 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW,
1853 &ioat->stats.descriptors_error,
1854 "Number of descriptors failed by channel errors");
1855 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW,
1856 &ioat->stats.channel_halts, 0,
1857 "Number of times the channel has halted");
1858 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW,
1859 &ioat->stats.last_halt_chanerr, 0,
1860 "The raw CHANERR when the channel was last halted");
1862 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt",
1863 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A",
1864 "Descriptors per interrupt");
1867 static inline struct ioat_softc *
1868 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind)
1872 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus"));
1874 old = atomic_fetchadd_32(&ioat->refcnt, 1);
1875 KASSERT(old < UINT32_MAX, ("refcnt overflow"));
1878 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1);
1879 KASSERT(old < UINT32_MAX, ("refcnt kind overflow"));
1886 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind)
1889 _ioat_putn(ioat, n, kind, FALSE);
1893 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind)
1896 _ioat_putn(ioat, n, kind, TRUE);
1900 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind,
1905 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus"));
1911 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n);
1912 KASSERT(old >= n, ("refcnt kind underflow"));
1915 /* Skip acquiring the lock if resulting refcnt > 0. */
1920 if (atomic_cmpset_32(&ioat->refcnt, old, old - n))
1925 mtx_assert(IOAT_REFLK, MA_OWNED);
1927 mtx_lock(IOAT_REFLK);
1929 old = atomic_fetchadd_32(&ioat->refcnt, -n);
1930 KASSERT(old >= n, ("refcnt error"));
1935 mtx_unlock(IOAT_REFLK);
1939 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind)
1942 ioat_putn(ioat, 1, kind);
1946 ioat_drain_locked(struct ioat_softc *ioat)
1949 mtx_assert(IOAT_REFLK, MA_OWNED);
1950 while (ioat->refcnt > 0)
1951 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0);
1955 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo)
1956 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object)
1957 DB_SHOW_COMMAND(ioat, db_show_ioat)
1959 struct ioat_softc *sc;
1964 idx = (unsigned)addr;
1965 if (idx >= ioat_channel_index)
1968 sc = ioat_channel[idx];
1969 db_printf("ioat softc at %p\n", sc);
1973 db_printf(" version: %d\n", sc->version);
1974 db_printf(" chan_idx: %u\n", sc->chan_idx);
1975 db_printf(" submit_lock: ");
1976 db_show_lock(&sc->submit_lock);
1978 db_printf(" capabilities: %b\n", (int)sc->capabilities,
1980 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay);
1981 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update);
1983 db_printf(" poll_timer:\n");
1984 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time);
1985 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg);
1986 db_printf(" c_func: %p\n", sc->poll_timer.c_func);
1987 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock);
1988 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags);
1990 db_printf(" quiescing: %d\n", (int)sc->quiescing);
1991 db_printf(" destroying: %d\n", (int)sc->destroying);
1992 db_printf(" is_submitter_processing: %d\n",
1993 (int)sc->is_submitter_processing);
1994 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending);
1995 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending);
1996 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running);
1997 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported);
1998 db_printf(" resetting: %d\n", (int)sc->resetting);
2000 db_printf(" head: %u\n", sc->head);
2001 db_printf(" tail: %u\n", sc->tail);
2002 db_printf(" hw_head: %u\n", sc->hw_head);
2003 db_printf(" ring_size_order: %u\n", sc->ring_size_order);
2004 db_printf(" last_seen: 0x%lx\n", sc->last_seen);
2005 db_printf(" ring: %p\n", sc->ring);
2006 db_printf(" descriptors: %p\n", sc->hw_desc_ring);
2007 db_printf(" descriptors (phys): 0x%jx\n",
2008 (uintmax_t)sc->hw_desc_bus_addr);
2010 db_printf(" ring[%u] (tail):\n", sc->tail %
2011 (1 << sc->ring_size_order));
2012 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id);
2013 db_printf(" addr: 0x%lx\n",
2014 RING_PHYS_ADDR(sc, sc->tail));
2015 db_printf(" next: 0x%lx\n",
2016 ioat_get_descriptor(sc, sc->tail)->generic.next);
2018 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) %
2019 (1 << sc->ring_size_order));
2020 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id);
2021 db_printf(" addr: 0x%lx\n",
2022 RING_PHYS_ADDR(sc, sc->head - 1));
2023 db_printf(" next: 0x%lx\n",
2024 ioat_get_descriptor(sc, sc->head - 1)->generic.next);
2026 db_printf(" ring[%u] (head):\n", (sc->head) %
2027 (1 << sc->ring_size_order));
2028 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id);
2029 db_printf(" addr: 0x%lx\n",
2030 RING_PHYS_ADDR(sc, sc->head));
2031 db_printf(" next: 0x%lx\n",
2032 ioat_get_descriptor(sc, sc->head)->generic.next);
2034 for (idx = 0; idx < (1 << sc->ring_size_order); idx++)
2035 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK)
2036 == RING_PHYS_ADDR(sc, idx))
2037 db_printf(" ring[%u] == hardware tail\n", idx);
2039 db_printf(" cleanup_lock: ");
2040 db_show_lock(&sc->cleanup_lock);
2042 db_printf(" refcnt: %u\n", sc->refcnt);
2044 CTASSERT(IOAT_NUM_REF_KINDS == 2);
2045 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0],
2048 db_printf(" stats:\n");
2049 db_printf(" interrupts: %lu\n", sc->stats.interrupts);
2050 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed);
2051 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error);
2052 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted);
2054 db_printf(" channel_halts: %u\n", sc->stats.channel_halts);
2055 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr);
2060 db_printf(" hw status:\n");
2061 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc));
2062 db_printf(" chanctrl: 0x%x\n",
2063 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET));
2064 db_printf(" chancmd: 0x%x\n",
2065 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET));
2066 db_printf(" dmacount: 0x%x\n",
2067 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET));
2068 db_printf(" chainaddr: 0x%lx\n",
2069 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW));
2070 db_printf(" chancmp: 0x%lx\n",
2071 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW));
2072 db_printf(" chanerr: %b\n",
2073 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR);
2076 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index);