2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/ioccom.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <machine/bus.h>
50 #include <machine/resource.h>
51 #include <machine/stdarg.h>
59 #include "ioat_internal.h"
61 #ifndef BUS_SPACE_MAXADDR_40BIT
62 #define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFULL
64 #define IOAT_INTR_TIMO (hz / 10)
65 #define IOAT_REFLK (&ioat->submit_lock)
67 static int ioat_probe(device_t device);
68 static int ioat_attach(device_t device);
69 static int ioat_detach(device_t device);
70 static int ioat_setup_intr(struct ioat_softc *ioat);
71 static int ioat_teardown_intr(struct ioat_softc *ioat);
72 static int ioat3_attach(device_t device);
73 static int ioat_start_channel(struct ioat_softc *ioat);
74 static int ioat_map_pci_bar(struct ioat_softc *ioat);
75 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg,
77 static void ioat_interrupt_handler(void *arg);
78 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat);
79 static int chanerr_to_errno(uint32_t);
80 static void ioat_process_events(struct ioat_softc *ioat);
81 static inline uint32_t ioat_get_active(struct ioat_softc *ioat);
82 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat);
83 static void ioat_free_ring(struct ioat_softc *, uint32_t size,
84 struct ioat_descriptor **);
85 static void ioat_free_ring_entry(struct ioat_softc *ioat,
86 struct ioat_descriptor *desc);
87 static struct ioat_descriptor *ioat_alloc_ring_entry(struct ioat_softc *,
89 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags);
90 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *ioat,
92 static struct ioat_descriptor **ioat_prealloc_ring(struct ioat_softc *,
93 uint32_t size, boolean_t need_dscr, int mflags);
94 static int ring_grow(struct ioat_softc *, uint32_t oldorder,
95 struct ioat_descriptor **);
96 static int ring_shrink(struct ioat_softc *, uint32_t oldorder,
97 struct ioat_descriptor **);
98 static void ioat_halted_debug(struct ioat_softc *, uint32_t);
99 static void ioat_timer_callback(void *arg);
100 static void dump_descriptor(void *hw_desc);
101 static void ioat_submit_single(struct ioat_softc *ioat);
102 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg,
104 static int ioat_reset_hw(struct ioat_softc *ioat);
105 static void ioat_reset_hw_task(void *, int);
106 static void ioat_setup_sysctl(device_t device);
107 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS);
108 static inline struct ioat_softc *ioat_get(struct ioat_softc *,
110 static inline void ioat_put(struct ioat_softc *, enum ioat_ref_kind);
111 static inline void _ioat_putn(struct ioat_softc *, uint32_t,
112 enum ioat_ref_kind, boolean_t);
113 static inline void ioat_putn(struct ioat_softc *, uint32_t,
115 static inline void ioat_putn_locked(struct ioat_softc *, uint32_t,
117 static void ioat_drain_locked(struct ioat_softc *);
119 #define ioat_log_message(v, ...) do { \
120 if ((v) <= g_ioat_debug_level) { \
121 device_printf(ioat->device, __VA_ARGS__); \
125 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations");
126 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node");
128 static int g_force_legacy_interrupts;
129 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN,
130 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
132 int g_ioat_debug_level = 0;
133 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level,
134 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
137 * OS <-> Driver interface structures
139 static device_method_t ioat_pci_methods[] = {
140 /* Device interface */
141 DEVMETHOD(device_probe, ioat_probe),
142 DEVMETHOD(device_attach, ioat_attach),
143 DEVMETHOD(device_detach, ioat_detach),
147 static driver_t ioat_pci_driver = {
150 sizeof(struct ioat_softc),
153 static devclass_t ioat_devclass;
154 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0);
155 MODULE_VERSION(ioat, 1);
158 * Private data structures
160 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS];
161 static unsigned ioat_channel_index = 0;
162 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0,
163 "Number of IOAT channels attached");
170 { 0x34308086, "TBG IOAT Ch0" },
171 { 0x34318086, "TBG IOAT Ch1" },
172 { 0x34328086, "TBG IOAT Ch2" },
173 { 0x34338086, "TBG IOAT Ch3" },
174 { 0x34298086, "TBG IOAT Ch4" },
175 { 0x342a8086, "TBG IOAT Ch5" },
176 { 0x342b8086, "TBG IOAT Ch6" },
177 { 0x342c8086, "TBG IOAT Ch7" },
179 { 0x37108086, "JSF IOAT Ch0" },
180 { 0x37118086, "JSF IOAT Ch1" },
181 { 0x37128086, "JSF IOAT Ch2" },
182 { 0x37138086, "JSF IOAT Ch3" },
183 { 0x37148086, "JSF IOAT Ch4" },
184 { 0x37158086, "JSF IOAT Ch5" },
185 { 0x37168086, "JSF IOAT Ch6" },
186 { 0x37178086, "JSF IOAT Ch7" },
187 { 0x37188086, "JSF IOAT Ch0 (RAID)" },
188 { 0x37198086, "JSF IOAT Ch1 (RAID)" },
190 { 0x3c208086, "SNB IOAT Ch0" },
191 { 0x3c218086, "SNB IOAT Ch1" },
192 { 0x3c228086, "SNB IOAT Ch2" },
193 { 0x3c238086, "SNB IOAT Ch3" },
194 { 0x3c248086, "SNB IOAT Ch4" },
195 { 0x3c258086, "SNB IOAT Ch5" },
196 { 0x3c268086, "SNB IOAT Ch6" },
197 { 0x3c278086, "SNB IOAT Ch7" },
198 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" },
199 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" },
201 { 0x0e208086, "IVB IOAT Ch0" },
202 { 0x0e218086, "IVB IOAT Ch1" },
203 { 0x0e228086, "IVB IOAT Ch2" },
204 { 0x0e238086, "IVB IOAT Ch3" },
205 { 0x0e248086, "IVB IOAT Ch4" },
206 { 0x0e258086, "IVB IOAT Ch5" },
207 { 0x0e268086, "IVB IOAT Ch6" },
208 { 0x0e278086, "IVB IOAT Ch7" },
209 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" },
210 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" },
212 { 0x2f208086, "HSW IOAT Ch0" },
213 { 0x2f218086, "HSW IOAT Ch1" },
214 { 0x2f228086, "HSW IOAT Ch2" },
215 { 0x2f238086, "HSW IOAT Ch3" },
216 { 0x2f248086, "HSW IOAT Ch4" },
217 { 0x2f258086, "HSW IOAT Ch5" },
218 { 0x2f268086, "HSW IOAT Ch6" },
219 { 0x2f278086, "HSW IOAT Ch7" },
220 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" },
221 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" },
223 { 0x0c508086, "BWD IOAT Ch0" },
224 { 0x0c518086, "BWD IOAT Ch1" },
225 { 0x0c528086, "BWD IOAT Ch2" },
226 { 0x0c538086, "BWD IOAT Ch3" },
228 { 0x6f508086, "BDXDE IOAT Ch0" },
229 { 0x6f518086, "BDXDE IOAT Ch1" },
230 { 0x6f528086, "BDXDE IOAT Ch2" },
231 { 0x6f538086, "BDXDE IOAT Ch3" },
233 { 0x6f208086, "BDX IOAT Ch0" },
234 { 0x6f218086, "BDX IOAT Ch1" },
235 { 0x6f228086, "BDX IOAT Ch2" },
236 { 0x6f238086, "BDX IOAT Ch3" },
237 { 0x6f248086, "BDX IOAT Ch4" },
238 { 0x6f258086, "BDX IOAT Ch5" },
239 { 0x6f268086, "BDX IOAT Ch6" },
240 { 0x6f278086, "BDX IOAT Ch7" },
241 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" },
242 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" },
248 * OS <-> Driver linkage functions
251 ioat_probe(device_t device)
256 type = pci_get_devid(device);
257 for (ep = pci_ids; ep->type; ep++) {
258 if (ep->type == type) {
259 device_set_desc(device, ep->desc);
267 ioat_attach(device_t device)
269 struct ioat_softc *ioat;
272 ioat = DEVICE2SOFTC(device);
273 ioat->device = device;
275 error = ioat_map_pci_bar(ioat);
279 ioat->version = ioat_read_cbver(ioat);
280 if (ioat->version < IOAT_VER_3_0) {
285 error = ioat3_attach(device);
289 error = pci_enable_busmaster(device);
293 error = ioat_setup_intr(ioat);
297 error = ioat_reset_hw(ioat);
301 ioat_process_events(ioat);
302 ioat_setup_sysctl(device);
304 ioat->chan_idx = ioat_channel_index;
305 ioat_channel[ioat_channel_index++] = ioat;
315 ioat_detach(device_t device)
317 struct ioat_softc *ioat;
319 ioat = DEVICE2SOFTC(device);
322 taskqueue_drain(taskqueue_thread, &ioat->reset_task);
324 mtx_lock(IOAT_REFLK);
325 ioat->quiescing = TRUE;
326 ioat->destroying = TRUE;
327 wakeup(&ioat->quiescing);
329 ioat_channel[ioat->chan_idx] = NULL;
331 ioat_drain_locked(ioat);
332 mtx_unlock(IOAT_REFLK);
334 ioat_teardown_intr(ioat);
335 callout_drain(&ioat->timer);
337 pci_disable_busmaster(device);
339 if (ioat->pci_resource != NULL)
340 bus_release_resource(device, SYS_RES_MEMORY,
341 ioat->pci_resource_id, ioat->pci_resource);
343 if (ioat->ring != NULL)
344 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
346 if (ioat->comp_update != NULL) {
347 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map);
348 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update,
349 ioat->comp_update_map);
350 bus_dma_tag_destroy(ioat->comp_update_tag);
353 bus_dma_tag_destroy(ioat->hw_desc_tag);
359 ioat_teardown_intr(struct ioat_softc *ioat)
362 if (ioat->tag != NULL)
363 bus_teardown_intr(ioat->device, ioat->res, ioat->tag);
365 if (ioat->res != NULL)
366 bus_release_resource(ioat->device, SYS_RES_IRQ,
367 rman_get_rid(ioat->res), ioat->res);
369 pci_release_msi(ioat->device);
374 ioat_start_channel(struct ioat_softc *ioat)
380 ioat_acquire(&ioat->dmaengine);
381 ioat_null(&ioat->dmaengine, NULL, NULL, 0);
382 ioat_release(&ioat->dmaengine);
384 for (i = 0; i < 100; i++) {
386 status = ioat_get_chansts(ioat);
387 if (is_ioat_idle(status))
391 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
392 ioat_log_message(0, "could not start channel: "
393 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr,
399 * Initialize Hardware
402 ioat3_attach(device_t device)
404 struct ioat_softc *ioat;
405 struct ioat_descriptor **ring;
406 struct ioat_descriptor *next;
407 struct ioat_dma_hw_descriptor *dma_hw_desc;
408 int i, num_descriptors;
413 ioat = DEVICE2SOFTC(device);
414 ioat->capabilities = ioat_read_dmacapability(ioat);
416 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities,
419 xfercap = ioat_read_xfercap(ioat);
420 ioat->max_xfer_size = 1 << xfercap;
422 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) &
423 IOAT_INTRDELAY_SUPPORTED) != 0;
424 if (ioat->intrdelay_supported)
425 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK;
427 /* TODO: need to check DCA here if we ever do XOR/PQ */
429 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
430 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF);
431 callout_init(&ioat->timer, 1);
432 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat);
434 /* Establish lock order for Witness */
435 mtx_lock(&ioat->submit_lock);
436 mtx_lock(&ioat->cleanup_lock);
437 mtx_unlock(&ioat->cleanup_lock);
438 mtx_unlock(&ioat->submit_lock);
440 ioat->is_resize_pending = FALSE;
441 ioat->is_completion_pending = FALSE;
442 ioat->is_reset_pending = FALSE;
443 ioat->is_channel_running = FALSE;
445 bus_dma_tag_create(bus_get_dma_tag(ioat->device), sizeof(uint64_t), 0x0,
446 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
447 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
448 &ioat->comp_update_tag);
450 error = bus_dmamem_alloc(ioat->comp_update_tag,
451 (void **)&ioat->comp_update, BUS_DMA_ZERO, &ioat->comp_update_map);
452 if (ioat->comp_update == NULL)
455 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
456 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
461 ioat->ring_size_order = IOAT_MIN_ORDER;
463 num_descriptors = 1 << ioat->ring_size_order;
465 bus_dma_tag_create(bus_get_dma_tag(ioat->device), 0x40, 0x0,
466 BUS_SPACE_MAXADDR_40BIT, BUS_SPACE_MAXADDR, NULL, NULL,
467 sizeof(struct ioat_dma_hw_descriptor), 1,
468 sizeof(struct ioat_dma_hw_descriptor), 0, NULL, NULL,
471 ioat->ring = malloc(num_descriptors * sizeof(*ring), M_IOAT,
475 for (i = 0; i < num_descriptors; i++) {
476 ring[i] = ioat_alloc_ring_entry(ioat, M_WAITOK);
483 for (i = 0; i < num_descriptors - 1; i++) {
485 dma_hw_desc = ring[i]->u.dma;
487 dma_hw_desc->next = next->hw_desc_bus_addr;
490 ring[i]->u.dma->next = ring[0]->hw_desc_bus_addr;
492 ioat->head = ioat->hw_head = 0;
499 ioat_map_pci_bar(struct ioat_softc *ioat)
502 ioat->pci_resource_id = PCIR_BAR(0);
503 ioat->pci_resource = bus_alloc_resource_any(ioat->device,
504 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE);
506 if (ioat->pci_resource == NULL) {
507 ioat_log_message(0, "unable to allocate pci resource\n");
511 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource);
512 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource);
517 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
519 struct ioat_softc *ioat = arg;
521 KASSERT(error == 0, ("%s: error:%d", __func__, error));
522 ioat->comp_update_bus_addr = seg[0].ds_addr;
526 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
530 KASSERT(error == 0, ("%s: error:%d", __func__, error));
532 *baddr = segs->ds_addr;
536 * Interrupt setup and handlers
539 ioat_setup_intr(struct ioat_softc *ioat)
541 uint32_t num_vectors;
544 boolean_t force_legacy_interrupts;
547 force_legacy_interrupts = FALSE;
549 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) {
551 pci_alloc_msix(ioat->device, &num_vectors);
552 if (num_vectors == 1)
558 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
559 &ioat->rid, RF_ACTIVE);
562 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
563 &ioat->rid, RF_SHAREABLE | RF_ACTIVE);
565 if (ioat->res == NULL) {
566 ioat_log_message(0, "bus_alloc_resource failed\n");
571 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE |
572 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag);
574 ioat_log_message(0, "bus_setup_intr failed\n");
578 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN);
583 ioat_model_resets_msix(struct ioat_softc *ioat)
587 pciid = pci_get_devid(ioat->device);
606 ioat_interrupt_handler(void *arg)
608 struct ioat_softc *ioat = arg;
610 ioat->stats.interrupts++;
611 ioat_process_events(ioat);
615 chanerr_to_errno(uint32_t chanerr)
620 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0)
622 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0)
624 /* This one is probably our fault: */
625 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0)
631 ioat_process_events(struct ioat_softc *ioat)
633 struct ioat_descriptor *desc;
634 struct bus_dmadesc *dmadesc;
635 uint64_t comp_update, status;
636 uint32_t completed, chanerr;
639 mtx_lock(&ioat->cleanup_lock);
642 comp_update = *ioat->comp_update;
643 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK;
645 CTR0(KTR_IOAT, __func__);
647 if (status == ioat->last_seen) {
649 * If we landed in process_events and nothing has been
650 * completed, check for a timeout due to channel halt.
652 comp_update = ioat_get_chansts(ioat);
657 desc = ioat_get_ring_entry(ioat, ioat->tail);
658 dmadesc = &desc->bus_dmadesc;
659 CTR1(KTR_IOAT, "completing desc %d", ioat->tail);
661 if (dmadesc->callback_fn != NULL)
662 dmadesc->callback_fn(dmadesc->callback_arg, 0);
666 if (desc->hw_desc_bus_addr == status)
670 ioat->last_seen = desc->hw_desc_bus_addr;
672 if (ioat->head == ioat->tail) {
673 ioat->is_completion_pending = FALSE;
674 callout_reset(&ioat->timer, IOAT_INTR_TIMO,
675 ioat_timer_callback, ioat);
678 ioat->stats.descriptors_processed += completed;
681 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
682 mtx_unlock(&ioat->cleanup_lock);
684 if (completed != 0) {
685 ioat_putn(ioat, completed, IOAT_ACTIVE_DESCR_REF);
689 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update))
692 ioat->stats.channel_halts++;
695 * Fatal programming error on this DMA channel. Flush any outstanding
696 * work with error status and restart the engine.
698 ioat_log_message(0, "Channel halted due to fatal programming error\n");
699 mtx_lock(&ioat->submit_lock);
700 mtx_lock(&ioat->cleanup_lock);
701 ioat->quiescing = TRUE;
703 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
704 ioat_halted_debug(ioat, chanerr);
705 ioat->stats.last_halt_chanerr = chanerr;
707 while (ioat_get_active(ioat) > 0) {
708 desc = ioat_get_ring_entry(ioat, ioat->tail);
709 dmadesc = &desc->bus_dmadesc;
710 CTR1(KTR_IOAT, "completing err desc %d", ioat->tail);
712 if (dmadesc->callback_fn != NULL)
713 dmadesc->callback_fn(dmadesc->callback_arg,
714 chanerr_to_errno(chanerr));
716 ioat_putn_locked(ioat, 1, IOAT_ACTIVE_DESCR_REF);
718 ioat->stats.descriptors_processed++;
719 ioat->stats.descriptors_error++;
722 /* Clear error status */
723 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
725 mtx_unlock(&ioat->cleanup_lock);
726 mtx_unlock(&ioat->submit_lock);
728 ioat_log_message(0, "Resetting channel to recover from error\n");
729 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task);
731 ("%s: taskqueue_enqueue failed: %d", __func__, error));
735 ioat_reset_hw_task(void *ctx, int pending __unused)
737 struct ioat_softc *ioat;
741 ioat_log_message(1, "%s: Resetting channel\n", __func__);
743 error = ioat_reset_hw(ioat);
744 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error));
752 ioat_get_nchannels(void)
755 return (ioat_channel_index);
759 ioat_get_dmaengine(uint32_t index, int flags)
761 struct ioat_softc *ioat;
763 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0,
764 ("invalid flags: 0x%08x", flags));
765 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK),
766 ("invalid wait | nowait"));
768 if (index >= ioat_channel_index)
771 ioat = ioat_channel[index];
772 if (ioat == NULL || ioat->destroying)
775 if (ioat->quiescing) {
776 if ((flags & M_NOWAIT) != 0)
779 mtx_lock(IOAT_REFLK);
780 while (ioat->quiescing && !ioat->destroying)
781 msleep(&ioat->quiescing, IOAT_REFLK, 0, "getdma", 0);
782 mtx_unlock(IOAT_REFLK);
784 if (ioat->destroying)
789 * There's a race here between the quiescing check and HW reset or
792 return (&ioat_get(ioat, IOAT_DMAENGINE_REF)->dmaengine);
796 ioat_put_dmaengine(bus_dmaengine_t dmaengine)
798 struct ioat_softc *ioat;
800 ioat = to_ioat_softc(dmaengine);
801 ioat_put(ioat, IOAT_DMAENGINE_REF);
805 ioat_get_hwversion(bus_dmaengine_t dmaengine)
807 struct ioat_softc *ioat;
809 ioat = to_ioat_softc(dmaengine);
810 return (ioat->version);
814 ioat_get_max_io_size(bus_dmaengine_t dmaengine)
816 struct ioat_softc *ioat;
818 ioat = to_ioat_softc(dmaengine);
819 return (ioat->max_xfer_size);
823 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
825 struct ioat_softc *ioat;
827 ioat = to_ioat_softc(dmaengine);
828 if (!ioat->intrdelay_supported)
830 if (delay > ioat->intrdelay_max)
833 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay);
834 ioat->cached_intrdelay =
835 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK;
840 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)
842 struct ioat_softc *ioat;
844 ioat = to_ioat_softc(dmaengine);
845 return (ioat->intrdelay_max);
849 ioat_acquire(bus_dmaengine_t dmaengine)
851 struct ioat_softc *ioat;
853 ioat = to_ioat_softc(dmaengine);
854 mtx_lock(&ioat->submit_lock);
855 CTR0(KTR_IOAT, __func__);
859 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags)
861 struct ioat_softc *ioat;
864 ioat = to_ioat_softc(dmaengine);
865 ioat_acquire(dmaengine);
867 error = ioat_reserve_space(ioat, n, mflags);
869 ioat_release(dmaengine);
874 ioat_release(bus_dmaengine_t dmaengine)
876 struct ioat_softc *ioat;
878 ioat = to_ioat_softc(dmaengine);
879 CTR0(KTR_IOAT, __func__);
880 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET, (uint16_t)ioat->hw_head);
881 mtx_unlock(&ioat->submit_lock);
884 static struct ioat_descriptor *
885 ioat_op_generic(struct ioat_softc *ioat, uint8_t op,
886 uint32_t size, uint64_t src, uint64_t dst,
887 bus_dmaengine_callback_t callback_fn, void *callback_arg,
890 struct ioat_generic_hw_descriptor *hw_desc;
891 struct ioat_descriptor *desc;
894 mtx_assert(&ioat->submit_lock, MA_OWNED);
896 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0,
897 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS));
898 if ((flags & DMA_NO_WAIT) != 0)
903 if (size > ioat->max_xfer_size) {
904 ioat_log_message(0, "%s: max_xfer_size = %d, requested = %u\n",
905 __func__, ioat->max_xfer_size, (unsigned)size);
909 if (ioat_reserve_space(ioat, 1, mflags) != 0)
912 desc = ioat_get_ring_entry(ioat, ioat->head);
913 hw_desc = desc->u.generic;
915 hw_desc->u.control_raw = 0;
916 hw_desc->u.control_generic.op = op;
917 hw_desc->u.control_generic.completion_update = 1;
919 if ((flags & DMA_INT_EN) != 0)
920 hw_desc->u.control_generic.int_enable = 1;
921 if ((flags & DMA_FENCE) != 0)
922 hw_desc->u.control_generic.fence = 1;
924 hw_desc->size = size;
925 hw_desc->src_addr = src;
926 hw_desc->dest_addr = dst;
928 desc->bus_dmadesc.callback_fn = callback_fn;
929 desc->bus_dmadesc.callback_arg = callback_arg;
934 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn,
935 void *callback_arg, uint32_t flags)
937 struct ioat_dma_hw_descriptor *hw_desc;
938 struct ioat_descriptor *desc;
939 struct ioat_softc *ioat;
941 CTR0(KTR_IOAT, __func__);
942 ioat = to_ioat_softc(dmaengine);
944 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn,
945 callback_arg, flags);
949 hw_desc = desc->u.dma;
950 hw_desc->u.control.null = 1;
951 ioat_submit_single(ioat);
952 return (&desc->bus_dmadesc);
956 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
957 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
958 void *callback_arg, uint32_t flags)
960 struct ioat_dma_hw_descriptor *hw_desc;
961 struct ioat_descriptor *desc;
962 struct ioat_softc *ioat;
964 CTR0(KTR_IOAT, __func__);
965 ioat = to_ioat_softc(dmaengine);
967 if (((src | dst) & (0xffffull << 48)) != 0) {
968 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n",
973 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
974 callback_arg, flags);
978 hw_desc = desc->u.dma;
979 if (g_ioat_debug_level >= 3)
980 dump_descriptor(hw_desc);
982 ioat_submit_single(ioat);
983 return (&desc->bus_dmadesc);
987 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
988 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
989 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
991 struct ioat_dma_hw_descriptor *hw_desc;
992 struct ioat_descriptor *desc;
993 struct ioat_softc *ioat;
995 CTR0(KTR_IOAT, __func__);
996 ioat = to_ioat_softc(dmaengine);
998 if (((src1 | src2 | dst1 | dst2) & (0xffffull << 48)) != 0) {
999 ioat_log_message(0, "%s: High 16 bits of src/dst invalid\n",
1003 if (((src1 | src2 | dst1 | dst2) & PAGE_MASK) != 0) {
1004 ioat_log_message(0, "%s: Addresses must be page-aligned\n",
1009 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, src1, dst1,
1010 callback_fn, callback_arg, flags);
1014 hw_desc = desc->u.dma;
1015 if (src2 != src1 + PAGE_SIZE) {
1016 hw_desc->u.control.src_page_break = 1;
1017 hw_desc->next_src_addr = src2;
1019 if (dst2 != dst1 + PAGE_SIZE) {
1020 hw_desc->u.control.dest_page_break = 1;
1021 hw_desc->next_dest_addr = dst2;
1024 if (g_ioat_debug_level >= 3)
1025 dump_descriptor(hw_desc);
1027 ioat_submit_single(ioat);
1028 return (&desc->bus_dmadesc);
1031 struct bus_dmadesc *
1032 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
1033 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
1034 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1036 struct ioat_crc32_hw_descriptor *hw_desc;
1037 struct ioat_descriptor *desc;
1038 struct ioat_softc *ioat;
1042 CTR0(KTR_IOAT, __func__);
1043 ioat = to_ioat_softc(dmaengine);
1045 if ((ioat->capabilities & IOAT_DMACAP_MOVECRC) == 0) {
1046 ioat_log_message(0, "%s: Device lacks MOVECRC capability\n",
1050 if (((src | dst) & (0xffffffull << 40)) != 0) {
1051 ioat_log_message(0, "%s: High 24 bits of src/dst invalid\n",
1055 teststore = (flags & _DMA_CRC_TESTSTORE);
1056 if (teststore == _DMA_CRC_TESTSTORE) {
1057 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
1060 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
1061 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
1066 switch (teststore) {
1068 op = IOAT_OP_MOVECRC_STORE;
1071 op = IOAT_OP_MOVECRC_TEST;
1074 KASSERT(teststore == 0, ("bogus"));
1075 op = IOAT_OP_MOVECRC;
1079 if ((flags & DMA_CRC_INLINE) == 0 &&
1080 (crcptr & (0xffffffull << 40)) != 0) {
1082 "%s: High 24 bits of crcptr invalid\n", __func__);
1086 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
1087 callback_arg, flags & ~_DMA_CRC_FLAGS);
1091 hw_desc = desc->u.crc32;
1093 if ((flags & DMA_CRC_INLINE) == 0)
1094 hw_desc->crc_address = crcptr;
1096 hw_desc->u.control.crc_location = 1;
1098 if (initialseed != NULL) {
1099 hw_desc->u.control.use_seed = 1;
1100 hw_desc->seed = *initialseed;
1103 if (g_ioat_debug_level >= 3)
1104 dump_descriptor(hw_desc);
1106 ioat_submit_single(ioat);
1107 return (&desc->bus_dmadesc);
1110 struct bus_dmadesc *
1111 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
1112 uint32_t *initialseed, bus_addr_t crcptr,
1113 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1115 struct ioat_crc32_hw_descriptor *hw_desc;
1116 struct ioat_descriptor *desc;
1117 struct ioat_softc *ioat;
1121 CTR0(KTR_IOAT, __func__);
1122 ioat = to_ioat_softc(dmaengine);
1124 if ((ioat->capabilities & IOAT_DMACAP_CRC) == 0) {
1125 ioat_log_message(0, "%s: Device lacks CRC capability\n",
1129 if ((src & (0xffffffull << 40)) != 0) {
1130 ioat_log_message(0, "%s: High 24 bits of src invalid\n",
1134 teststore = (flags & _DMA_CRC_TESTSTORE);
1135 if (teststore == _DMA_CRC_TESTSTORE) {
1136 ioat_log_message(0, "%s: TEST and STORE invalid\n", __func__);
1139 if (teststore == 0 && (flags & DMA_CRC_INLINE) != 0) {
1140 ioat_log_message(0, "%s: INLINE invalid without TEST or STORE\n",
1145 switch (teststore) {
1147 op = IOAT_OP_CRC_STORE;
1150 op = IOAT_OP_CRC_TEST;
1153 KASSERT(teststore == 0, ("bogus"));
1158 if ((flags & DMA_CRC_INLINE) == 0 &&
1159 (crcptr & (0xffffffull << 40)) != 0) {
1161 "%s: High 24 bits of crcptr invalid\n", __func__);
1165 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
1166 callback_arg, flags & ~_DMA_CRC_FLAGS);
1170 hw_desc = desc->u.crc32;
1172 if ((flags & DMA_CRC_INLINE) == 0)
1173 hw_desc->crc_address = crcptr;
1175 hw_desc->u.control.crc_location = 1;
1177 if (initialseed != NULL) {
1178 hw_desc->u.control.use_seed = 1;
1179 hw_desc->seed = *initialseed;
1182 if (g_ioat_debug_level >= 3)
1183 dump_descriptor(hw_desc);
1185 ioat_submit_single(ioat);
1186 return (&desc->bus_dmadesc);
1189 struct bus_dmadesc *
1190 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
1191 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg,
1194 struct ioat_fill_hw_descriptor *hw_desc;
1195 struct ioat_descriptor *desc;
1196 struct ioat_softc *ioat;
1198 CTR0(KTR_IOAT, __func__);
1199 ioat = to_ioat_softc(dmaengine);
1201 if ((ioat->capabilities & IOAT_DMACAP_BFILL) == 0) {
1202 ioat_log_message(0, "%s: Device lacks BFILL capability\n",
1207 if ((dst & (0xffffull << 48)) != 0) {
1208 ioat_log_message(0, "%s: High 16 bits of dst invalid\n",
1213 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, fillpattern, dst,
1214 callback_fn, callback_arg, flags);
1218 hw_desc = desc->u.fill;
1219 if (g_ioat_debug_level >= 3)
1220 dump_descriptor(hw_desc);
1222 ioat_submit_single(ioat);
1223 return (&desc->bus_dmadesc);
1229 static inline uint32_t
1230 ioat_get_active(struct ioat_softc *ioat)
1233 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1));
1236 static inline uint32_t
1237 ioat_get_ring_space(struct ioat_softc *ioat)
1240 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1);
1243 static struct ioat_descriptor *
1244 ioat_alloc_ring_entry(struct ioat_softc *ioat, int mflags)
1246 struct ioat_generic_hw_descriptor *hw_desc;
1247 struct ioat_descriptor *desc;
1248 int error, busdmaflag;
1253 if ((mflags & M_WAITOK) != 0)
1254 busdmaflag = BUS_DMA_WAITOK;
1256 busdmaflag = BUS_DMA_NOWAIT;
1258 desc = malloc(sizeof(*desc), M_IOAT, mflags);
1262 bus_dmamem_alloc(ioat->hw_desc_tag, (void **)&hw_desc,
1263 BUS_DMA_ZERO | busdmaflag, &ioat->hw_desc_map);
1264 if (hw_desc == NULL)
1267 memset(&desc->bus_dmadesc, 0, sizeof(desc->bus_dmadesc));
1268 desc->u.generic = hw_desc;
1270 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc,
1271 sizeof(*hw_desc), ioat_dmamap_cb, &desc->hw_desc_bus_addr,
1278 ioat_free_ring_entry(ioat, desc);
1285 ioat_free_ring_entry(struct ioat_softc *ioat, struct ioat_descriptor *desc)
1291 if (desc->u.generic)
1292 bus_dmamem_free(ioat->hw_desc_tag, desc->u.generic,
1298 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain
1301 * If mflags contains M_WAITOK, blocks until enough space is available.
1303 * Returns zero on success, or an errno on error. If num_descs is beyond the
1304 * maximum ring size, returns EINVAl; if allocation would block and mflags
1305 * contains M_NOWAIT, returns EAGAIN.
1307 * Must be called with the submit_lock held; returns with the lock held. The
1308 * lock may be dropped to allocate the ring.
1310 * (The submit_lock is needed to add any entries to the ring, so callers are
1311 * assured enough room is available.)
1314 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags)
1316 struct ioat_descriptor **new_ring;
1320 mtx_assert(&ioat->submit_lock, MA_OWNED);
1323 if (num_descs < 1 || num_descs > (1 << IOAT_MAX_ORDER)) {
1327 if (ioat->quiescing) {
1333 if (ioat_get_ring_space(ioat) >= num_descs)
1336 order = ioat->ring_size_order;
1337 if (ioat->is_resize_pending || order == IOAT_MAX_ORDER) {
1338 if ((mflags & M_WAITOK) != 0) {
1339 msleep(&ioat->tail, &ioat->submit_lock, 0,
1348 ioat->is_resize_pending = TRUE;
1350 mtx_unlock(&ioat->submit_lock);
1352 new_ring = ioat_prealloc_ring(ioat, 1 << (order + 1),
1355 mtx_lock(&ioat->submit_lock);
1356 KASSERT(ioat->ring_size_order == order,
1357 ("is_resize_pending should protect order"));
1359 if (new_ring == NULL) {
1360 KASSERT((mflags & M_WAITOK) == 0,
1361 ("allocation failed"));
1366 error = ring_grow(ioat, order, new_ring);
1370 ioat->is_resize_pending = FALSE;
1371 wakeup(&ioat->tail);
1377 mtx_assert(&ioat->submit_lock, MA_OWNED);
1381 static struct ioat_descriptor **
1382 ioat_prealloc_ring(struct ioat_softc *ioat, uint32_t size, boolean_t need_dscr,
1385 struct ioat_descriptor **ring;
1389 KASSERT(size > 0 && powerof2(size), ("bogus size"));
1391 ring = malloc(size * sizeof(*ring), M_IOAT, M_ZERO | mflags);
1397 for (i = size / 2; i < size; i++) {
1398 ring[i] = ioat_alloc_ring_entry(ioat, mflags);
1399 if (ring[i] == NULL)
1407 if (error != 0 && ring != NULL) {
1408 ioat_free_ring(ioat, size, ring);
1415 ioat_free_ring(struct ioat_softc *ioat, uint32_t size,
1416 struct ioat_descriptor **ring)
1420 for (i = 0; i < size; i++) {
1421 if (ring[i] != NULL)
1422 ioat_free_ring_entry(ioat, ring[i]);
1427 static struct ioat_descriptor *
1428 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index)
1431 return (ioat->ring[index % (1 << ioat->ring_size_order)]);
1435 ring_grow(struct ioat_softc *ioat, uint32_t oldorder,
1436 struct ioat_descriptor **newring)
1438 struct ioat_descriptor *tmp, *next;
1439 struct ioat_dma_hw_descriptor *hw;
1440 uint32_t oldsize, newsize, head, tail, i, end;
1443 CTR0(KTR_IOAT, __func__);
1445 mtx_assert(&ioat->submit_lock, MA_OWNED);
1447 if (oldorder != ioat->ring_size_order || oldorder >= IOAT_MAX_ORDER) {
1452 oldsize = (1 << oldorder);
1453 newsize = (1 << (oldorder + 1));
1455 mtx_lock(&ioat->cleanup_lock);
1457 head = ioat->head & (oldsize - 1);
1458 tail = ioat->tail & (oldsize - 1);
1460 /* Copy old descriptors to new ring */
1461 for (i = 0; i < oldsize; i++)
1462 newring[i] = ioat->ring[i];
1465 * If head has wrapped but tail hasn't, we must swap some descriptors
1466 * around so that tail can increment directly to head.
1469 for (i = 0; i <= head; i++) {
1470 tmp = newring[oldsize + i];
1472 newring[oldsize + i] = newring[i];
1473 newring[oldsize + i]->id = oldsize + i;
1481 KASSERT(head >= tail, ("invariants"));
1483 /* Head didn't wrap; we only need to link in oldsize..newsize */
1484 if (head < oldsize) {
1488 /* Head did wrap; link newhead..newsize and 0..oldhead */
1490 end = newsize + (head - oldsize) + 1;
1494 * Fix up hardware ring, being careful not to trample the active
1495 * section (tail -> head).
1497 for (; i < end; i++) {
1498 KASSERT((i & (newsize - 1)) < tail ||
1499 (i & (newsize - 1)) >= head, ("trampling snake"));
1501 next = newring[(i + 1) & (newsize - 1)];
1502 hw = newring[i & (newsize - 1)]->u.dma;
1503 hw->next = next->hw_desc_bus_addr;
1506 free(ioat->ring, M_IOAT);
1507 ioat->ring = newring;
1508 ioat->ring_size_order = oldorder + 1;
1513 mtx_unlock(&ioat->cleanup_lock);
1516 ioat_free_ring(ioat, (1 << (oldorder + 1)), newring);
1521 ring_shrink(struct ioat_softc *ioat, uint32_t oldorder,
1522 struct ioat_descriptor **newring)
1524 struct ioat_dma_hw_descriptor *hw;
1525 struct ioat_descriptor *ent, *next;
1526 uint32_t oldsize, newsize, current_idx, new_idx, i;
1529 CTR0(KTR_IOAT, __func__);
1531 mtx_assert(&ioat->submit_lock, MA_OWNED);
1533 if (oldorder != ioat->ring_size_order || oldorder <= IOAT_MIN_ORDER) {
1538 oldsize = (1 << oldorder);
1539 newsize = (1 << (oldorder - 1));
1541 mtx_lock(&ioat->cleanup_lock);
1543 /* Can't shrink below current active set! */
1544 if (ioat_get_active(ioat) >= newsize) {
1550 * Copy current descriptors to the new ring, dropping the removed
1553 for (i = 0; i < newsize; i++) {
1554 current_idx = (ioat->tail + i) & (oldsize - 1);
1555 new_idx = (ioat->tail + i) & (newsize - 1);
1557 newring[new_idx] = ioat->ring[current_idx];
1558 newring[new_idx]->id = new_idx;
1561 /* Free deleted descriptors */
1562 for (i = newsize; i < oldsize; i++) {
1563 ent = ioat_get_ring_entry(ioat, ioat->tail + i);
1564 ioat_free_ring_entry(ioat, ent);
1567 /* Fix up hardware ring. */
1568 hw = newring[(ioat->tail + newsize - 1) & (newsize - 1)]->u.dma;
1569 next = newring[(ioat->tail + newsize) & (newsize - 1)];
1570 hw->next = next->hw_desc_bus_addr;
1572 free(ioat->ring, M_IOAT);
1573 ioat->ring = newring;
1574 ioat->ring_size_order = oldorder - 1;
1578 mtx_unlock(&ioat->cleanup_lock);
1581 ioat_free_ring(ioat, (1 << (oldorder - 1)), newring);
1586 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr)
1588 struct ioat_descriptor *desc;
1590 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr,
1595 mtx_assert(&ioat->cleanup_lock, MA_OWNED);
1597 desc = ioat_get_ring_entry(ioat, ioat->tail + 0);
1598 dump_descriptor(desc->u.raw);
1600 desc = ioat_get_ring_entry(ioat, ioat->tail + 1);
1601 dump_descriptor(desc->u.raw);
1605 ioat_timer_callback(void *arg)
1607 struct ioat_descriptor **newring;
1608 struct ioat_softc *ioat;
1612 ioat_log_message(1, "%s\n", __func__);
1614 if (ioat->is_completion_pending) {
1615 ioat_process_events(ioat);
1619 /* Slowly scale the ring down if idle. */
1620 mtx_lock(&ioat->submit_lock);
1621 order = ioat->ring_size_order;
1622 if (ioat->is_resize_pending || order == IOAT_MIN_ORDER) {
1623 mtx_unlock(&ioat->submit_lock);
1626 ioat->is_resize_pending = TRUE;
1627 mtx_unlock(&ioat->submit_lock);
1629 newring = ioat_prealloc_ring(ioat, 1 << (order - 1), FALSE,
1632 mtx_lock(&ioat->submit_lock);
1633 KASSERT(ioat->ring_size_order == order,
1634 ("resize_pending protects order"));
1636 if (newring != NULL)
1637 ring_shrink(ioat, order, newring);
1639 ioat->is_resize_pending = FALSE;
1640 mtx_unlock(&ioat->submit_lock);
1643 if (ioat->ring_size_order > IOAT_MIN_ORDER)
1644 callout_reset(&ioat->timer, 10 * hz,
1645 ioat_timer_callback, ioat);
1652 ioat_submit_single(struct ioat_softc *ioat)
1655 ioat_get(ioat, IOAT_ACTIVE_DESCR_REF);
1656 atomic_add_rel_int(&ioat->head, 1);
1657 atomic_add_rel_int(&ioat->hw_head, 1);
1659 if (!ioat->is_completion_pending) {
1660 ioat->is_completion_pending = TRUE;
1661 callout_reset(&ioat->timer, IOAT_INTR_TIMO,
1662 ioat_timer_callback, ioat);
1665 ioat->stats.descriptors_submitted++;
1669 ioat_reset_hw(struct ioat_softc *ioat)
1676 mtx_lock(IOAT_REFLK);
1677 ioat->quiescing = TRUE;
1678 ioat_drain_locked(ioat);
1679 mtx_unlock(IOAT_REFLK);
1681 status = ioat_get_chansts(ioat);
1682 if (is_ioat_active(status) || is_ioat_idle(status))
1685 /* Wait at most 20 ms */
1686 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) &&
1687 timeout < 20; timeout++) {
1689 status = ioat_get_chansts(ioat);
1691 if (timeout == 20) {
1696 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce"));
1698 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1699 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
1702 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors
1703 * that can cause stability issues for IOAT v3.
1705 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07,
1707 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4);
1708 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4);
1711 * BDXDE and BWD models reset MSI-X registers on device reset.
1712 * Save/restore their contents manually.
1714 if (ioat_model_resets_msix(ioat)) {
1715 ioat_log_message(1, "device resets MSI-X registers; saving\n");
1716 pci_save_state(ioat->device);
1721 /* Wait at most 20 ms */
1722 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++)
1724 if (timeout == 20) {
1729 if (ioat_model_resets_msix(ioat)) {
1730 ioat_log_message(1, "device resets registers; restored\n");
1731 pci_restore_state(ioat->device);
1734 /* Reset attempts to return the hardware to "halted." */
1735 status = ioat_get_chansts(ioat);
1736 if (is_ioat_active(status) || is_ioat_idle(status)) {
1737 /* So this really shouldn't happen... */
1738 ioat_log_message(0, "Device is active after a reset?\n");
1739 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1744 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1746 mtx_lock(&ioat->cleanup_lock);
1747 ioat_halted_debug(ioat, chanerr);
1748 mtx_unlock(&ioat->cleanup_lock);
1754 * Bring device back online after reset. Writing CHAINADDR brings the
1755 * device back to active.
1757 * The internal ring counter resets to zero, so we have to start over
1760 ioat->tail = ioat->head = ioat->hw_head = 0;
1761 ioat->last_seen = 0;
1763 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1764 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);
1765 ioat_write_chainaddr(ioat, ioat->ring[0]->hw_desc_bus_addr);
1769 mtx_lock(IOAT_REFLK);
1770 ioat->quiescing = FALSE;
1771 wakeup(&ioat->quiescing);
1772 mtx_unlock(IOAT_REFLK);
1775 error = ioat_start_channel(ioat);
1781 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)
1783 struct ioat_softc *ioat;
1790 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
1792 sbuf_new_for_sysctl(&sb, NULL, 256, req);
1794 case IOAT_CHANSTS_ACTIVE:
1795 sbuf_printf(&sb, "ACTIVE");
1797 case IOAT_CHANSTS_IDLE:
1798 sbuf_printf(&sb, "IDLE");
1800 case IOAT_CHANSTS_SUSPENDED:
1801 sbuf_printf(&sb, "SUSPENDED");
1803 case IOAT_CHANSTS_HALTED:
1804 sbuf_printf(&sb, "HALTED");
1806 case IOAT_CHANSTS_ARMED:
1807 sbuf_printf(&sb, "ARMED");
1810 sbuf_printf(&sb, "UNKNOWN");
1813 error = sbuf_finish(&sb);
1816 if (error != 0 || req->newptr == NULL)
1822 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)
1824 struct ioat_softc *ioat;
1826 #define PRECISION "1"
1827 const uintmax_t factor = 10;
1832 sbuf_new_for_sysctl(&sb, NULL, 16, req);
1834 if (ioat->stats.interrupts == 0) {
1835 sbuf_printf(&sb, "NaN");
1838 rate = ioat->stats.descriptors_processed * factor /
1839 ioat->stats.interrupts;
1840 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor,
1844 error = sbuf_finish(&sb);
1846 if (error != 0 || req->newptr == NULL)
1852 sysctl_handle_error(SYSCTL_HANDLER_ARGS)
1854 struct ioat_descriptor *desc;
1855 struct ioat_softc *ioat;
1861 error = SYSCTL_OUT(req, &arg, sizeof(arg));
1862 if (error != 0 || req->newptr == NULL)
1865 error = SYSCTL_IN(req, &arg, sizeof(arg));
1870 ioat_acquire(&ioat->dmaengine);
1871 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 1,
1872 0xffff000000000000ull, 0xffff000000000000ull, NULL, NULL,
1877 ioat_submit_single(ioat);
1878 ioat_release(&ioat->dmaengine);
1884 sysctl_handle_reset(SYSCTL_HANDLER_ARGS)
1886 struct ioat_softc *ioat;
1892 error = SYSCTL_OUT(req, &arg, sizeof(arg));
1893 if (error != 0 || req->newptr == NULL)
1896 error = SYSCTL_IN(req, &arg, sizeof(arg));
1901 error = ioat_reset_hw(ioat);
1907 dump_descriptor(void *hw_desc)
1911 for (i = 0; i < 2; i++) {
1912 for (j = 0; j < 8; j++)
1913 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]);
1919 ioat_setup_sysctl(device_t device)
1921 struct sysctl_oid_list *par, *statpar, *state, *hammer;
1922 struct sysctl_ctx_list *ctx;
1923 struct sysctl_oid *tree, *tmp;
1924 struct ioat_softc *ioat;
1926 ioat = DEVICE2SOFTC(device);
1927 ctx = device_get_sysctl_ctx(device);
1928 tree = device_get_sysctl_tree(device);
1929 par = SYSCTL_CHILDREN(tree);
1931 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD,
1932 &ioat->version, 0, "HW version (0xMM form)");
1933 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD,
1934 &ioat->max_xfer_size, 0, "HW maximum transfer size");
1935 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD,
1936 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported");
1937 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD,
1938 &ioat->intrdelay_max, 0,
1939 "Maximum configurable INTRDELAY on this channel (microseconds)");
1941 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL,
1942 "IOAT channel internal state");
1943 state = SYSCTL_CHILDREN(tmp);
1945 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD,
1946 &ioat->ring_size_order, 0, "SW descriptor ring size order");
1947 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head,
1948 0, "SW descriptor head pointer index");
1949 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail,
1950 0, "SW descriptor tail pointer index");
1951 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "hw_head", CTLFLAG_RD,
1952 &ioat->hw_head, 0, "HW DMACOUNT");
1954 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD,
1955 ioat->comp_update, "HW addr of last completion");
1957 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_resize_pending", CTLFLAG_RD,
1958 &ioat->is_resize_pending, 0, "resize pending");
1959 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_completion_pending",
1960 CTLFLAG_RD, &ioat->is_completion_pending, 0, "completion pending");
1961 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_reset_pending", CTLFLAG_RD,
1962 &ioat->is_reset_pending, 0, "reset pending");
1963 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_channel_running", CTLFLAG_RD,
1964 &ioat->is_channel_running, 0, "channel running");
1966 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts",
1967 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A",
1968 "String of the channel status");
1970 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD,
1971 &ioat->cached_intrdelay, 0,
1972 "Current INTRDELAY on this channel (cached, microseconds)");
1974 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL,
1975 "Big hammers (mostly for testing)");
1976 hammer = SYSCTL_CHILDREN(tmp);
1978 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset",
1979 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I",
1980 "Set to non-zero to reset the hardware");
1981 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_error",
1982 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_error, "I",
1983 "Set to non-zero to inject a recoverable hardware error");
1985 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL,
1986 "IOAT channel statistics");
1987 statpar = SYSCTL_CHILDREN(tmp);
1989 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts", CTLFLAG_RW,
1990 &ioat->stats.interrupts,
1991 "Number of interrupts processed on this channel");
1992 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors", CTLFLAG_RW,
1993 &ioat->stats.descriptors_processed,
1994 "Number of descriptors processed on this channel");
1995 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted", CTLFLAG_RW,
1996 &ioat->stats.descriptors_submitted,
1997 "Number of descriptors submitted to this channel");
1998 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored", CTLFLAG_RW,
1999 &ioat->stats.descriptors_error,
2000 "Number of descriptors failed by channel errors");
2001 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts", CTLFLAG_RW,
2002 &ioat->stats.channel_halts, 0,
2003 "Number of times the channel has halted");
2004 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr", CTLFLAG_RW,
2005 &ioat->stats.last_halt_chanerr, 0,
2006 "The raw CHANERR when the channel was last halted");
2008 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt",
2009 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A",
2010 "Descriptors per interrupt");
2013 static inline struct ioat_softc *
2014 ioat_get(struct ioat_softc *ioat, enum ioat_ref_kind kind)
2018 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus"));
2020 old = atomic_fetchadd_32(&ioat->refcnt, 1);
2021 KASSERT(old < UINT32_MAX, ("refcnt overflow"));
2024 old = atomic_fetchadd_32(&ioat->refkinds[kind], 1);
2025 KASSERT(old < UINT32_MAX, ("refcnt kind overflow"));
2032 ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind)
2035 _ioat_putn(ioat, n, kind, FALSE);
2039 ioat_putn_locked(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind)
2042 _ioat_putn(ioat, n, kind, TRUE);
2046 _ioat_putn(struct ioat_softc *ioat, uint32_t n, enum ioat_ref_kind kind,
2051 KASSERT(kind < IOAT_NUM_REF_KINDS, ("bogus"));
2057 old = atomic_fetchadd_32(&ioat->refkinds[kind], -n);
2058 KASSERT(old >= n, ("refcnt kind underflow"));
2061 /* Skip acquiring the lock if resulting refcnt > 0. */
2066 if (atomic_cmpset_32(&ioat->refcnt, old, old - n))
2071 mtx_assert(IOAT_REFLK, MA_OWNED);
2073 mtx_lock(IOAT_REFLK);
2075 old = atomic_fetchadd_32(&ioat->refcnt, -n);
2076 KASSERT(old >= n, ("refcnt error"));
2081 mtx_unlock(IOAT_REFLK);
2085 ioat_put(struct ioat_softc *ioat, enum ioat_ref_kind kind)
2088 ioat_putn(ioat, 1, kind);
2092 ioat_drain_locked(struct ioat_softc *ioat)
2095 mtx_assert(IOAT_REFLK, MA_OWNED);
2096 while (ioat->refcnt > 0)
2097 msleep(IOAT_REFLK, IOAT_REFLK, 0, "ioat_drain", 0);
2101 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo)
2102 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object)
2103 DB_SHOW_COMMAND(ioat, db_show_ioat)
2105 struct ioat_softc *sc;
2110 idx = (unsigned)addr;
2111 if (addr >= ioat_channel_index)
2114 sc = ioat_channel[idx];
2115 db_printf("ioat softc at %p\n", sc);
2119 db_printf(" version: %d\n", sc->version);
2120 db_printf(" chan_idx: %u\n", sc->chan_idx);
2121 db_printf(" submit_lock: ");
2122 db_show_lock(&sc->submit_lock);
2124 db_printf(" capabilities: %b\n", (int)sc->capabilities,
2126 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay);
2127 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update);
2129 db_printf(" timer:\n");
2130 db_printf(" c_time: %ju\n", (uintmax_t)sc->timer.c_time);
2131 db_printf(" c_arg: %p\n", sc->timer.c_arg);
2132 db_printf(" c_func: %p\n", sc->timer.c_func);
2133 db_printf(" c_lock: %p\n", sc->timer.c_lock);
2134 db_printf(" c_flags: 0x%x\n", (unsigned)sc->timer.c_flags);
2136 db_printf(" quiescing: %d\n", (int)sc->quiescing);
2137 db_printf(" destroying: %d\n", (int)sc->destroying);
2138 db_printf(" is_resize_pending: %d\n", (int)sc->is_resize_pending);
2139 db_printf(" is_completion_pending: %d\n", (int)sc->is_completion_pending);
2140 db_printf(" is_reset_pending: %d\n", (int)sc->is_reset_pending);
2141 db_printf(" is_channel_running: %d\n", (int)sc->is_channel_running);
2142 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported);
2144 db_printf(" head: %u\n", sc->head);
2145 db_printf(" tail: %u\n", sc->tail);
2146 db_printf(" hw_head: %u\n", sc->hw_head);
2147 db_printf(" ring_size_order: %u\n", sc->ring_size_order);
2148 db_printf(" last_seen: 0x%lx\n", sc->last_seen);
2149 db_printf(" ring: %p\n", sc->ring);
2151 db_printf(" cleanup_lock: ");
2152 db_show_lock(&sc->cleanup_lock);
2154 db_printf(" refcnt: %u\n", sc->refcnt);
2156 CTASSERT(IOAT_NUM_REF_KINDS == 2);
2157 db_printf(" refkinds: [ENG=%u, DESCR=%u]\n", sc->refkinds[0],
2160 db_printf(" stats:\n");
2161 db_printf(" interrupts: %lu\n", sc->stats.interrupts);
2162 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed);
2163 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error);
2164 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted);
2166 db_printf(" channel_halts: %u\n", sc->stats.channel_halts);
2167 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr);
2172 db_printf(" hw status:\n");
2173 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc));
2174 db_printf(" chanctrl: 0x%x\n",
2175 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET));
2176 db_printf(" chancmd: 0x%x\n",
2177 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET));
2178 db_printf(" dmacount: 0x%x\n",
2179 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET));
2180 db_printf(" chainaddr: 0x%lx\n",
2181 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW));
2182 db_printf(" chancmp: 0x%lx\n",
2183 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW));
2184 db_printf(" chanerr: %b\n",
2185 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR);
2188 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index);