2 * Copyright (C) 2012 Intel Corporation
4 * Copyright (C) 2018 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
37 #include <sys/domainset.h>
39 #include <sys/ioccom.h>
40 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
56 #include <machine/stdarg.h>
64 #include "ioat_internal.h"
66 #ifndef BUS_SPACE_MAXADDR_40BIT
67 #define BUS_SPACE_MAXADDR_40BIT MIN(BUS_SPACE_MAXADDR, 0xFFFFFFFFFFULL)
69 #ifndef BUS_SPACE_MAXADDR_46BIT
70 #define BUS_SPACE_MAXADDR_46BIT MIN(BUS_SPACE_MAXADDR, 0x3FFFFFFFFFFFULL)
73 static int ioat_probe(device_t device);
74 static int ioat_attach(device_t device);
75 static int ioat_detach(device_t device);
76 static int ioat_setup_intr(struct ioat_softc *ioat);
77 static int ioat_teardown_intr(struct ioat_softc *ioat);
78 static int ioat3_attach(device_t device);
79 static int ioat_start_channel(struct ioat_softc *ioat);
80 static int ioat_map_pci_bar(struct ioat_softc *ioat);
81 static void ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg,
83 static void ioat_interrupt_handler(void *arg);
84 static boolean_t ioat_model_resets_msix(struct ioat_softc *ioat);
85 static int chanerr_to_errno(uint32_t);
86 static void ioat_process_events(struct ioat_softc *ioat, boolean_t intr);
87 static inline uint32_t ioat_get_active(struct ioat_softc *ioat);
88 static inline uint32_t ioat_get_ring_space(struct ioat_softc *ioat);
89 static void ioat_free_ring(struct ioat_softc *, uint32_t size,
90 struct ioat_descriptor *);
91 static int ioat_reserve_space(struct ioat_softc *, uint32_t, int mflags);
92 static union ioat_hw_descriptor *ioat_get_descriptor(struct ioat_softc *,
94 static struct ioat_descriptor *ioat_get_ring_entry(struct ioat_softc *,
96 static void ioat_halted_debug(struct ioat_softc *, uint32_t);
97 static void ioat_poll_timer_callback(void *arg);
98 static void dump_descriptor(void *hw_desc);
99 static void ioat_submit_single(struct ioat_softc *ioat);
100 static void ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg,
102 static int ioat_reset_hw(struct ioat_softc *ioat);
103 static void ioat_reset_hw_task(void *, int);
104 static void ioat_setup_sysctl(device_t device);
105 static int sysctl_handle_reset(SYSCTL_HANDLER_ARGS);
106 static void ioat_get(struct ioat_softc *);
107 static void ioat_put(struct ioat_softc *);
108 static void ioat_drain_locked(struct ioat_softc *);
110 #define ioat_log_message(v, ...) do { \
111 if ((v) <= g_ioat_debug_level) { \
112 device_printf(ioat->device, __VA_ARGS__); \
116 MALLOC_DEFINE(M_IOAT, "ioat", "ioat driver memory allocations");
117 SYSCTL_NODE(_hw, OID_AUTO, ioat, CTLFLAG_RD, 0, "ioat node");
119 static int g_force_legacy_interrupts;
120 SYSCTL_INT(_hw_ioat, OID_AUTO, force_legacy_interrupts, CTLFLAG_RDTUN,
121 &g_force_legacy_interrupts, 0, "Set to non-zero to force MSI-X disabled");
123 int g_ioat_debug_level = 0;
124 SYSCTL_INT(_hw_ioat, OID_AUTO, debug_level, CTLFLAG_RWTUN, &g_ioat_debug_level,
125 0, "Set log level (0-3) for ioat(4). Higher is more verbose.");
127 unsigned g_ioat_ring_order = 13;
128 SYSCTL_UINT(_hw_ioat, OID_AUTO, ring_order, CTLFLAG_RDTUN, &g_ioat_ring_order,
129 0, "Set IOAT ring order. (1 << this) == ring size.");
132 * OS <-> Driver interface structures
134 static device_method_t ioat_pci_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, ioat_probe),
137 DEVMETHOD(device_attach, ioat_attach),
138 DEVMETHOD(device_detach, ioat_detach),
142 static driver_t ioat_pci_driver = {
145 sizeof(struct ioat_softc),
148 static devclass_t ioat_devclass;
149 DRIVER_MODULE(ioat, pci, ioat_pci_driver, ioat_devclass, 0, 0);
150 MODULE_VERSION(ioat, 1);
153 * Private data structures
155 static struct ioat_softc *ioat_channel[IOAT_MAX_CHANNELS];
156 static unsigned ioat_channel_index = 0;
157 SYSCTL_UINT(_hw_ioat, OID_AUTO, channels, CTLFLAG_RD, &ioat_channel_index, 0,
158 "Number of IOAT channels attached");
159 static struct mtx ioat_list_mtx;
160 MTX_SYSINIT(ioat_list_mtx, &ioat_list_mtx, "ioat list mtx", MTX_DEF);
167 { 0x34308086, "TBG IOAT Ch0" },
168 { 0x34318086, "TBG IOAT Ch1" },
169 { 0x34328086, "TBG IOAT Ch2" },
170 { 0x34338086, "TBG IOAT Ch3" },
171 { 0x34298086, "TBG IOAT Ch4" },
172 { 0x342a8086, "TBG IOAT Ch5" },
173 { 0x342b8086, "TBG IOAT Ch6" },
174 { 0x342c8086, "TBG IOAT Ch7" },
176 { 0x37108086, "JSF IOAT Ch0" },
177 { 0x37118086, "JSF IOAT Ch1" },
178 { 0x37128086, "JSF IOAT Ch2" },
179 { 0x37138086, "JSF IOAT Ch3" },
180 { 0x37148086, "JSF IOAT Ch4" },
181 { 0x37158086, "JSF IOAT Ch5" },
182 { 0x37168086, "JSF IOAT Ch6" },
183 { 0x37178086, "JSF IOAT Ch7" },
184 { 0x37188086, "JSF IOAT Ch0 (RAID)" },
185 { 0x37198086, "JSF IOAT Ch1 (RAID)" },
187 { 0x3c208086, "SNB IOAT Ch0" },
188 { 0x3c218086, "SNB IOAT Ch1" },
189 { 0x3c228086, "SNB IOAT Ch2" },
190 { 0x3c238086, "SNB IOAT Ch3" },
191 { 0x3c248086, "SNB IOAT Ch4" },
192 { 0x3c258086, "SNB IOAT Ch5" },
193 { 0x3c268086, "SNB IOAT Ch6" },
194 { 0x3c278086, "SNB IOAT Ch7" },
195 { 0x3c2e8086, "SNB IOAT Ch0 (RAID)" },
196 { 0x3c2f8086, "SNB IOAT Ch1 (RAID)" },
198 { 0x0e208086, "IVB IOAT Ch0" },
199 { 0x0e218086, "IVB IOAT Ch1" },
200 { 0x0e228086, "IVB IOAT Ch2" },
201 { 0x0e238086, "IVB IOAT Ch3" },
202 { 0x0e248086, "IVB IOAT Ch4" },
203 { 0x0e258086, "IVB IOAT Ch5" },
204 { 0x0e268086, "IVB IOAT Ch6" },
205 { 0x0e278086, "IVB IOAT Ch7" },
206 { 0x0e2e8086, "IVB IOAT Ch0 (RAID)" },
207 { 0x0e2f8086, "IVB IOAT Ch1 (RAID)" },
209 { 0x2f208086, "HSW IOAT Ch0" },
210 { 0x2f218086, "HSW IOAT Ch1" },
211 { 0x2f228086, "HSW IOAT Ch2" },
212 { 0x2f238086, "HSW IOAT Ch3" },
213 { 0x2f248086, "HSW IOAT Ch4" },
214 { 0x2f258086, "HSW IOAT Ch5" },
215 { 0x2f268086, "HSW IOAT Ch6" },
216 { 0x2f278086, "HSW IOAT Ch7" },
217 { 0x2f2e8086, "HSW IOAT Ch0 (RAID)" },
218 { 0x2f2f8086, "HSW IOAT Ch1 (RAID)" },
220 { 0x0c508086, "BWD IOAT Ch0" },
221 { 0x0c518086, "BWD IOAT Ch1" },
222 { 0x0c528086, "BWD IOAT Ch2" },
223 { 0x0c538086, "BWD IOAT Ch3" },
225 { 0x6f508086, "BDXDE IOAT Ch0" },
226 { 0x6f518086, "BDXDE IOAT Ch1" },
227 { 0x6f528086, "BDXDE IOAT Ch2" },
228 { 0x6f538086, "BDXDE IOAT Ch3" },
230 { 0x6f208086, "BDX IOAT Ch0" },
231 { 0x6f218086, "BDX IOAT Ch1" },
232 { 0x6f228086, "BDX IOAT Ch2" },
233 { 0x6f238086, "BDX IOAT Ch3" },
234 { 0x6f248086, "BDX IOAT Ch4" },
235 { 0x6f258086, "BDX IOAT Ch5" },
236 { 0x6f268086, "BDX IOAT Ch6" },
237 { 0x6f278086, "BDX IOAT Ch7" },
238 { 0x6f2e8086, "BDX IOAT Ch0 (RAID)" },
239 { 0x6f2f8086, "BDX IOAT Ch1 (RAID)" },
241 { 0x20218086, "SKX IOAT" },
244 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ioat, pci_ids,
248 * OS <-> Driver linkage functions
251 ioat_probe(device_t device)
256 type = pci_get_devid(device);
257 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) {
258 if (ep->type == type) {
259 device_set_desc(device, ep->desc);
267 ioat_attach(device_t device)
269 struct ioat_softc *ioat;
272 ioat = DEVICE2SOFTC(device);
273 ioat->device = device;
274 if (bus_get_domain(device, &ioat->domain) != 0)
276 ioat->cpu = CPU_FFS(&cpuset_domain[ioat->domain]) - 1;
278 ioat->cpu = CPU_FIRST();
280 error = ioat_map_pci_bar(ioat);
284 ioat->version = ioat_read_cbver(ioat);
285 if (ioat->version < IOAT_VER_3_0) {
290 error = ioat3_attach(device);
294 error = pci_enable_busmaster(device);
298 error = ioat_setup_intr(ioat);
302 error = ioat_reset_hw(ioat);
306 ioat_process_events(ioat, FALSE);
307 ioat_setup_sysctl(device);
309 mtx_lock(&ioat_list_mtx);
310 for (i = 0; i < IOAT_MAX_CHANNELS; i++) {
311 if (ioat_channel[i] == NULL)
314 if (i >= IOAT_MAX_CHANNELS) {
315 mtx_unlock(&ioat_list_mtx);
316 device_printf(device, "Too many I/OAT devices in system\n");
321 ioat_channel[i] = ioat;
322 if (i >= ioat_channel_index)
323 ioat_channel_index = i + 1;
324 mtx_unlock(&ioat_list_mtx);
335 ioat_bus_dmamap_destroy(struct ioat_softc *ioat, const char *func,
336 bus_dma_tag_t dmat, bus_dmamap_t map)
340 error = bus_dmamap_destroy(dmat, map);
343 "%s: bus_dmamap_destroy failed %d\n", func, error);
350 ioat_detach(device_t device)
352 struct ioat_softc *ioat;
355 ioat = DEVICE2SOFTC(device);
357 mtx_lock(&ioat_list_mtx);
358 ioat_channel[ioat->chan_idx] = NULL;
359 while (ioat_channel_index > 0 &&
360 ioat_channel[ioat_channel_index - 1] == NULL)
361 ioat_channel_index--;
362 mtx_unlock(&ioat_list_mtx);
365 taskqueue_drain(taskqueue_thread, &ioat->reset_task);
367 mtx_lock(&ioat->submit_lock);
368 ioat->quiescing = TRUE;
369 ioat->destroying = TRUE;
370 wakeup(&ioat->quiescing);
371 wakeup(&ioat->resetting);
373 ioat_drain_locked(ioat);
374 mtx_unlock(&ioat->submit_lock);
375 mtx_lock(&ioat->cleanup_lock);
376 while (ioat_get_active(ioat) > 0)
377 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1);
378 mtx_unlock(&ioat->cleanup_lock);
380 ioat_teardown_intr(ioat);
381 callout_drain(&ioat->poll_timer);
383 pci_disable_busmaster(device);
385 if (ioat->pci_resource != NULL)
386 bus_release_resource(device, SYS_RES_MEMORY,
387 ioat->pci_resource_id, ioat->pci_resource);
389 if (ioat->data_tag != NULL) {
390 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
391 error = ioat_bus_dmamap_destroy(ioat, __func__,
392 ioat->data_tag, ioat->ring[i].src_dmamap);
396 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
397 error = ioat_bus_dmamap_destroy(ioat, __func__,
398 ioat->data_tag, ioat->ring[i].dst_dmamap);
403 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
404 error = ioat_bus_dmamap_destroy(ioat, __func__,
405 ioat->data_tag, ioat->ring[i].src2_dmamap);
409 for (i = 0; i < 1 << ioat->ring_size_order; i++) {
410 error = ioat_bus_dmamap_destroy(ioat, __func__,
411 ioat->data_tag, ioat->ring[i].dst2_dmamap);
416 bus_dma_tag_destroy(ioat->data_tag);
419 if (ioat->ring != NULL)
420 ioat_free_ring(ioat, 1 << ioat->ring_size_order, ioat->ring);
422 if (ioat->comp_update != NULL) {
423 bus_dmamap_unload(ioat->comp_update_tag, ioat->comp_update_map);
424 bus_dmamem_free(ioat->comp_update_tag, ioat->comp_update,
425 ioat->comp_update_map);
426 bus_dma_tag_destroy(ioat->comp_update_tag);
429 if (ioat->hw_desc_ring != NULL) {
430 bus_dmamap_unload(ioat->hw_desc_tag, ioat->hw_desc_map);
431 bus_dmamem_free(ioat->hw_desc_tag, ioat->hw_desc_ring,
433 bus_dma_tag_destroy(ioat->hw_desc_tag);
440 ioat_teardown_intr(struct ioat_softc *ioat)
443 if (ioat->tag != NULL)
444 bus_teardown_intr(ioat->device, ioat->res, ioat->tag);
446 if (ioat->res != NULL)
447 bus_release_resource(ioat->device, SYS_RES_IRQ,
448 rman_get_rid(ioat->res), ioat->res);
450 pci_release_msi(ioat->device);
455 ioat_start_channel(struct ioat_softc *ioat)
457 struct ioat_dma_hw_descriptor *hw_desc;
458 struct ioat_descriptor *desc;
459 struct bus_dmadesc *dmadesc;
464 ioat_acquire(&ioat->dmaengine);
466 /* Submit 'NULL' operation manually to avoid quiescing flag */
467 desc = ioat_get_ring_entry(ioat, ioat->head);
468 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->dma;
469 dmadesc = &desc->bus_dmadesc;
471 dmadesc->callback_fn = NULL;
472 dmadesc->callback_arg = NULL;
474 hw_desc->u.control_raw = 0;
475 hw_desc->u.control_generic.op = IOAT_OP_COPY;
476 hw_desc->u.control_generic.completion_update = 1;
478 hw_desc->src_addr = 0;
479 hw_desc->dest_addr = 0;
480 hw_desc->u.control.null = 1;
482 ioat_submit_single(ioat);
483 ioat_release(&ioat->dmaengine);
485 for (i = 0; i < 100; i++) {
487 status = ioat_get_chansts(ioat);
488 if (is_ioat_idle(status))
492 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
493 ioat_log_message(0, "could not start channel: "
494 "status = %#jx error = %b\n", (uintmax_t)status, (int)chanerr,
500 * Initialize Hardware
503 ioat3_attach(device_t device)
505 struct ioat_softc *ioat;
506 struct ioat_descriptor *ring;
507 struct ioat_dma_hw_descriptor *dma_hw_desc;
511 int i, num_descriptors;
516 ioat = DEVICE2SOFTC(device);
517 ioat->capabilities = ioat_read_dmacapability(ioat);
519 ioat_log_message(0, "Capabilities: %b\n", (int)ioat->capabilities,
522 xfercap = ioat_read_xfercap(ioat);
523 ioat->max_xfer_size = 1 << xfercap;
525 ioat->intrdelay_supported = (ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) &
526 IOAT_INTRDELAY_SUPPORTED) != 0;
527 if (ioat->intrdelay_supported)
528 ioat->intrdelay_max = IOAT_INTRDELAY_US_MASK;
530 /* TODO: need to check DCA here if we ever do XOR/PQ */
532 mtx_init(&ioat->submit_lock, "ioat_submit", NULL, MTX_DEF);
533 mtx_init(&ioat->cleanup_lock, "ioat_cleanup", NULL, MTX_DEF);
534 callout_init(&ioat->poll_timer, 1);
535 TASK_INIT(&ioat->reset_task, 0, ioat_reset_hw_task, ioat);
537 /* Establish lock order for Witness */
538 mtx_lock(&ioat->cleanup_lock);
539 mtx_lock(&ioat->submit_lock);
540 mtx_unlock(&ioat->submit_lock);
541 mtx_unlock(&ioat->cleanup_lock);
543 ioat->is_submitter_processing = FALSE;
545 if (ioat->version >= IOAT_VER_3_3)
546 lowaddr = BUS_SPACE_MAXADDR_48BIT;
547 else if (ioat->version >= IOAT_VER_3_2)
548 lowaddr = BUS_SPACE_MAXADDR_46BIT;
550 lowaddr = BUS_SPACE_MAXADDR_40BIT;
552 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
553 sizeof(uint64_t), 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
554 sizeof(uint64_t), 1, sizeof(uint64_t), 0, NULL, NULL,
555 &ioat->comp_update_tag);
559 error = bus_dmamem_alloc(ioat->comp_update_tag,
560 (void **)&ioat->comp_update, BUS_DMA_ZERO | BUS_DMA_WAITOK,
561 &ioat->comp_update_map);
565 error = bus_dmamap_load(ioat->comp_update_tag, ioat->comp_update_map,
566 ioat->comp_update, sizeof(uint64_t), ioat_comp_update_map, ioat,
571 ioat->ring_size_order = g_ioat_ring_order;
572 num_descriptors = 1 << ioat->ring_size_order;
573 ringsz = sizeof(struct ioat_dma_hw_descriptor) * num_descriptors;
575 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
576 2 * 1024 * 1024, 0x0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
577 ringsz, 1, ringsz, 0, NULL, NULL, &ioat->hw_desc_tag);
581 error = bus_dmamem_alloc(ioat->hw_desc_tag, &hw_desc,
582 BUS_DMA_ZERO | BUS_DMA_WAITOK, &ioat->hw_desc_map);
586 error = bus_dmamap_load(ioat->hw_desc_tag, ioat->hw_desc_map, hw_desc,
587 ringsz, ioat_dmamap_cb, &ioat->hw_desc_bus_addr, BUS_DMA_NOWAIT);
591 ioat->hw_desc_ring = hw_desc;
593 error = bus_dma_tag_create(bus_get_dma_tag(ioat->device),
594 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
595 ioat->max_xfer_size, 1, ioat->max_xfer_size, 0, NULL, NULL,
599 ioat->ring = malloc_domainset(num_descriptors * sizeof(*ring), M_IOAT,
600 DOMAINSET_PREF(ioat->domain), M_ZERO | M_WAITOK);
603 for (i = 0; i < num_descriptors; i++) {
604 memset(&ring[i].bus_dmadesc, 0, sizeof(ring[i].bus_dmadesc));
606 error = bus_dmamap_create(ioat->data_tag, 0,
607 &ring[i].src_dmamap);
610 "%s: bus_dmamap_create failed %d\n", __func__,
614 error = bus_dmamap_create(ioat->data_tag, 0,
615 &ring[i].dst_dmamap);
618 "%s: bus_dmamap_create failed %d\n", __func__,
622 error = bus_dmamap_create(ioat->data_tag, 0,
623 &ring[i].src2_dmamap);
626 "%s: bus_dmamap_create failed %d\n", __func__,
630 error = bus_dmamap_create(ioat->data_tag, 0,
631 &ring[i].dst2_dmamap);
634 "%s: bus_dmamap_create failed %d\n", __func__,
640 for (i = 0; i < num_descriptors; i++) {
641 dma_hw_desc = &ioat->hw_desc_ring[i].dma;
642 dma_hw_desc->next = RING_PHYS_ADDR(ioat, i + 1);
645 ioat->tail = ioat->head = 0;
646 *ioat->comp_update = ioat->last_seen =
647 RING_PHYS_ADDR(ioat, ioat->tail - 1);
652 ioat_map_pci_bar(struct ioat_softc *ioat)
655 ioat->pci_resource_id = PCIR_BAR(0);
656 ioat->pci_resource = bus_alloc_resource_any(ioat->device,
657 SYS_RES_MEMORY, &ioat->pci_resource_id, RF_ACTIVE);
659 if (ioat->pci_resource == NULL) {
660 ioat_log_message(0, "unable to allocate pci resource\n");
664 ioat->pci_bus_tag = rman_get_bustag(ioat->pci_resource);
665 ioat->pci_bus_handle = rman_get_bushandle(ioat->pci_resource);
670 ioat_comp_update_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
672 struct ioat_softc *ioat = arg;
674 KASSERT(error == 0, ("%s: error:%d", __func__, error));
675 ioat->comp_update_bus_addr = seg[0].ds_addr;
679 ioat_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
683 KASSERT(error == 0, ("%s: error:%d", __func__, error));
685 *baddr = segs->ds_addr;
689 * Interrupt setup and handlers
692 ioat_setup_intr(struct ioat_softc *ioat)
694 uint32_t num_vectors;
697 boolean_t force_legacy_interrupts;
700 force_legacy_interrupts = FALSE;
702 if (!g_force_legacy_interrupts && pci_msix_count(ioat->device) >= 1) {
704 pci_alloc_msix(ioat->device, &num_vectors);
705 if (num_vectors == 1)
711 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
712 &ioat->rid, RF_ACTIVE);
715 ioat->res = bus_alloc_resource_any(ioat->device, SYS_RES_IRQ,
716 &ioat->rid, RF_SHAREABLE | RF_ACTIVE);
718 if (ioat->res == NULL) {
719 ioat_log_message(0, "bus_alloc_resource failed\n");
724 error = bus_setup_intr(ioat->device, ioat->res, INTR_MPSAFE |
725 INTR_TYPE_MISC, NULL, ioat_interrupt_handler, ioat, &ioat->tag);
727 ioat_log_message(0, "bus_setup_intr failed\n");
731 ioat_write_intrctrl(ioat, IOAT_INTRCTRL_MASTER_INT_EN);
736 ioat_model_resets_msix(struct ioat_softc *ioat)
740 pciid = pci_get_devid(ioat->device);
759 ioat_interrupt_handler(void *arg)
761 struct ioat_softc *ioat = arg;
763 ioat->stats.interrupts++;
764 ioat_process_events(ioat, TRUE);
768 chanerr_to_errno(uint32_t chanerr)
773 if ((chanerr & (IOAT_CHANERR_XSADDERR | IOAT_CHANERR_XDADDERR)) != 0)
775 if ((chanerr & (IOAT_CHANERR_RDERR | IOAT_CHANERR_WDERR)) != 0)
777 /* This one is probably our fault: */
778 if ((chanerr & IOAT_CHANERR_NDADDERR) != 0)
784 ioat_process_events(struct ioat_softc *ioat, boolean_t intr)
786 struct ioat_descriptor *desc;
787 struct bus_dmadesc *dmadesc;
788 uint64_t comp_update, status;
789 uint32_t completed, chanerr;
793 mtx_lock(&ioat->cleanup_lock);
795 if (!mtx_trylock(&ioat->cleanup_lock))
800 * Don't run while the hardware is being reset. Reset is responsible
801 * for blocking new work and draining & completing existing work, so
802 * there is nothing to do until new work is queued after reset anyway.
804 if (ioat->resetting_cleanup) {
805 mtx_unlock(&ioat->cleanup_lock);
810 comp_update = *ioat->comp_update;
811 status = comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK;
813 if (status < ioat->hw_desc_bus_addr ||
814 status >= ioat->hw_desc_bus_addr + (1 << ioat->ring_size_order) *
815 sizeof(struct ioat_generic_hw_descriptor))
816 panic("Bogus completion address %jx (channel %u)",
817 (uintmax_t)status, ioat->chan_idx);
819 if (status == ioat->last_seen) {
821 * If we landed in process_events and nothing has been
822 * completed, check for a timeout due to channel halt.
826 CTR4(KTR_IOAT, "%s channel=%u hw_status=0x%lx last_seen=0x%lx",
827 __func__, ioat->chan_idx, comp_update, ioat->last_seen);
829 while (RING_PHYS_ADDR(ioat, ioat->tail - 1) != status) {
830 desc = ioat_get_ring_entry(ioat, ioat->tail);
831 dmadesc = &desc->bus_dmadesc;
832 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) ok cb %p(%p)",
833 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
834 dmadesc->callback_arg);
836 bus_dmamap_unload(ioat->data_tag, desc->src_dmamap);
837 bus_dmamap_unload(ioat->data_tag, desc->dst_dmamap);
838 bus_dmamap_unload(ioat->data_tag, desc->src2_dmamap);
839 bus_dmamap_unload(ioat->data_tag, desc->dst2_dmamap);
841 if (dmadesc->callback_fn != NULL)
842 dmadesc->callback_fn(dmadesc->callback_arg, 0);
847 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
848 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
850 if (completed != 0) {
851 ioat->last_seen = RING_PHYS_ADDR(ioat, ioat->tail - 1);
852 ioat->stats.descriptors_processed += completed;
857 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
858 mtx_unlock(&ioat->cleanup_lock);
861 * The device doesn't seem to reliably push suspend/halt statuses to
862 * the channel completion memory address, so poll the device register
863 * here. For performance reasons skip it on interrupts, do it only
864 * on much more rare polling events.
867 comp_update = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
868 if (!is_ioat_halted(comp_update) && !is_ioat_suspended(comp_update))
871 ioat->stats.channel_halts++;
874 * Fatal programming error on this DMA channel. Flush any outstanding
875 * work with error status and restart the engine.
877 mtx_lock(&ioat->submit_lock);
878 ioat->quiescing = TRUE;
879 mtx_unlock(&ioat->submit_lock);
882 * This is safe to do here because the submit queue is quiesced. We
883 * know that we will drain all outstanding events, so ioat_reset_hw
884 * can't deadlock. It is necessary to protect other ioat_process_event
885 * threads from racing ioat_reset_hw, reading an indeterminate hw
886 * state, and attempting to continue issuing completions.
888 mtx_lock(&ioat->cleanup_lock);
889 ioat->resetting_cleanup = TRUE;
891 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
892 if (1 <= g_ioat_debug_level)
893 ioat_halted_debug(ioat, chanerr);
894 ioat->stats.last_halt_chanerr = chanerr;
896 while (ioat_get_active(ioat) > 0) {
897 desc = ioat_get_ring_entry(ioat, ioat->tail);
898 dmadesc = &desc->bus_dmadesc;
899 CTR5(KTR_IOAT, "channel=%u completing desc idx %u (%p) err cb %p(%p)",
900 ioat->chan_idx, ioat->tail, dmadesc, dmadesc->callback_fn,
901 dmadesc->callback_arg);
903 if (dmadesc->callback_fn != NULL)
904 dmadesc->callback_fn(dmadesc->callback_arg,
905 chanerr_to_errno(chanerr));
908 ioat->stats.descriptors_processed++;
909 ioat->stats.descriptors_error++;
911 CTR5(KTR_IOAT, "%s channel=%u head=%u tail=%u active=%u", __func__,
912 ioat->chan_idx, ioat->head, ioat->tail, ioat_get_active(ioat));
914 /* Clear error status */
915 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
917 mtx_unlock(&ioat->cleanup_lock);
919 ioat_log_message(0, "Resetting channel to recover from error\n");
920 error = taskqueue_enqueue(taskqueue_thread, &ioat->reset_task);
922 ("%s: taskqueue_enqueue failed: %d", __func__, error));
926 ioat_reset_hw_task(void *ctx, int pending __unused)
928 struct ioat_softc *ioat;
932 ioat_log_message(1, "%s: Resetting channel\n", __func__);
934 error = ioat_reset_hw(ioat);
935 KASSERT(error == 0, ("%s: reset failed: %d", __func__, error));
943 ioat_get_nchannels(void)
946 return (ioat_channel_index);
950 ioat_get_dmaengine(uint32_t index, int flags)
952 struct ioat_softc *ioat;
954 KASSERT((flags & ~(M_NOWAIT | M_WAITOK)) == 0,
955 ("invalid flags: 0x%08x", flags));
956 KASSERT((flags & (M_NOWAIT | M_WAITOK)) != (M_NOWAIT | M_WAITOK),
957 ("invalid wait | nowait"));
959 mtx_lock(&ioat_list_mtx);
960 if (index >= ioat_channel_index ||
961 (ioat = ioat_channel[index]) == NULL) {
962 mtx_unlock(&ioat_list_mtx);
965 mtx_lock(&ioat->submit_lock);
966 mtx_unlock(&ioat_list_mtx);
968 if (ioat->destroying) {
969 mtx_unlock(&ioat->submit_lock);
974 if (ioat->quiescing) {
975 if ((flags & M_NOWAIT) != 0) {
977 mtx_unlock(&ioat->submit_lock);
981 while (ioat->quiescing && !ioat->destroying)
982 msleep(&ioat->quiescing, &ioat->submit_lock, 0, "getdma", 0);
984 if (ioat->destroying) {
986 mtx_unlock(&ioat->submit_lock);
990 mtx_unlock(&ioat->submit_lock);
991 return (&ioat->dmaengine);
995 ioat_put_dmaengine(bus_dmaengine_t dmaengine)
997 struct ioat_softc *ioat;
999 ioat = to_ioat_softc(dmaengine);
1000 mtx_lock(&ioat->submit_lock);
1002 mtx_unlock(&ioat->submit_lock);
1006 ioat_get_hwversion(bus_dmaengine_t dmaengine)
1008 struct ioat_softc *ioat;
1010 ioat = to_ioat_softc(dmaengine);
1011 return (ioat->version);
1015 ioat_get_max_io_size(bus_dmaengine_t dmaengine)
1017 struct ioat_softc *ioat;
1019 ioat = to_ioat_softc(dmaengine);
1020 return (ioat->max_xfer_size);
1024 ioat_get_capabilities(bus_dmaengine_t dmaengine)
1026 struct ioat_softc *ioat;
1028 ioat = to_ioat_softc(dmaengine);
1029 return (ioat->capabilities);
1033 ioat_get_domain(bus_dmaengine_t dmaengine, int *domain)
1035 struct ioat_softc *ioat;
1037 ioat = to_ioat_softc(dmaengine);
1038 return (bus_get_domain(ioat->device, domain));
1042 ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay)
1044 struct ioat_softc *ioat;
1046 ioat = to_ioat_softc(dmaengine);
1047 if (!ioat->intrdelay_supported)
1049 if (delay > ioat->intrdelay_max)
1052 ioat_write_2(ioat, IOAT_INTRDELAY_OFFSET, delay);
1053 ioat->cached_intrdelay =
1054 ioat_read_2(ioat, IOAT_INTRDELAY_OFFSET) & IOAT_INTRDELAY_US_MASK;
1059 ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine)
1061 struct ioat_softc *ioat;
1063 ioat = to_ioat_softc(dmaengine);
1064 return (ioat->intrdelay_max);
1068 ioat_acquire(bus_dmaengine_t dmaengine)
1070 struct ioat_softc *ioat;
1072 ioat = to_ioat_softc(dmaengine);
1073 mtx_lock(&ioat->submit_lock);
1074 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1075 ioat->acq_head = ioat->head;
1079 ioat_acquire_reserve(bus_dmaengine_t dmaengine, unsigned n, int mflags)
1081 struct ioat_softc *ioat;
1084 ioat = to_ioat_softc(dmaengine);
1085 ioat_acquire(dmaengine);
1087 error = ioat_reserve_space(ioat, n, mflags);
1089 ioat_release(dmaengine);
1094 ioat_release(bus_dmaengine_t dmaengine)
1096 struct ioat_softc *ioat;
1098 ioat = to_ioat_softc(dmaengine);
1099 CTR3(KTR_IOAT, "%s channel=%u dispatch1 head=%u", __func__,
1100 ioat->chan_idx, ioat->head);
1101 KFAIL_POINT_CODE(DEBUG_FP, ioat_release, /* do nothing */);
1102 CTR3(KTR_IOAT, "%s channel=%u dispatch2 head=%u", __func__,
1103 ioat->chan_idx, ioat->head);
1105 if (ioat->acq_head != ioat->head) {
1106 ioat_write_2(ioat, IOAT_DMACOUNT_OFFSET,
1107 (uint16_t)ioat->head);
1109 if (!callout_pending(&ioat->poll_timer)) {
1110 callout_reset_on(&ioat->poll_timer, 1,
1111 ioat_poll_timer_callback, ioat, ioat->cpu);
1114 mtx_unlock(&ioat->submit_lock);
1117 static struct ioat_descriptor *
1118 ioat_op_generic(struct ioat_softc *ioat, uint8_t op,
1119 uint32_t size, uint64_t src, uint64_t dst,
1120 bus_dmaengine_callback_t callback_fn, void *callback_arg,
1123 struct ioat_generic_hw_descriptor *hw_desc;
1124 struct ioat_descriptor *desc;
1125 bus_dma_segment_t seg;
1126 int mflags, nseg, error;
1128 mtx_assert(&ioat->submit_lock, MA_OWNED);
1130 KASSERT((flags & ~_DMA_GENERIC_FLAGS) == 0,
1131 ("Unrecognized flag(s): %#x", flags & ~_DMA_GENERIC_FLAGS));
1132 KASSERT(size <= ioat->max_xfer_size, ("%s: size too big (%u > %u)",
1133 __func__, (unsigned)size, ioat->max_xfer_size));
1135 if ((flags & DMA_NO_WAIT) != 0)
1140 if (ioat_reserve_space(ioat, 1, mflags) != 0)
1143 desc = ioat_get_ring_entry(ioat, ioat->head);
1144 hw_desc = &ioat_get_descriptor(ioat, ioat->head)->generic;
1146 hw_desc->u.control_raw = 0;
1147 hw_desc->u.control_generic.op = op;
1148 hw_desc->u.control_generic.completion_update = 1;
1150 if ((flags & DMA_INT_EN) != 0)
1151 hw_desc->u.control_generic.int_enable = 1;
1152 if ((flags & DMA_FENCE) != 0)
1153 hw_desc->u.control_generic.fence = 1;
1155 hw_desc->size = size;
1159 error = _bus_dmamap_load_phys(ioat->data_tag, desc->src_dmamap,
1160 src, size, 0, &seg, &nseg);
1162 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1163 " failed %d\n", __func__, error);
1166 hw_desc->src_addr = seg.ds_addr;
1171 error = _bus_dmamap_load_phys(ioat->data_tag, desc->dst_dmamap,
1172 dst, size, 0, &seg, &nseg);
1174 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1175 " failed %d\n", __func__, error);
1178 hw_desc->dest_addr = seg.ds_addr;
1181 desc->bus_dmadesc.callback_fn = callback_fn;
1182 desc->bus_dmadesc.callback_arg = callback_arg;
1186 struct bus_dmadesc *
1187 ioat_null(bus_dmaengine_t dmaengine, bus_dmaengine_callback_t callback_fn,
1188 void *callback_arg, uint32_t flags)
1190 struct ioat_dma_hw_descriptor *hw_desc;
1191 struct ioat_descriptor *desc;
1192 struct ioat_softc *ioat;
1194 ioat = to_ioat_softc(dmaengine);
1195 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1197 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 8, 0, 0, callback_fn,
1198 callback_arg, flags);
1202 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1203 hw_desc->u.control.null = 1;
1204 ioat_submit_single(ioat);
1205 return (&desc->bus_dmadesc);
1208 struct bus_dmadesc *
1209 ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
1210 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
1211 void *callback_arg, uint32_t flags)
1213 struct ioat_dma_hw_descriptor *hw_desc;
1214 struct ioat_descriptor *desc;
1215 struct ioat_softc *ioat;
1217 ioat = to_ioat_softc(dmaengine);
1218 desc = ioat_op_generic(ioat, IOAT_OP_COPY, len, src, dst, callback_fn,
1219 callback_arg, flags);
1223 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1224 if (g_ioat_debug_level >= 3)
1225 dump_descriptor(hw_desc);
1227 ioat_submit_single(ioat);
1228 CTR6(KTR_IOAT, "%s channel=%u desc=%p dest=%lx src=%lx len=%lx",
1229 __func__, ioat->chan_idx, &desc->bus_dmadesc, dst, src, len);
1230 return (&desc->bus_dmadesc);
1233 struct bus_dmadesc *
1234 ioat_copy_8k_aligned(bus_dmaengine_t dmaengine, bus_addr_t dst1,
1235 bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
1236 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1238 struct ioat_dma_hw_descriptor *hw_desc;
1239 struct ioat_descriptor *desc;
1240 struct ioat_softc *ioat;
1241 bus_size_t src1_len, dst1_len;
1242 bus_dma_segment_t seg;
1245 ioat = to_ioat_softc(dmaengine);
1246 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1248 KASSERT(((src1 | src2 | dst1 | dst2) & PAGE_MASK) == 0,
1249 ("%s: addresses are not page-aligned", __func__));
1251 desc = ioat_op_generic(ioat, IOAT_OP_COPY, 2 * PAGE_SIZE, 0, 0,
1252 callback_fn, callback_arg, flags);
1256 hw_desc = &ioat_get_descriptor(ioat, desc->id)->dma;
1258 src1_len = (src2 != src1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE;
1260 error = _bus_dmamap_load_phys(ioat->data_tag,
1261 desc->src_dmamap, src1, src1_len, 0, &seg, &nseg);
1263 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1264 " failed %d\n", __func__, error);
1267 hw_desc->src_addr = seg.ds_addr;
1268 if (src1_len != 2 * PAGE_SIZE) {
1269 hw_desc->u.control.src_page_break = 1;
1271 error = _bus_dmamap_load_phys(ioat->data_tag,
1272 desc->src2_dmamap, src2, PAGE_SIZE, 0, &seg, &nseg);
1274 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1275 " failed %d\n", __func__, error);
1278 hw_desc->next_src_addr = seg.ds_addr;
1281 dst1_len = (dst2 != dst1 + PAGE_SIZE) ? PAGE_SIZE : 2 * PAGE_SIZE;
1283 error = _bus_dmamap_load_phys(ioat->data_tag,
1284 desc->dst_dmamap, dst1, dst1_len, 0, &seg, &nseg);
1286 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1287 " failed %d\n", __func__, error);
1290 hw_desc->dest_addr = seg.ds_addr;
1291 if (dst1_len != 2 * PAGE_SIZE) {
1292 hw_desc->u.control.dest_page_break = 1;
1294 error = _bus_dmamap_load_phys(ioat->data_tag,
1295 desc->dst2_dmamap, dst2, PAGE_SIZE, 0, &seg, &nseg);
1297 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1298 " failed %d\n", __func__, error);
1301 hw_desc->next_dest_addr = seg.ds_addr;
1304 if (g_ioat_debug_level >= 3)
1305 dump_descriptor(hw_desc);
1307 ioat_submit_single(ioat);
1308 return (&desc->bus_dmadesc);
1311 struct bus_dmadesc *
1312 ioat_copy_crc(bus_dmaengine_t dmaengine, bus_addr_t dst, bus_addr_t src,
1313 bus_size_t len, uint32_t *initialseed, bus_addr_t crcptr,
1314 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1316 struct ioat_crc32_hw_descriptor *hw_desc;
1317 struct ioat_descriptor *desc;
1318 struct ioat_softc *ioat;
1321 bus_dma_segment_t seg;
1324 ioat = to_ioat_softc(dmaengine);
1325 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1327 KASSERT((ioat->capabilities & IOAT_DMACAP_MOVECRC) != 0,
1328 ("%s: device lacks MOVECRC capability", __func__));
1329 teststore = (flags & _DMA_CRC_TESTSTORE);
1330 KASSERT(teststore != _DMA_CRC_TESTSTORE,
1331 ("%s: TEST and STORE invalid", __func__));
1332 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0,
1333 ("%s: INLINE invalid without TEST or STORE", __func__));
1335 switch (teststore) {
1337 op = IOAT_OP_MOVECRC_STORE;
1340 op = IOAT_OP_MOVECRC_TEST;
1343 KASSERT(teststore == 0, ("bogus"));
1344 op = IOAT_OP_MOVECRC;
1348 desc = ioat_op_generic(ioat, op, len, src, dst, callback_fn,
1349 callback_arg, flags & ~_DMA_CRC_FLAGS);
1353 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1355 if ((flags & DMA_CRC_INLINE) == 0) {
1357 error = _bus_dmamap_load_phys(ioat->data_tag,
1358 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
1361 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1362 " failed %d\n", __func__, error);
1365 hw_desc->crc_address = seg.ds_addr;
1367 hw_desc->u.control.crc_location = 1;
1369 if (initialseed != NULL) {
1370 hw_desc->u.control.use_seed = 1;
1371 hw_desc->seed = *initialseed;
1374 if (g_ioat_debug_level >= 3)
1375 dump_descriptor(hw_desc);
1377 ioat_submit_single(ioat);
1378 return (&desc->bus_dmadesc);
1381 struct bus_dmadesc *
1382 ioat_crc(bus_dmaengine_t dmaengine, bus_addr_t src, bus_size_t len,
1383 uint32_t *initialseed, bus_addr_t crcptr,
1384 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags)
1386 struct ioat_crc32_hw_descriptor *hw_desc;
1387 struct ioat_descriptor *desc;
1388 struct ioat_softc *ioat;
1391 bus_dma_segment_t seg;
1394 ioat = to_ioat_softc(dmaengine);
1395 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1397 KASSERT((ioat->capabilities & IOAT_DMACAP_CRC) != 0,
1398 ("%s: device lacks CRC capability", __func__));
1399 teststore = (flags & _DMA_CRC_TESTSTORE);
1400 KASSERT(teststore != _DMA_CRC_TESTSTORE,
1401 ("%s: TEST and STORE invalid", __func__));
1402 KASSERT(teststore != 0 || (flags & DMA_CRC_INLINE) == 0,
1403 ("%s: INLINE invalid without TEST or STORE", __func__));
1405 switch (teststore) {
1407 op = IOAT_OP_CRC_STORE;
1410 op = IOAT_OP_CRC_TEST;
1413 KASSERT(teststore == 0, ("bogus"));
1418 desc = ioat_op_generic(ioat, op, len, src, 0, callback_fn,
1419 callback_arg, flags & ~_DMA_CRC_FLAGS);
1423 hw_desc = &ioat_get_descriptor(ioat, desc->id)->crc32;
1425 if ((flags & DMA_CRC_INLINE) == 0) {
1427 error = _bus_dmamap_load_phys(ioat->data_tag,
1428 desc->dst2_dmamap, crcptr, sizeof(uint32_t), 0,
1431 ioat_log_message(0, "%s: _bus_dmamap_load_phys"
1432 " failed %d\n", __func__, error);
1435 hw_desc->crc_address = seg.ds_addr;
1437 hw_desc->u.control.crc_location = 1;
1439 if (initialseed != NULL) {
1440 hw_desc->u.control.use_seed = 1;
1441 hw_desc->seed = *initialseed;
1444 if (g_ioat_debug_level >= 3)
1445 dump_descriptor(hw_desc);
1447 ioat_submit_single(ioat);
1448 return (&desc->bus_dmadesc);
1451 struct bus_dmadesc *
1452 ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst, uint64_t fillpattern,
1453 bus_size_t len, bus_dmaengine_callback_t callback_fn, void *callback_arg,
1456 struct ioat_fill_hw_descriptor *hw_desc;
1457 struct ioat_descriptor *desc;
1458 struct ioat_softc *ioat;
1460 ioat = to_ioat_softc(dmaengine);
1461 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1463 KASSERT((ioat->capabilities & IOAT_DMACAP_BFILL) != 0,
1464 ("%s: device lacks BFILL capability", __func__));
1466 desc = ioat_op_generic(ioat, IOAT_OP_FILL, len, 0, dst,
1467 callback_fn, callback_arg, flags);
1471 hw_desc = &ioat_get_descriptor(ioat, desc->id)->fill;
1472 hw_desc->src_data = fillpattern;
1473 if (g_ioat_debug_level >= 3)
1474 dump_descriptor(hw_desc);
1476 ioat_submit_single(ioat);
1477 return (&desc->bus_dmadesc);
1483 static inline uint32_t
1484 ioat_get_active(struct ioat_softc *ioat)
1487 return ((ioat->head - ioat->tail) & ((1 << ioat->ring_size_order) - 1));
1490 static inline uint32_t
1491 ioat_get_ring_space(struct ioat_softc *ioat)
1494 return ((1 << ioat->ring_size_order) - ioat_get_active(ioat) - 1);
1498 * Reserves space in this IOAT descriptor ring by ensuring enough slots remain
1501 * If mflags contains M_WAITOK, blocks until enough space is available.
1503 * Returns zero on success, or an errno on error. If num_descs is beyond the
1504 * maximum ring size, returns EINVAl; if allocation would block and mflags
1505 * contains M_NOWAIT, returns EAGAIN.
1507 * Must be called with the submit_lock held; returns with the lock held. The
1508 * lock may be dropped to allocate the ring.
1510 * (The submit_lock is needed to add any entries to the ring, so callers are
1511 * assured enough room is available.)
1514 ioat_reserve_space(struct ioat_softc *ioat, uint32_t num_descs, int mflags)
1519 mtx_assert(&ioat->submit_lock, MA_OWNED);
1523 if (num_descs < 1 || num_descs >= (1 << ioat->ring_size_order)) {
1529 if (ioat->quiescing) {
1534 if (ioat_get_ring_space(ioat) >= num_descs)
1537 CTR3(KTR_IOAT, "%s channel=%u starved (%u)", __func__,
1538 ioat->chan_idx, num_descs);
1540 if (!dug && !ioat->is_submitter_processing) {
1541 ioat->is_submitter_processing = TRUE;
1542 mtx_unlock(&ioat->submit_lock);
1544 CTR2(KTR_IOAT, "%s channel=%u attempting to process events",
1545 __func__, ioat->chan_idx);
1546 ioat_process_events(ioat, FALSE);
1548 mtx_lock(&ioat->submit_lock);
1550 KASSERT(ioat->is_submitter_processing == TRUE,
1551 ("is_submitter_processing"));
1552 ioat->is_submitter_processing = FALSE;
1553 wakeup(&ioat->tail);
1557 if ((mflags & M_WAITOK) == 0) {
1561 CTR2(KTR_IOAT, "%s channel=%u blocking on completions",
1562 __func__, ioat->chan_idx);
1563 msleep(&ioat->tail, &ioat->submit_lock, 0,
1569 mtx_assert(&ioat->submit_lock, MA_OWNED);
1570 KASSERT(!ioat->quiescing || error == ENXIO,
1571 ("reserved during quiesce"));
1576 ioat_free_ring(struct ioat_softc *ioat, uint32_t size,
1577 struct ioat_descriptor *ring)
1580 free_domain(ring, M_IOAT);
1583 static struct ioat_descriptor *
1584 ioat_get_ring_entry(struct ioat_softc *ioat, uint32_t index)
1587 return (&ioat->ring[index % (1 << ioat->ring_size_order)]);
1590 static union ioat_hw_descriptor *
1591 ioat_get_descriptor(struct ioat_softc *ioat, uint32_t index)
1594 return (&ioat->hw_desc_ring[index % (1 << ioat->ring_size_order)]);
1598 ioat_halted_debug(struct ioat_softc *ioat, uint32_t chanerr)
1600 union ioat_hw_descriptor *desc;
1602 ioat_log_message(0, "Channel halted (%b)\n", (int)chanerr,
1607 mtx_assert(&ioat->cleanup_lock, MA_OWNED);
1609 desc = ioat_get_descriptor(ioat, ioat->tail + 0);
1610 dump_descriptor(desc);
1612 desc = ioat_get_descriptor(ioat, ioat->tail + 1);
1613 dump_descriptor(desc);
1617 ioat_poll_timer_callback(void *arg)
1619 struct ioat_softc *ioat;
1622 CTR1(KTR_IOAT, "%s", __func__);
1624 ioat_process_events(ioat, FALSE);
1626 mtx_lock(&ioat->submit_lock);
1627 if (ioat_get_active(ioat) > 0)
1628 callout_schedule(&ioat->poll_timer, 1);
1629 mtx_unlock(&ioat->submit_lock);
1636 ioat_submit_single(struct ioat_softc *ioat)
1639 mtx_assert(&ioat->submit_lock, MA_OWNED);
1642 CTR4(KTR_IOAT, "%s channel=%u head=%u tail=%u", __func__,
1643 ioat->chan_idx, ioat->head, ioat->tail);
1645 ioat->stats.descriptors_submitted++;
1649 ioat_reset_hw(struct ioat_softc *ioat)
1656 CTR2(KTR_IOAT, "%s channel=%u", __func__, ioat->chan_idx);
1658 mtx_lock(&ioat->submit_lock);
1659 while (ioat->resetting && !ioat->destroying)
1660 msleep(&ioat->resetting, &ioat->submit_lock, 0, "IRH_drain", 0);
1661 if (ioat->destroying) {
1662 mtx_unlock(&ioat->submit_lock);
1665 ioat->resetting = TRUE;
1666 ioat->quiescing = TRUE;
1667 mtx_unlock(&ioat->submit_lock);
1668 mtx_lock(&ioat->cleanup_lock);
1669 while (ioat_get_active(ioat) > 0)
1670 msleep(&ioat->tail, &ioat->cleanup_lock, 0, "ioat_drain", 1);
1673 * Suspend ioat_process_events while the hardware and softc are in an
1674 * indeterminate state.
1676 ioat->resetting_cleanup = TRUE;
1677 mtx_unlock(&ioat->cleanup_lock);
1679 CTR2(KTR_IOAT, "%s channel=%u quiesced and drained", __func__,
1682 status = ioat_get_chansts(ioat);
1683 if (is_ioat_active(status) || is_ioat_idle(status))
1686 /* Wait at most 20 ms */
1687 for (timeout = 0; (is_ioat_active(status) || is_ioat_idle(status)) &&
1688 timeout < 20; timeout++) {
1690 status = ioat_get_chansts(ioat);
1692 if (timeout == 20) {
1697 KASSERT(ioat_get_active(ioat) == 0, ("active after quiesce"));
1699 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1700 ioat_write_4(ioat, IOAT_CHANERR_OFFSET, chanerr);
1702 CTR2(KTR_IOAT, "%s channel=%u hardware suspended", __func__,
1706 * IOAT v3 workaround - CHANERRMSK_INT with 3E07h to masks out errors
1707 * that can cause stability issues for IOAT v3.
1709 pci_write_config(ioat->device, IOAT_CFG_CHANERRMASK_INT_OFFSET, 0x3e07,
1711 chanerr = pci_read_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, 4);
1712 pci_write_config(ioat->device, IOAT_CFG_CHANERR_INT_OFFSET, chanerr, 4);
1715 * BDXDE and BWD models reset MSI-X registers on device reset.
1716 * Save/restore their contents manually.
1718 if (ioat_model_resets_msix(ioat)) {
1719 ioat_log_message(1, "device resets MSI-X registers; saving\n");
1720 pci_save_state(ioat->device);
1724 CTR2(KTR_IOAT, "%s channel=%u hardware reset", __func__,
1727 /* Wait at most 20 ms */
1728 for (timeout = 0; ioat_reset_pending(ioat) && timeout < 20; timeout++)
1730 if (timeout == 20) {
1735 if (ioat_model_resets_msix(ioat)) {
1736 ioat_log_message(1, "device resets registers; restored\n");
1737 pci_restore_state(ioat->device);
1740 /* Reset attempts to return the hardware to "halted." */
1741 status = ioat_get_chansts(ioat);
1742 if (is_ioat_active(status) || is_ioat_idle(status)) {
1743 /* So this really shouldn't happen... */
1744 ioat_log_message(0, "Device is active after a reset?\n");
1745 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1750 chanerr = ioat_read_4(ioat, IOAT_CHANERR_OFFSET);
1752 mtx_lock(&ioat->cleanup_lock);
1753 ioat_halted_debug(ioat, chanerr);
1754 mtx_unlock(&ioat->cleanup_lock);
1760 * Bring device back online after reset. Writing CHAINADDR brings the
1761 * device back to active.
1763 * The internal ring counter resets to zero, so we have to start over
1766 ioat->tail = ioat->head = 0;
1767 *ioat->comp_update = ioat->last_seen =
1768 RING_PHYS_ADDR(ioat, ioat->tail - 1);
1770 ioat_write_chanctrl(ioat, IOAT_CHANCTRL_RUN);
1771 ioat_write_chancmp(ioat, ioat->comp_update_bus_addr);
1772 ioat_write_chainaddr(ioat, RING_PHYS_ADDR(ioat, 0));
1774 CTR2(KTR_IOAT, "%s channel=%u configured channel", __func__,
1778 /* Enqueues a null operation and ensures it completes. */
1780 error = ioat_start_channel(ioat);
1781 CTR2(KTR_IOAT, "%s channel=%u started channel", __func__,
1786 * Resume completions now that ring state is consistent.
1788 mtx_lock(&ioat->cleanup_lock);
1789 ioat->resetting_cleanup = FALSE;
1790 mtx_unlock(&ioat->cleanup_lock);
1792 /* Unblock submission of new work */
1793 mtx_lock(&ioat->submit_lock);
1794 ioat->quiescing = FALSE;
1795 wakeup(&ioat->quiescing);
1797 ioat->resetting = FALSE;
1798 wakeup(&ioat->resetting);
1800 CTR2(KTR_IOAT, "%s channel=%u reset done", __func__, ioat->chan_idx);
1801 mtx_unlock(&ioat->submit_lock);
1807 sysctl_handle_chansts(SYSCTL_HANDLER_ARGS)
1809 struct ioat_softc *ioat;
1816 status = ioat_get_chansts(ioat) & IOAT_CHANSTS_STATUS;
1818 sbuf_new_for_sysctl(&sb, NULL, 256, req);
1820 case IOAT_CHANSTS_ACTIVE:
1821 sbuf_printf(&sb, "ACTIVE");
1823 case IOAT_CHANSTS_IDLE:
1824 sbuf_printf(&sb, "IDLE");
1826 case IOAT_CHANSTS_SUSPENDED:
1827 sbuf_printf(&sb, "SUSPENDED");
1829 case IOAT_CHANSTS_HALTED:
1830 sbuf_printf(&sb, "HALTED");
1832 case IOAT_CHANSTS_ARMED:
1833 sbuf_printf(&sb, "ARMED");
1836 sbuf_printf(&sb, "UNKNOWN");
1839 error = sbuf_finish(&sb);
1842 if (error != 0 || req->newptr == NULL)
1848 sysctl_handle_dpi(SYSCTL_HANDLER_ARGS)
1850 struct ioat_softc *ioat;
1852 #define PRECISION "1"
1853 const uintmax_t factor = 10;
1858 sbuf_new_for_sysctl(&sb, NULL, 16, req);
1860 if (ioat->stats.interrupts == 0) {
1861 sbuf_printf(&sb, "NaN");
1864 rate = ioat->stats.descriptors_processed * factor /
1865 ioat->stats.interrupts;
1866 sbuf_printf(&sb, "%ju.%." PRECISION "ju", rate / factor,
1870 error = sbuf_finish(&sb);
1872 if (error != 0 || req->newptr == NULL)
1878 sysctl_handle_reset(SYSCTL_HANDLER_ARGS)
1880 struct ioat_softc *ioat;
1886 error = SYSCTL_OUT(req, &arg, sizeof(arg));
1887 if (error != 0 || req->newptr == NULL)
1890 error = SYSCTL_IN(req, &arg, sizeof(arg));
1895 error = ioat_reset_hw(ioat);
1901 dump_descriptor(void *hw_desc)
1905 for (i = 0; i < 2; i++) {
1906 for (j = 0; j < 8; j++)
1907 printf("%08x ", ((uint32_t *)hw_desc)[i * 8 + j]);
1913 ioat_setup_sysctl(device_t device)
1915 struct sysctl_oid_list *par, *statpar, *state, *hammer;
1916 struct sysctl_ctx_list *ctx;
1917 struct sysctl_oid *tree, *tmp;
1918 struct ioat_softc *ioat;
1920 ioat = DEVICE2SOFTC(device);
1921 ctx = device_get_sysctl_ctx(device);
1922 tree = device_get_sysctl_tree(device);
1923 par = SYSCTL_CHILDREN(tree);
1925 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "version", CTLFLAG_RD,
1926 &ioat->version, 0, "HW version (0xMM form)");
1927 SYSCTL_ADD_UINT(ctx, par, OID_AUTO, "max_xfer_size", CTLFLAG_RD,
1928 &ioat->max_xfer_size, 0, "HW maximum transfer size");
1929 SYSCTL_ADD_INT(ctx, par, OID_AUTO, "intrdelay_supported", CTLFLAG_RD,
1930 &ioat->intrdelay_supported, 0, "Is INTRDELAY supported");
1931 SYSCTL_ADD_U16(ctx, par, OID_AUTO, "intrdelay_max", CTLFLAG_RD,
1932 &ioat->intrdelay_max, 0,
1933 "Maximum configurable INTRDELAY on this channel (microseconds)");
1935 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "state", CTLFLAG_RD, NULL,
1936 "IOAT channel internal state");
1937 state = SYSCTL_CHILDREN(tmp);
1939 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "ring_size_order", CTLFLAG_RD,
1940 &ioat->ring_size_order, 0, "SW descriptor ring size order");
1941 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "head", CTLFLAG_RD, &ioat->head,
1942 0, "SW descriptor head pointer index");
1943 SYSCTL_ADD_UINT(ctx, state, OID_AUTO, "tail", CTLFLAG_RD, &ioat->tail,
1944 0, "SW descriptor tail pointer index");
1946 SYSCTL_ADD_UQUAD(ctx, state, OID_AUTO, "last_completion", CTLFLAG_RD,
1947 ioat->comp_update, "HW addr of last completion");
1949 SYSCTL_ADD_INT(ctx, state, OID_AUTO, "is_submitter_processing",
1950 CTLFLAG_RD, &ioat->is_submitter_processing, 0,
1951 "submitter processing");
1953 SYSCTL_ADD_PROC(ctx, state, OID_AUTO, "chansts",
1954 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_chansts, "A",
1955 "String of the channel status");
1957 SYSCTL_ADD_U16(ctx, state, OID_AUTO, "intrdelay", CTLFLAG_RD,
1958 &ioat->cached_intrdelay, 0,
1959 "Current INTRDELAY on this channel (cached, microseconds)");
1961 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "hammer", CTLFLAG_RD, NULL,
1962 "Big hammers (mostly for testing)");
1963 hammer = SYSCTL_CHILDREN(tmp);
1965 SYSCTL_ADD_PROC(ctx, hammer, OID_AUTO, "force_hw_reset",
1966 CTLTYPE_INT | CTLFLAG_RW, ioat, 0, sysctl_handle_reset, "I",
1967 "Set to non-zero to reset the hardware");
1969 tmp = SYSCTL_ADD_NODE(ctx, par, OID_AUTO, "stats", CTLFLAG_RD, NULL,
1970 "IOAT channel statistics");
1971 statpar = SYSCTL_CHILDREN(tmp);
1973 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "interrupts",
1974 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.interrupts,
1975 "Number of interrupts processed on this channel");
1976 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "descriptors",
1977 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_processed,
1978 "Number of descriptors processed on this channel");
1979 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "submitted",
1980 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_submitted,
1981 "Number of descriptors submitted to this channel");
1982 SYSCTL_ADD_UQUAD(ctx, statpar, OID_AUTO, "errored",
1983 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.descriptors_error,
1984 "Number of descriptors failed by channel errors");
1985 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "halts",
1986 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.channel_halts, 0,
1987 "Number of times the channel has halted");
1988 SYSCTL_ADD_U32(ctx, statpar, OID_AUTO, "last_halt_chanerr",
1989 CTLFLAG_RW | CTLFLAG_STATS, &ioat->stats.last_halt_chanerr, 0,
1990 "The raw CHANERR when the channel was last halted");
1992 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "desc_per_interrupt",
1993 CTLTYPE_STRING | CTLFLAG_RD, ioat, 0, sysctl_handle_dpi, "A",
1994 "Descriptors per interrupt");
1998 ioat_get(struct ioat_softc *ioat)
2001 mtx_assert(&ioat->submit_lock, MA_OWNED);
2002 KASSERT(ioat->refcnt < UINT32_MAX, ("refcnt overflow"));
2008 ioat_put(struct ioat_softc *ioat)
2011 mtx_assert(&ioat->submit_lock, MA_OWNED);
2012 KASSERT(ioat->refcnt >= 1, ("refcnt error"));
2014 if (--ioat->refcnt == 0)
2015 wakeup(&ioat->refcnt);
2019 ioat_drain_locked(struct ioat_softc *ioat)
2022 mtx_assert(&ioat->submit_lock, MA_OWNED);
2024 while (ioat->refcnt > 0)
2025 msleep(&ioat->refcnt, &ioat->submit_lock, 0, "ioat_drain", 0);
2029 #define _db_show_lock(lo) LOCK_CLASS(lo)->lc_ddb_show(lo)
2030 #define db_show_lock(lk) _db_show_lock(&(lk)->lock_object)
2031 DB_SHOW_COMMAND(ioat, db_show_ioat)
2033 struct ioat_softc *sc;
2038 idx = (unsigned)addr;
2039 if (idx >= ioat_channel_index)
2042 sc = ioat_channel[idx];
2043 db_printf("ioat softc at %p\n", sc);
2047 db_printf(" version: %d\n", sc->version);
2048 db_printf(" chan_idx: %u\n", sc->chan_idx);
2049 db_printf(" submit_lock: ");
2050 db_show_lock(&sc->submit_lock);
2052 db_printf(" capabilities: %b\n", (int)sc->capabilities,
2054 db_printf(" cached_intrdelay: %u\n", sc->cached_intrdelay);
2055 db_printf(" *comp_update: 0x%jx\n", (uintmax_t)*sc->comp_update);
2057 db_printf(" poll_timer:\n");
2058 db_printf(" c_time: %ju\n", (uintmax_t)sc->poll_timer.c_time);
2059 db_printf(" c_arg: %p\n", sc->poll_timer.c_arg);
2060 db_printf(" c_func: %p\n", sc->poll_timer.c_func);
2061 db_printf(" c_lock: %p\n", sc->poll_timer.c_lock);
2062 db_printf(" c_flags: 0x%x\n", (unsigned)sc->poll_timer.c_flags);
2064 db_printf(" quiescing: %d\n", (int)sc->quiescing);
2065 db_printf(" destroying: %d\n", (int)sc->destroying);
2066 db_printf(" is_submitter_processing: %d\n",
2067 (int)sc->is_submitter_processing);
2068 db_printf(" intrdelay_supported: %d\n", (int)sc->intrdelay_supported);
2069 db_printf(" resetting: %d\n", (int)sc->resetting);
2071 db_printf(" head: %u\n", sc->head);
2072 db_printf(" tail: %u\n", sc->tail);
2073 db_printf(" ring_size_order: %u\n", sc->ring_size_order);
2074 db_printf(" last_seen: 0x%lx\n", sc->last_seen);
2075 db_printf(" ring: %p\n", sc->ring);
2076 db_printf(" descriptors: %p\n", sc->hw_desc_ring);
2077 db_printf(" descriptors (phys): 0x%jx\n",
2078 (uintmax_t)sc->hw_desc_bus_addr);
2080 db_printf(" ring[%u] (tail):\n", sc->tail %
2081 (1 << sc->ring_size_order));
2082 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->tail)->id);
2083 db_printf(" addr: 0x%lx\n",
2084 RING_PHYS_ADDR(sc, sc->tail));
2085 db_printf(" next: 0x%lx\n",
2086 ioat_get_descriptor(sc, sc->tail)->generic.next);
2088 db_printf(" ring[%u] (head - 1):\n", (sc->head - 1) %
2089 (1 << sc->ring_size_order));
2090 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head - 1)->id);
2091 db_printf(" addr: 0x%lx\n",
2092 RING_PHYS_ADDR(sc, sc->head - 1));
2093 db_printf(" next: 0x%lx\n",
2094 ioat_get_descriptor(sc, sc->head - 1)->generic.next);
2096 db_printf(" ring[%u] (head):\n", (sc->head) %
2097 (1 << sc->ring_size_order));
2098 db_printf(" id: %u\n", ioat_get_ring_entry(sc, sc->head)->id);
2099 db_printf(" addr: 0x%lx\n",
2100 RING_PHYS_ADDR(sc, sc->head));
2101 db_printf(" next: 0x%lx\n",
2102 ioat_get_descriptor(sc, sc->head)->generic.next);
2104 for (idx = 0; idx < (1 << sc->ring_size_order); idx++)
2105 if ((*sc->comp_update & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK)
2106 == RING_PHYS_ADDR(sc, idx))
2107 db_printf(" ring[%u] == hardware tail\n", idx);
2109 db_printf(" cleanup_lock: ");
2110 db_show_lock(&sc->cleanup_lock);
2112 db_printf(" refcnt: %u\n", sc->refcnt);
2113 db_printf(" stats:\n");
2114 db_printf(" interrupts: %lu\n", sc->stats.interrupts);
2115 db_printf(" descriptors_processed: %lu\n", sc->stats.descriptors_processed);
2116 db_printf(" descriptors_error: %lu\n", sc->stats.descriptors_error);
2117 db_printf(" descriptors_submitted: %lu\n", sc->stats.descriptors_submitted);
2119 db_printf(" channel_halts: %u\n", sc->stats.channel_halts);
2120 db_printf(" last_halt_chanerr: %u\n", sc->stats.last_halt_chanerr);
2125 db_printf(" hw status:\n");
2126 db_printf(" status: 0x%lx\n", ioat_get_chansts(sc));
2127 db_printf(" chanctrl: 0x%x\n",
2128 (unsigned)ioat_read_2(sc, IOAT_CHANCTRL_OFFSET));
2129 db_printf(" chancmd: 0x%x\n",
2130 (unsigned)ioat_read_1(sc, IOAT_CHANCMD_OFFSET));
2131 db_printf(" dmacount: 0x%x\n",
2132 (unsigned)ioat_read_2(sc, IOAT_DMACOUNT_OFFSET));
2133 db_printf(" chainaddr: 0x%lx\n",
2134 ioat_read_double_4(sc, IOAT_CHAINADDR_OFFSET_LOW));
2135 db_printf(" chancmp: 0x%lx\n",
2136 ioat_read_double_4(sc, IOAT_CHANCMP_OFFSET_LOW));
2137 db_printf(" chanerr: %b\n",
2138 (int)ioat_read_4(sc, IOAT_CHANERR_OFFSET), IOAT_CHANERR_STR);
2141 db_printf("usage: show ioat <0-%u>\n", ioat_channel_index);