2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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27 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <machine/bus.h>
36 * This file defines the public interface to the IOAT driver.
40 * Enables an interrupt for this operation. Typically, you would only enable
41 * this on the last operation in a group
43 #define DMA_INT_EN 0x1
45 * Like M_NOWAIT. Operations will return NULL if they cannot allocate a
46 * descriptor without blocking.
48 #define DMA_NO_WAIT 0x2
49 #define DMA_ALL_FLAGS (DMA_INT_EN | DMA_NO_WAIT)
52 * Hardware revision number. Different hardware revisions support different
53 * features. For example, 3.2 cannot read from MMIO space, while 3.3 can.
55 #define IOAT_VER_3_0 0x30
56 #define IOAT_VER_3_2 0x32
57 #define IOAT_VER_3_3 0x33
59 typedef void *bus_dmaengine_t;
61 typedef void (*bus_dmaengine_callback_t)(void *arg, int error);
64 * Called first to acquire a reference to the DMA channel
66 bus_dmaengine_t ioat_get_dmaengine(uint32_t channel_index);
68 /* Release the DMA channel */
69 void ioat_put_dmaengine(bus_dmaengine_t dmaengine);
71 /* Check the DMA engine's HW version */
72 int ioat_get_hwversion(bus_dmaengine_t dmaengine);
75 * Set interrupt coalescing on a DMA channel.
77 * The argument is in microseconds. A zero value disables coalescing. Any
78 * other value delays interrupt generation for N microseconds to provide
79 * opportunity to coalesce multiple operations into a single interrupt.
81 * Returns an error status, or zero on success.
83 * - ERANGE if the given value exceeds the delay supported by the hardware.
84 * (All current hardware supports a maximum of 0x3fff microseconds delay.)
85 * - ENODEV if the hardware does not support interrupt coalescing.
87 int ioat_set_interrupt_coalesce(bus_dmaengine_t dmaengine, uint16_t delay);
90 * Return the maximum supported coalescing period, for use in
91 * ioat_set_interrupt_coalesce(). If the hardware does not support coalescing,
94 uint16_t ioat_get_max_coalesce_period(bus_dmaengine_t dmaengine);
97 * Acquire must be called before issuing an operation to perform. Release is
98 * called after. Multiple operations can be issued within the context of one
101 void ioat_acquire(bus_dmaengine_t dmaengine);
102 void ioat_release(bus_dmaengine_t dmaengine);
105 * Issue a blockfill operation. The 64-bit pattern 'fillpattern' is written to
106 * 'len' physically contiguous bytes at 'dst'.
108 * Only supported on devices with the BFILL capability.
110 struct bus_dmadesc *ioat_blockfill(bus_dmaengine_t dmaengine, bus_addr_t dst,
111 uint64_t fillpattern, bus_size_t len, bus_dmaengine_callback_t callback_fn,
112 void *callback_arg, uint32_t flags);
114 /* Issues the copy data operation */
115 struct bus_dmadesc *ioat_copy(bus_dmaengine_t dmaengine, bus_addr_t dst,
116 bus_addr_t src, bus_size_t len, bus_dmaengine_callback_t callback_fn,
117 void *callback_arg, uint32_t flags);
120 * Issue a copy data operation, with constraints:
121 * - src1, src2, dst1, dst2 are all page-aligned addresses
122 * - The quantity to copy is exactly 2 pages;
123 * - src1 -> dst1, src2 -> dst2
125 * Why use this instead of normal _copy()? You can copy two non-contiguous
126 * pages (src, dst, or both) with one descriptor.
128 struct bus_dmadesc *ioat_copy_8k_aligned(bus_dmaengine_t dmaengine,
129 bus_addr_t dst1, bus_addr_t dst2, bus_addr_t src1, bus_addr_t src2,
130 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
133 * Issues a null operation. This issues the operation to the hardware, but the
134 * hardware doesn't do anything with it.
136 struct bus_dmadesc *ioat_null(bus_dmaengine_t dmaengine,
137 bus_dmaengine_callback_t callback_fn, void *callback_arg, uint32_t flags);
140 #endif /* __IOAT_H__ */