2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 __FBSDID("$FreeBSD$");
29 #ifndef __IOAT_INTERNAL_H__
30 #define __IOAT_INTERNAL_H__
32 #define DEVICE2SOFTC(dev) ((struct ioat_softc *) device_get_softc(dev))
33 #define KTR_IOAT KTR_SPARE3
35 #define ioat_read_chancnt(ioat) \
36 ioat_read_1((ioat), IOAT_CHANCNT_OFFSET)
38 #define ioat_read_xfercap(ioat) \
39 (ioat_read_1((ioat), IOAT_XFERCAP_OFFSET) & IOAT_XFERCAP_VALID_MASK)
41 #define ioat_write_intrctrl(ioat, value) \
42 ioat_write_1((ioat), IOAT_INTRCTRL_OFFSET, (value))
44 #define ioat_read_cbver(ioat) \
45 (ioat_read_1((ioat), IOAT_CBVER_OFFSET) & 0xFF)
47 #define ioat_read_dmacapability(ioat) \
48 ioat_read_4((ioat), IOAT_DMACAPABILITY_OFFSET)
50 #define ioat_write_chanctrl(ioat, value) \
51 ioat_write_2((ioat), IOAT_CHANCTRL_OFFSET, (value))
53 static __inline uint64_t
54 ioat_bus_space_read_8_lower_first(bus_space_tag_t tag,
55 bus_space_handle_t handle, bus_size_t offset)
57 return (bus_space_read_4(tag, handle, offset) |
58 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32);
62 ioat_bus_space_write_8_lower_first(bus_space_tag_t tag,
63 bus_space_handle_t handle, bus_size_t offset, uint64_t val)
65 bus_space_write_4(tag, handle, offset, val);
66 bus_space_write_4(tag, handle, offset + 4, val >> 32);
70 #define ioat_bus_space_read_8 ioat_bus_space_read_8_lower_first
71 #define ioat_bus_space_write_8 ioat_bus_space_write_8_lower_first
73 #define ioat_bus_space_read_8(tag, handle, offset) \
74 bus_space_read_8((tag), (handle), (offset))
75 #define ioat_bus_space_write_8(tag, handle, offset, val) \
76 bus_space_write_8((tag), (handle), (offset), (val))
79 #define ioat_read_1(ioat, offset) \
80 bus_space_read_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
83 #define ioat_read_2(ioat, offset) \
84 bus_space_read_2((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
87 #define ioat_read_4(ioat, offset) \
88 bus_space_read_4((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
91 #define ioat_read_8(ioat, offset) \
92 ioat_bus_space_read_8((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
95 #define ioat_read_double_4(ioat, offset) \
96 ioat_bus_space_read_8_lower_first((ioat)->pci_bus_tag, \
97 (ioat)->pci_bus_handle, (offset))
99 #define ioat_write_1(ioat, offset, value) \
100 bus_space_write_1((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
103 #define ioat_write_2(ioat, offset, value) \
104 bus_space_write_2((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
107 #define ioat_write_4(ioat, offset, value) \
108 bus_space_write_4((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
111 #define ioat_write_8(ioat, offset, value) \
112 ioat_bus_space_write_8((ioat)->pci_bus_tag, (ioat)->pci_bus_handle, \
115 #define ioat_write_double_4(ioat, offset, value) \
116 ioat_bus_space_write_8_lower_first((ioat)->pci_bus_tag, \
117 (ioat)->pci_bus_handle, (offset), (value))
119 MALLOC_DECLARE(M_IOAT);
121 SYSCTL_DECL(_hw_ioat);
123 extern int g_ioat_debug_level;
125 struct generic_dma_control {
126 uint32_t int_enable:1;
127 uint32_t src_snoop_disable:1;
128 uint32_t dest_snoop_disable:1;
129 uint32_t completion_update:1;
131 uint32_t reserved1:1;
132 uint32_t src_page_break:1;
133 uint32_t dest_page_break:1;
137 uint32_t reserved2:13;
141 struct ioat_generic_hw_descriptor {
144 uint32_t control_raw;
145 struct generic_dma_control control_generic;
150 uint64_t reserved[4];
153 struct ioat_dma_hw_descriptor {
156 uint32_t control_raw;
157 struct generic_dma_control control_generic;
159 uint32_t int_enable:1;
160 uint32_t src_snoop_disable:1;
161 uint32_t dest_snoop_disable:1;
162 uint32_t completion_update:1;
165 uint32_t src_page_break:1;
166 uint32_t dest_page_break:1;
170 uint32_t reserved:13;
171 #define IOAT_OP_COPY 0x00
184 struct ioat_fill_hw_descriptor {
187 uint32_t control_raw;
188 struct generic_dma_control control_generic;
190 uint32_t int_enable:1;
192 uint32_t dest_snoop_disable:1;
193 uint32_t completion_update:1;
195 uint32_t reserved2:2;
196 uint32_t dest_page_break:1;
198 uint32_t reserved3:15;
199 #define IOAT_OP_FILL 0x01
207 uint64_t next_dest_addr;
212 struct ioat_xor_hw_descriptor {
215 uint32_t control_raw;
216 struct generic_dma_control control_generic;
218 uint32_t int_enable:1;
219 uint32_t src_snoop_disable:1;
220 uint32_t dest_snoop_disable:1;
221 uint32_t completion_update:1;
223 uint32_t src_count:3;
227 uint32_t reserved:13;
228 #define IOAT_OP_XOR 0x87
229 #define IOAT_OP_XOR_VAL 0x88
242 struct ioat_xor_ext_hw_descriptor {
247 uint64_t reserved[4];
250 struct ioat_pq_hw_descriptor {
253 uint32_t control_raw;
254 struct generic_dma_control control_generic;
256 uint32_t int_enable:1;
257 uint32_t src_snoop_disable:1;
258 uint32_t dest_snoop_disable:1;
259 uint32_t completion_update:1;
261 uint32_t src_count:3;
265 uint32_t p_disable:1;
266 uint32_t q_disable:1;
267 uint32_t reserved:11;
268 #define IOAT_OP_PQ 0x89
269 #define IOAT_OP_PQ_VAL 0x8a
282 struct ioat_pq_ext_hw_descriptor {
289 uint64_t reserved[2];
292 struct ioat_pq_update_hw_descriptor {
295 uint32_t control_raw;
296 struct generic_dma_control control_generic;
298 uint32_t int_enable:1;
299 uint32_t src_snoop_disable:1;
300 uint32_t dest_snoop_disable:1;
301 uint32_t completion_update:1;
307 uint32_t p_disable:1;
308 uint32_t q_disable:1;
311 #define IOAT_OP_PQ_UP 0x8b
324 struct ioat_raw_hw_descriptor {
329 bus_dmaengine_callback_t callback_fn;
333 struct ioat_descriptor {
334 struct bus_dmadesc bus_dmadesc;
336 struct ioat_generic_hw_descriptor *generic;
337 struct ioat_dma_hw_descriptor *dma;
338 struct ioat_fill_hw_descriptor *fill;
339 struct ioat_xor_hw_descriptor *xor;
340 struct ioat_xor_ext_hw_descriptor *xor_ext;
341 struct ioat_pq_hw_descriptor *pq;
342 struct ioat_pq_ext_hw_descriptor *pq_ext;
343 struct ioat_raw_hw_descriptor *raw;
347 enum validate_flags *validate_result;
348 bus_addr_t hw_desc_bus_addr;
352 IOAT_DMAENGINE_REF = 0,
353 IOAT_ACTIVE_DESCR_REF,
357 /* One of these per allocated PCI device. */
359 bus_dmaengine_t dmaengine;
360 #define to_ioat_softc(_dmaeng) \
362 bus_dmaengine_t *_p = (_dmaeng); \
363 (struct ioat_softc *)((char *)_p - \
364 offsetof(struct ioat_softc, dmaengine)); \
370 struct mtx submit_lock;
372 bus_space_tag_t pci_bus_tag;
373 bus_space_handle_t pci_bus_handle;
375 struct resource *pci_resource;
376 uint32_t max_xfer_size;
377 uint32_t capabilities;
379 struct resource *res;
383 bus_dma_tag_t hw_desc_tag;
384 bus_dmamap_t hw_desc_map;
386 bus_dma_tag_t comp_update_tag;
387 bus_dmamap_t comp_update_map;
388 uint64_t *comp_update;
389 bus_addr_t comp_update_bus_addr;
391 struct callout timer;
394 boolean_t is_resize_pending;
395 boolean_t is_completion_pending;
396 boolean_t is_reset_pending;
397 boolean_t is_channel_running;
402 uint32_t ring_size_order;
403 bus_addr_t last_seen;
405 struct ioat_descriptor **ring;
407 struct mtx cleanup_lock;
408 volatile uint32_t refcnt;
410 volatile uint32_t refkinds[IOAT_NUM_REF_KINDS];
414 void ioat_test_attach(void);
415 void ioat_test_detach(void);
417 static inline uint64_t
418 ioat_get_chansts(struct ioat_softc *ioat)
422 if (ioat->version >= IOAT_VER_3_3)
423 status = ioat_read_8(ioat, IOAT_CHANSTS_OFFSET);
425 /* Must read lower 4 bytes before upper 4 bytes. */
426 status = ioat_read_double_4(ioat, IOAT_CHANSTS_OFFSET);
431 ioat_write_chancmp(struct ioat_softc *ioat, uint64_t addr)
434 if (ioat->version >= IOAT_VER_3_3)
435 ioat_write_8(ioat, IOAT_CHANCMP_OFFSET_LOW, addr);
437 ioat_write_double_4(ioat, IOAT_CHANCMP_OFFSET_LOW, addr);
441 ioat_write_chainaddr(struct ioat_softc *ioat, uint64_t addr)
444 if (ioat->version >= IOAT_VER_3_3)
445 ioat_write_8(ioat, IOAT_CHAINADDR_OFFSET_LOW, addr);
447 ioat_write_double_4(ioat, IOAT_CHAINADDR_OFFSET_LOW, addr);
450 static inline boolean_t
451 is_ioat_active(uint64_t status)
453 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
456 static inline boolean_t
457 is_ioat_idle(uint64_t status)
459 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_IDLE);
462 static inline boolean_t
463 is_ioat_halted(uint64_t status)
465 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
468 static inline boolean_t
469 is_ioat_suspended(uint64_t status)
471 return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
475 ioat_suspend(struct ioat_softc *ioat)
477 ioat_write_1(ioat, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_SUSPEND);
481 ioat_reset(struct ioat_softc *ioat)
483 ioat_write_1(ioat, IOAT_CHANCMD_OFFSET, IOAT_CHANCMD_RESET);
486 static inline boolean_t
487 ioat_reset_pending(struct ioat_softc *ioat)
491 cmd = ioat_read_1(ioat, IOAT_CHANCMD_OFFSET);
492 return ((cmd & IOAT_CHANCMD_RESET) != 0);
495 #endif /* __IOAT_INTERNAL_H__ */