2 * Copyright (C) 2012 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/ioccom.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/sysctl.h>
42 #include <dev/pci/pcireg.h>
43 #include <dev/pci/pcivar.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <machine/stdarg.h>
48 #include <vm/vm_param.h>
53 #include "ioat_internal.h"
54 #include "ioat_test.h"
57 #define time_after(a,b) ((long)(b) - (long)(a) < 0)
60 MALLOC_DEFINE(M_IOAT_TEST, "ioat_test", "ioat test allocations");
62 #define IOAT_MAX_BUFS 256
64 struct test_transaction {
65 void *buf[IOAT_MAX_BUFS];
68 uint32_t crc[IOAT_MAX_BUFS];
69 struct ioat_test *test;
70 TAILQ_ENTRY(test_transaction) entry;
73 #define IT_LOCK() mtx_lock(&ioat_test_lk)
74 #define IT_UNLOCK() mtx_unlock(&ioat_test_lk)
75 #define IT_ASSERT() mtx_assert(&ioat_test_lk, MA_OWNED)
76 static struct mtx ioat_test_lk;
77 MTX_SYSINIT(ioat_test_lk, &ioat_test_lk, "test coordination mtx", MTX_DEF);
79 static int g_thread_index = 1;
80 static struct cdev *g_ioat_cdev = NULL;
82 #define ioat_test_log(v, ...) _ioat_test_log((v), "ioat_test: " __VA_ARGS__)
83 static void _ioat_test_log(int verbosity, const char *fmt, ...);
86 ioat_test_transaction_destroy(struct test_transaction *tx)
88 struct ioat_test *test;
93 for (i = 0; i < IOAT_MAX_BUFS; i++) {
94 if (tx->buf[i] != NULL) {
95 if (test->testkind == IOAT_TEST_DMA_8K)
96 free(tx->buf[i], M_IOAT_TEST);
98 contigfree(tx->buf[i], tx->length, M_IOAT_TEST);
103 free(tx, M_IOAT_TEST);
107 test_transaction *ioat_test_transaction_create(struct ioat_test *test,
108 unsigned num_buffers)
110 struct test_transaction *tx;
113 tx = malloc(sizeof(*tx), M_IOAT_TEST, M_NOWAIT | M_ZERO);
117 tx->length = test->buffer_size;
119 for (i = 0; i < num_buffers; i++) {
120 if (test->testkind == IOAT_TEST_DMA_8K)
121 tx->buf[i] = malloc(test->buffer_size, M_IOAT_TEST,
124 tx->buf[i] = contigmalloc(test->buffer_size,
125 M_IOAT_TEST, M_NOWAIT, 0, BUS_SPACE_MAXADDR,
128 if (tx->buf[i] == NULL) {
129 ioat_test_transaction_destroy(tx);
137 dump_hex(void *p, size_t chunks)
141 for (i = 0; i < chunks; i++) {
142 for (j = 0; j < 8; j++)
143 printf("%08x ", ((uint32_t *)p)[i * 8 + j]);
149 ioat_compare_ok(struct test_transaction *tx)
151 struct ioat_test *test;
157 for (i = 0; i < tx->depth; i++) {
158 dst = tx->buf[2 * i + 1];
159 src = tx->buf[2 * i];
161 if (test->testkind == IOAT_TEST_FILL) {
162 for (j = 0; j < tx->length; j += sizeof(uint64_t)) {
163 if (memcmp(src, &dst[j],
164 MIN(sizeof(uint64_t), tx->length - j))
168 } else if (test->testkind == IOAT_TEST_DMA) {
169 if (memcmp(src, dst, tx->length) != 0)
171 } else if (test->testkind == IOAT_TEST_RAW_DMA) {
173 dst = test->raw_vtarget;
174 dump_hex(dst, tx->length / 32);
181 ioat_dma_test_callback(void *arg, int error)
183 struct test_transaction *tx;
184 struct ioat_test *test;
187 ioat_test_log(0, "%s: Got error: %d\n", __func__, error);
192 if (test->verify && !ioat_compare_ok(tx)) {
193 ioat_test_log(0, "miscompare found\n");
194 atomic_add_32(&test->status[IOAT_TEST_MISCOMPARE], tx->depth);
195 } else if (!test->too_late)
196 atomic_add_32(&test->status[IOAT_TEST_OK], tx->depth);
199 TAILQ_REMOVE(&test->pend_q, tx, entry);
200 TAILQ_INSERT_TAIL(&test->free_q, tx, entry);
201 wakeup(&test->free_q);
206 ioat_test_prealloc_memory(struct ioat_test *test, int index)
209 struct test_transaction *tx;
211 for (i = 0; i < test->transactions; i++) {
212 tx = ioat_test_transaction_create(test, test->chain_depth * 2);
214 ioat_test_log(0, "tx == NULL - memory exhausted\n");
215 test->status[IOAT_TEST_NO_MEMORY]++;
219 TAILQ_INSERT_HEAD(&test->free_q, tx, entry);
222 tx->depth = test->chain_depth;
224 /* fill in source buffers */
225 for (j = 0; j < (tx->length / sizeof(uint32_t)); j++) {
226 uint32_t val = j + (index << 28);
228 for (k = 0; k < test->chain_depth; k++) {
229 ((uint32_t *)tx->buf[2*k])[j] = ~val;
230 ((uint32_t *)tx->buf[2*k+1])[j] = val;
238 ioat_test_release_memory(struct ioat_test *test)
240 struct test_transaction *tx, *s;
242 TAILQ_FOREACH_SAFE(tx, &test->free_q, entry, s)
243 ioat_test_transaction_destroy(tx);
244 TAILQ_INIT(&test->free_q);
246 TAILQ_FOREACH_SAFE(tx, &test->pend_q, entry, s)
247 ioat_test_transaction_destroy(tx);
248 TAILQ_INIT(&test->pend_q);
252 ioat_test_submit_1_tx(struct ioat_test *test, bus_dmaengine_t dma)
254 struct test_transaction *tx;
255 struct bus_dmadesc *desc;
256 bus_dmaengine_callback_t cb;
257 bus_addr_t src, dest;
258 uint64_t fillpattern;
264 while (TAILQ_EMPTY(&test->free_q))
265 msleep(&test->free_q, &ioat_test_lk, 0, "test_submit", 0);
267 tx = TAILQ_FIRST(&test->free_q);
268 TAILQ_REMOVE(&test->free_q, tx, entry);
269 TAILQ_INSERT_HEAD(&test->pend_q, tx, entry);
272 if (test->testkind != IOAT_TEST_MEMCPY)
274 for (i = 0; i < tx->depth; i++) {
275 if (test->testkind == IOAT_TEST_MEMCPY) {
276 memcpy(tx->buf[2 * i + 1], tx->buf[2 * i], tx->length);
277 if (i == tx->depth - 1)
278 ioat_dma_test_callback(tx, 0);
282 src = vtophys((vm_offset_t)tx->buf[2*i]);
283 dest = vtophys((vm_offset_t)tx->buf[2*i+1]);
285 if (test->testkind == IOAT_TEST_RAW_DMA) {
287 dest = test->raw_target;
289 src = test->raw_target;
292 if (i == tx->depth - 1) {
293 cb = ioat_dma_test_callback;
300 if (test->testkind == IOAT_TEST_DMA ||
301 test->testkind == IOAT_TEST_RAW_DMA)
302 desc = ioat_copy(dma, dest, src, tx->length, cb, tx,
304 else if (test->testkind == IOAT_TEST_FILL) {
305 fillpattern = *(uint64_t *)tx->buf[2*i];
306 desc = ioat_blockfill(dma, dest, fillpattern,
307 tx->length, cb, tx, flags);
308 } else if (test->testkind == IOAT_TEST_DMA_8K) {
309 bus_addr_t src2, dst2;
311 src2 = vtophys((vm_offset_t)tx->buf[2*i] + PAGE_SIZE);
312 dst2 = vtophys((vm_offset_t)tx->buf[2*i+1] + PAGE_SIZE);
314 desc = ioat_copy_8k_aligned(dma, dest, dst2, src, src2,
316 } else if (test->testkind == IOAT_TEST_DMA_8K_PB) {
317 bus_addr_t src2, dst2;
319 src2 = vtophys((vm_offset_t)tx->buf[2*i+1] + PAGE_SIZE);
320 dst2 = vtophys((vm_offset_t)tx->buf[2*i] + PAGE_SIZE);
322 desc = ioat_copy_8k_aligned(dma, dest, dst2, src, src2,
324 } else if (test->testkind == IOAT_TEST_DMA_CRC) {
328 crc = vtophys((vm_offset_t)&tx->crc[i]);
329 desc = ioat_crc(dma, src, tx->length,
330 NULL, crc, cb, tx, flags | DMA_CRC_STORE);
331 } else if (test->testkind == IOAT_TEST_DMA_CRC_COPY) {
335 crc = vtophys((vm_offset_t)&tx->crc[i]);
336 desc = ioat_copy_crc(dma, dest, src, tx->length,
337 NULL, crc, cb, tx, flags | DMA_CRC_STORE);
342 if (test->testkind == IOAT_TEST_MEMCPY)
347 * We couldn't issue an IO -- either the device is being detached or
348 * the HW reset. Essentially spin until the device comes back up or
351 if (desc == NULL && tx->depth > 0) {
352 atomic_add_32(&test->status[IOAT_TEST_NO_DMA_ENGINE], tx->depth);
354 TAILQ_REMOVE(&test->pend_q, tx, entry);
355 TAILQ_INSERT_HEAD(&test->free_q, tx, entry);
361 ioat_dma_test(void *arg)
363 struct ioat_softc *ioat;
364 struct ioat_test *test;
365 bus_dmaengine_t dmaengine;
367 int index, rc, start, end, error;
370 memset(__DEVOLATILE(void *, test->status), 0, sizeof(test->status));
372 if ((test->testkind == IOAT_TEST_DMA_8K ||
373 test->testkind == IOAT_TEST_DMA_8K_PB) &&
374 test->buffer_size != 2 * PAGE_SIZE) {
375 ioat_test_log(0, "Asked for 8k test and buffer size isn't 8k\n");
376 test->status[IOAT_TEST_INVALID_INPUT]++;
380 if (test->buffer_size > 1024 * 1024) {
381 ioat_test_log(0, "Buffer size too large >1MB\n");
382 test->status[IOAT_TEST_NO_MEMORY]++;
386 if (test->chain_depth * 2 > IOAT_MAX_BUFS) {
387 ioat_test_log(0, "Depth too large (> %u)\n",
388 (unsigned)IOAT_MAX_BUFS / 2);
389 test->status[IOAT_TEST_NO_MEMORY]++;
393 if (btoc((uint64_t)test->buffer_size * test->chain_depth *
394 test->transactions) > (physmem / 4)) {
395 ioat_test_log(0, "Sanity check failed -- test would "
396 "use more than 1/4 of phys mem.\n");
397 test->status[IOAT_TEST_NO_MEMORY]++;
401 if ((uint64_t)test->transactions * test->chain_depth > (1<<16)) {
402 ioat_test_log(0, "Sanity check failed -- test would "
403 "use more than available IOAT ring space.\n");
404 test->status[IOAT_TEST_NO_MEMORY]++;
408 if (test->testkind >= IOAT_NUM_TESTKINDS) {
409 ioat_test_log(0, "Invalid kind %u\n",
410 (unsigned)test->testkind);
411 test->status[IOAT_TEST_INVALID_INPUT]++;
415 dmaengine = ioat_get_dmaengine(test->channel_index, M_NOWAIT);
416 if (dmaengine == NULL) {
417 ioat_test_log(0, "Couldn't acquire dmaengine\n");
418 test->status[IOAT_TEST_NO_DMA_ENGINE]++;
421 ioat = to_ioat_softc(dmaengine);
423 if (test->testkind == IOAT_TEST_FILL &&
424 (ioat->capabilities & IOAT_DMACAP_BFILL) == 0)
427 "Hardware doesn't support block fill, aborting test\n");
428 test->status[IOAT_TEST_INVALID_INPUT]++;
432 if (test->coalesce_period > ioat->intrdelay_max) {
434 "Hardware doesn't support intrdelay of %u us.\n",
435 (unsigned)test->coalesce_period);
436 test->status[IOAT_TEST_INVALID_INPUT]++;
439 error = ioat_set_interrupt_coalesce(dmaengine, test->coalesce_period);
440 if (error == ENODEV && test->coalesce_period == 0)
443 ioat_test_log(0, "ioat_set_interrupt_coalesce: %d\n", error);
444 test->status[IOAT_TEST_INVALID_INPUT]++;
448 if (test->zero_stats)
449 memset(&ioat->stats, 0, sizeof(ioat->stats));
451 if (test->testkind == IOAT_TEST_RAW_DMA) {
452 if (test->raw_is_virtual) {
453 test->raw_vtarget = (void *)test->raw_target;
454 test->raw_target = vtophys(test->raw_vtarget);
456 test->raw_vtarget = pmap_mapdev(test->raw_target,
461 index = g_thread_index++;
462 TAILQ_INIT(&test->free_q);
463 TAILQ_INIT(&test->pend_q);
465 if (test->duration == 0)
466 ioat_test_log(1, "Thread %d: num_loops remaining: 0x%08x\n",
467 index, test->transactions);
469 ioat_test_log(1, "Thread %d: starting\n", index);
471 rc = ioat_test_prealloc_memory(test, index);
473 ioat_test_log(0, "prealloc_memory: %d\n", rc);
478 test->too_late = false;
480 end = start + (((sbintime_t)test->duration * hz) / 1000);
482 for (loops = 0;; loops++) {
483 if (test->duration == 0 && loops >= test->transactions)
485 else if (test->duration != 0 && time_after(ticks, end)) {
486 test->too_late = true;
490 ioat_test_submit_1_tx(test, dmaengine);
493 ioat_test_log(1, "Test Elapsed: %d ticks (overrun %d), %d sec.\n",
494 ticks - start, ticks - end, (ticks - start) / hz);
497 while (!TAILQ_EMPTY(&test->pend_q))
498 msleep(&test->free_q, &ioat_test_lk, 0, "ioattestcompl", hz);
501 ioat_test_log(1, "Test Elapsed2: %d ticks (overrun %d), %d sec.\n",
502 ticks - start, ticks - end, (ticks - start) / hz);
504 ioat_test_release_memory(test);
506 if (test->testkind == IOAT_TEST_RAW_DMA && !test->raw_is_virtual)
507 pmap_unmapdev((vm_offset_t)test->raw_vtarget,
509 ioat_put_dmaengine(dmaengine);
513 ioat_test_open(struct cdev *dev, int flags, int fmt, struct thread *td)
520 ioat_test_close(struct cdev *dev, int flags, int fmt, struct thread *td)
527 ioat_test_ioctl(struct cdev *dev, unsigned long cmd, caddr_t arg, int flag,
541 static struct cdevsw ioat_cdevsw = {
542 .d_version = D_VERSION,
544 .d_open = ioat_test_open,
545 .d_close = ioat_test_close,
546 .d_ioctl = ioat_test_ioctl,
547 .d_name = "ioat_test",
551 enable_ioat_test(bool enable)
554 mtx_assert(&Giant, MA_OWNED);
556 if (enable && g_ioat_cdev == NULL) {
557 g_ioat_cdev = make_dev(&ioat_cdevsw, 0, UID_ROOT, GID_WHEEL,
559 } else if (!enable && g_ioat_cdev != NULL) {
560 destroy_dev(g_ioat_cdev);
567 sysctl_enable_ioat_test(SYSCTL_HANDLER_ARGS)
571 enabled = (g_ioat_cdev != NULL);
572 error = sysctl_handle_int(oidp, &enabled, 0, req);
573 if (error != 0 || req->newptr == NULL)
576 enable_ioat_test(enabled);
579 SYSCTL_PROC(_hw_ioat, OID_AUTO, enable_ioat_test,
580 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 0, 0,
581 sysctl_enable_ioat_test, "I",
582 "Non-zero: Enable the /dev/ioat_test device");
585 ioat_test_attach(void)
589 val = kern_getenv("hw.ioat.enable_ioat_test");
590 if (val != NULL && strcmp(val, "0") != 0) {
592 enable_ioat_test(true);
599 ioat_test_detach(void)
603 enable_ioat_test(false);
608 _ioat_test_log(int verbosity, const char *fmt, ...)
612 if (verbosity > g_ioat_debug_level)