2 * Copyright (c) 2006 IronPort Systems Inc. <ambrisko@ironport.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef __IPMIVARS_H__
30 #define __IPMIVARS_H__
32 struct ipmi_get_info {
43 TAILQ_ENTRY(ipmi_request) ir_link;
44 struct ipmi_device *ir_owner; /* Driver uses NULL. */
45 u_char *ir_request; /* Request is data to send to BMC. */
47 u_char *ir_reply; /* Reply is data read from BMC. */
48 size_t ir_replybuflen; /* Length of ir_reply[] buffer. */
49 int ir_replylen; /* Length of reply from BMC. */
61 #define SMIC_CTL_STS 1
66 /* Per file descriptor data. */
68 TAILQ_ENTRY(ipmi_device) ipmi_link;
69 TAILQ_HEAD(,ipmi_request) ipmi_completed_requests;
70 struct selinfo ipmi_select;
71 struct ipmi_softc *ipmi_softc;
74 u_char ipmi_address; /* IPMB address. */
93 struct ipmi_smic smic;
94 struct ipmi_ssif ssif;
98 struct mtx ipmi_io_lock;
99 struct resource *ipmi_io_res[MAX_RES];
102 struct resource *ipmi_irq_res;
106 struct cdev *ipmi_cdev;
107 TAILQ_HEAD(,ipmi_request) ipmi_pending_requests;
108 int ipmi_driver_requests_polled;
109 eventhandler_tag ipmi_watchdog_tag;
110 int ipmi_watchdog_active;
111 struct intr_config_hook ipmi_ich;
112 struct mtx ipmi_requests_lock;
113 struct cv ipmi_request_added;
114 struct proc *ipmi_kthread;
115 driver_intr_t *ipmi_intr;
116 int (*ipmi_startup)(struct ipmi_softc *);
117 int (*ipmi_enqueue_request)(struct ipmi_softc *, struct ipmi_request *);
118 int (*ipmi_driver_request)(struct ipmi_softc *, struct ipmi_request *, int);
121 #define ipmi_ssif_smbus_address _iface.ssif.smbus_address
122 #define ipmi_ssif_smbus _iface.ssif.smbus
128 #define KCS_MODE 0x01
129 #define SMIC_MODE 0x02
131 #define SSIF_MODE 0x04
133 /* KCS status flags */
134 #define KCS_STATUS_OBF 0x01 /* Data Out ready from BMC */
135 #define KCS_STATUS_IBF 0x02 /* Data In from System */
136 #define KCS_STATUS_SMS_ATN 0x04 /* Ready in RX queue */
137 #define KCS_STATUS_C_D 0x08 /* Command/Data register write*/
138 #define KCS_STATUS_OEM1 0x10
139 #define KCS_STATUS_OEM2 0x20
140 #define KCS_STATUS_S0 0x40
141 #define KCS_STATUS_S1 0x80
142 #define KCS_STATUS_STATE(x) ((x)>>6)
143 #define KCS_STATUS_STATE_IDLE 0x0
144 #define KCS_STATUS_STATE_READ 0x1
145 #define KCS_STATUS_STATE_WRITE 0x2
146 #define KCS_STATUS_STATE_ERROR 0x3
147 #define KCS_IFACE_STATUS_OK 0x00
148 #define KCS_IFACE_STATUS_ABORT 0x01
149 #define KCS_IFACE_STATUS_ILLEGAL 0x02
150 #define KCS_IFACE_STATUS_LENGTH_ERR 0x06
151 #define KCS_IFACE_STATUS_UNKNOWN_ERR 0xff
153 /* KCS control codes */
154 #define KCS_CONTROL_GET_STATUS_ABORT 0x60
155 #define KCS_CONTROL_WRITE_START 0x61
156 #define KCS_CONTROL_WRITE_END 0x62
157 #define KCS_DATA_IN_READ 0x68
159 /* SMIC status flags */
160 #define SMIC_STATUS_BUSY 0x01 /* System set and BMC clears it */
161 #define SMIC_STATUS_SMS_ATN 0x04 /* BMC has a message */
162 #define SMIC_STATUS_EVT_ATN 0x08 /* Event has been RX */
163 #define SMIC_STATUS_SMI 0x10 /* asserted SMI */
164 #define SMIC_STATUS_TX_RDY 0x40 /* Ready to accept WRITE */
165 #define SMIC_STATUS_RX_RDY 0x80 /* Ready to read */
166 #define SMIC_STATUS_RESERVED 0x22
168 /* SMIC control codes */
169 #define SMIC_CC_SMS_GET_STATUS 0x40
170 #define SMIC_CC_SMS_WR_START 0x41
171 #define SMIC_CC_SMS_WR_NEXT 0x42
172 #define SMIC_CC_SMS_WR_END 0x43
173 #define SMIC_CC_SMS_RD_START 0x44
174 #define SMIC_CC_SMS_RD_NEXT 0x45
175 #define SMIC_CC_SMS_RD_END 0x46
177 /* SMIC status codes */
178 #define SMIC_SC_SMS_RDY 0xc0
179 #define SMIC_SC_SMS_WR_START 0xc1
180 #define SMIC_SC_SMS_WR_NEXT 0xc2
181 #define SMIC_SC_SMS_WR_END 0xc3
182 #define SMIC_SC_SMS_RD_START 0xc4
183 #define SMIC_SC_SMS_RD_NEXT 0xc5
184 #define SMIC_SC_SMS_RD_END 0xc6
186 #define IPMI_ADDR(netfn, lun) ((netfn) << 2 | (lun))
187 #define IPMI_REPLY_ADDR(addr) ((addr) + 0x4)
189 #define IPMI_LOCK(sc) mtx_lock(&(sc)->ipmi_requests_lock)
190 #define IPMI_UNLOCK(sc) mtx_unlock(&(sc)->ipmi_requests_lock)
191 #define IPMI_LOCK_ASSERT(sc) mtx_assert(&(sc)->ipmi_requests_lock, MA_OWNED)
193 #define IPMI_IO_LOCK(sc) mtx_lock(&(sc)->ipmi_io_lock)
194 #define IPMI_IO_UNLOCK(sc) mtx_unlock(&(sc)->ipmi_io_lock)
195 #define IPMI_IO_LOCK_ASSERT(sc) mtx_assert(&(sc)->ipmi_io_lock, MA_OWNED)
197 /* I/O to a single I/O resource. */
198 #define INB_SINGLE(sc, x) \
199 bus_read_1((sc)->ipmi_io_res[0], (sc)->ipmi_io_spacing * (x))
200 #define OUTB_SINGLE(sc, x, value) \
201 bus_write_1((sc)->ipmi_io_res[0], (sc)->ipmi_io_spacing * (x), value)
203 /* I/O with each register in its in I/O resource. */
204 #define INB_MULTIPLE(sc, x) \
205 bus_read_1((sc)->ipmi_io_res[(x)], 0)
206 #define OUTB_MULTIPLE(sc, x, value) \
207 bus_write_1((sc)->ipmi_io_res[(x)], 0, value)
210 * Determine I/O method based on whether or not we have more than one I/O
214 ((sc)->ipmi_io_res[1] != NULL ? INB_MULTIPLE(sc, x) : INB_SINGLE(sc, x))
215 #define OUTB(sc, x, value) \
216 ((sc)->ipmi_io_res[1] != NULL ? OUTB_MULTIPLE(sc, x, value) : \
217 OUTB_SINGLE(sc, x, value))
219 #define MAX_TIMEOUT 6 * hz
221 int ipmi_attach(device_t);
222 int ipmi_detach(device_t);
223 void ipmi_release_resources(device_t);
225 /* Manage requests. */
226 struct ipmi_request *ipmi_alloc_request(struct ipmi_device *, long, uint8_t,
227 uint8_t, size_t, size_t);
228 void ipmi_complete_request(struct ipmi_softc *, struct ipmi_request *);
229 struct ipmi_request *ipmi_dequeue_request(struct ipmi_softc *);
230 void ipmi_free_request(struct ipmi_request *);
231 int ipmi_polled_enqueue_request(struct ipmi_softc *, struct ipmi_request *);
232 int ipmi_submit_driver_request(struct ipmi_softc *, struct ipmi_request *,
235 /* Identify BMC interface via SMBIOS. */
236 int ipmi_smbios_identify(struct ipmi_get_info *);
238 /* Match BMC PCI device listed in SMBIOS. */
239 const char *ipmi_pci_match(uint16_t, uint16_t);
241 /* Interface attach routines. */
242 int ipmi_kcs_attach(struct ipmi_softc *);
243 int ipmi_kcs_probe_align(struct ipmi_softc *);
244 int ipmi_smic_attach(struct ipmi_softc *);
245 int ipmi_ssif_attach(struct ipmi_softc *, device_t, int);
248 int ipmi_handle_attn(struct ipmi_softc *);
251 extern devclass_t ipmi_devclass;
252 extern int ipmi_attached;
254 #endif /* !__IPMIVARS_H__ */