4 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
6 * Copyright (c) 2004-2006
7 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice unmodified, this list of conditions, and the following
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd))
34 #define IPW_NDATA (IPW_NTBD / 2)
36 #define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd))
37 #define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status))
39 #define IPW_CSR_INTR 0x0008
40 #define IPW_CSR_INTR_MASK 0x000c
41 #define IPW_CSR_INDIRECT_ADDR 0x0010
42 #define IPW_CSR_INDIRECT_DATA 0x0014
43 #define IPW_CSR_AUTOINC_ADDR 0x0018
44 #define IPW_CSR_AUTOINC_DATA 0x001c
45 #define IPW_CSR_RST 0x0020
46 #define IPW_CSR_CTL 0x0024
47 #define IPW_CSR_IO 0x0030
48 #define IPW_CSR_TX_BASE 0x0200
49 #define IPW_CSR_TX_SIZE 0x0204
50 #define IPW_CSR_RX_BASE 0x0240
51 #define IPW_CSR_STATUS_BASE 0x0244
52 #define IPW_CSR_RX_SIZE 0x0248
53 #define IPW_CSR_TX_READ 0x0280
54 #define IPW_CSR_RX_READ 0x02a0
55 #define IPW_CSR_TABLE1_BASE 0x0380
56 #define IPW_CSR_TABLE2_BASE 0x0384
57 #define IPW_CSR_TX_WRITE 0x0f80
58 #define IPW_CSR_RX_WRITE 0x0fa0
60 /* possible flags for register IPW_CSR_INTR */
61 #define IPW_INTR_TX_TRANSFER 0x00000001
62 #define IPW_INTR_RX_TRANSFER 0x00000002
63 #define IPW_INTR_STATUS_CHANGE 0x00000010
64 #define IPW_INTR_COMMAND_DONE 0x00010000
65 #define IPW_INTR_FW_INIT_DONE 0x01000000
66 #define IPW_INTR_FATAL_ERROR 0x40000000
67 #define IPW_INTR_PARITY_ERROR 0x80000000
69 #define IPW_INTR_MASK \
70 (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \
71 IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \
72 IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \
73 IPW_INTR_PARITY_ERROR)
75 /* possible flags for register IPW_CSR_RST */
76 #define IPW_RST_PRINCETON_RESET 0x00000001
77 #define IPW_RST_SW_RESET 0x00000080
78 #define IPW_RST_MASTER_DISABLED 0x00000100
79 #define IPW_RST_STOP_MASTER 0x00000200
81 /* possible flags for register IPW_CSR_CTL */
82 #define IPW_CTL_CLOCK_READY 0x00000001
83 #define IPW_CTL_ALLOW_STANDBY 0x00000002
84 #define IPW_CTL_INIT 0x00000004
86 /* possible flags for register IPW_CSR_IO */
87 #define IPW_IO_GPIO1_ENABLE 0x00000008
88 #define IPW_IO_GPIO1_MASK 0x0000000c
89 #define IPW_IO_GPIO3_MASK 0x000000c0
90 #define IPW_IO_LED_OFF 0x00002000
91 #define IPW_IO_RADIO_DISABLED 0x00010000
93 /* state codes sent by fw on IPW_STATUS_CODE_NEWSTATE interrupt */
94 #define IPW_STATE_INITIALIZED 0x0001
95 #define IPW_STATE_CC_FOUND 0x0002 /* 802.11d cc received */
96 #define IPW_STATE_ASSOCIATED 0x0004
97 #define IPW_STATE_ASSOCIATION_LOST 0x0008
98 #define IPW_STATE_ASSOCIATION_CHANGED 0x0010 /* assoc params changed? */
99 #define IPW_STATE_SCAN_COMPLETE 0x0020
100 #define IPW_STATE_PS_ENTER 0x0040 /* entered power-save mode */
101 #define IPW_STATE_PS_EXIT 0x0080 /* exited power-save mode */
102 #define IPW_STATE_RADIO_DISABLED 0x0100
103 #define IPW_STATE_DISABLED 0x0200
104 #define IPW_STATE_POWER_DOWN 0x0400 /* ??? */
105 #define IPW_STATE_SCANNING 0x0800
108 #define IPW_INFO_LOCK 480
109 #define IPW_INFO_APS_CNT 604
110 #define IPW_INFO_APS_BASE 608
111 #define IPW_INFO_CARD_DISABLED 628
112 #define IPW_INFO_CURRENT_CHANNEL 756
113 #define IPW_INFO_CURRENT_TX_RATE 768
116 #define IPW_INFO_CURRENT_SSID 48
117 #define IPW_INFO_CURRENT_BSSID 112
119 /* supported rates */
120 #define IPW_RATE_DS1 1
121 #define IPW_RATE_DS2 2
122 #define IPW_RATE_DS5 4
123 #define IPW_RATE_DS11 8
125 /* firmware binary image header */
126 struct ipw_firmware_hdr {
132 /* buffer descriptor */
137 #define IPW_BD_FLAG_TX_FRAME_802_3 0x00
138 #define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01
139 #define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02
140 #define IPW_BD_FLAG_TX_FRAME_802_11 0x04
141 #define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08
142 uint8_t nfrag; /* number of fragments */
150 #define IPW_STATUS_CODE_COMMAND 0
151 #define IPW_STATUS_CODE_NEWSTATE 1
152 #define IPW_STATUS_CODE_DATA_802_11 2
153 #define IPW_STATUS_CODE_DATA_802_3 3
154 #define IPW_STATUS_CODE_NOTIFICATION 4
156 #define IPW_STATUS_FLAG_DECRYPTED 0x01
157 #define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02
158 #define IPW_STATUS_FLAG_CRC_ERROR 0x04
159 uint8_t rssi; /* received signal strength indicator */
160 #define IPW_RSSI_TO_DBM (-98) /* XXX fixed nf to convert dBm */
166 #define IPW_HDR_TYPE_SEND 33
172 uint8_t key[IEEE80211_KEYBUF_SIZE];
173 uint8_t reserved[10];
174 uint8_t src_addr[IEEE80211_ADDR_LEN];
175 uint8_t dst_addr[IEEE80211_ADDR_LEN];
182 #define IPW_CMD_ENABLE 2
183 #define IPW_CMD_SET_CONFIGURATION 6
184 #define IPW_CMD_SET_ESSID 8
185 #define IPW_CMD_SET_MANDATORY_BSSID 9
186 #define IPW_CMD_SET_MAC_ADDRESS 11
187 #define IPW_CMD_SET_MODE 12
188 #define IPW_CMD_SET_CHANNEL 14
189 #define IPW_CMD_SET_RTS_THRESHOLD 15
190 #define IPW_CMD_SET_FRAG_THRESHOLD 16
191 #define IPW_CMD_SET_POWER_MODE 17
192 #define IPW_CMD_SET_TX_RATES 18
193 #define IPW_CMD_SET_BASIC_TX_RATES 19
194 #define IPW_CMD_SET_WEP_KEY 20
195 #define IPW_CMD_SET_WEP_KEY_INDEX 25
196 #define IPW_CMD_SET_WEP_FLAGS 26
197 #define IPW_CMD_ADD_MULTICAST 27
198 #define IPW_CMD_SET_BEACON_INTERVAL 29
199 #define IPW_CMD_SET_TX_POWER_INDEX 36
200 #define IPW_CMD_BROADCAST_SCAN 43
201 #define IPW_CMD_DISABLE 44
202 #define IPW_CMD_SET_DESIRED_BSSID 45
203 #define IPW_CMD_SET_SCAN_OPTIONS 46
204 #define IPW_CMD_SET_SCAN_DWELL_TIME 47
205 #define IPW_CMD_SET_SHORT_RETRY 51
206 #define IPW_CMD_SET_LONG_RETRY 52
207 #define IPW_CMD_PREPARE_POWER_DOWN 58
208 #define IPW_CMD_DISABLE_PHY 61
209 #define IPW_CMD_SET_MSDU_TX_RATES 62
210 #define IPW_CMD_SET_SECURITY_INFO 67
211 #define IPW_CMD_DISASSOCIATE 68
212 #define IPW_CMD_SET_WPA_IE 69
218 uint8_t reserved[68];
221 /* possible values for command IPW_CMD_SET_POWER_MODE */
222 #define IPW_POWER_MODE_CAM 0
223 #define IPW_POWER_MODE_AUTO 6
225 /* possible values for command IPW_CMD_SET_MODE */
226 #define IPW_MODE_BSS 0
227 #define IPW_MODE_IBSS 1
228 #define IPW_MODE_MONITOR 2
230 /* possible flags for command IPW_CMD_SET_WEP_FLAGS */
231 #define IPW_WEPON 0x8
233 /* structure for command IPW_CMD_SET_WEP_KEY */
240 /* structure for command IPW_CMD_SET_SECURITY_INFORMATION */
241 struct ipw_security {
243 #define IPW_CIPHER_NONE 0x00000001
244 #define IPW_CIPHER_WEP40 0x00000002
245 #define IPW_CIPHER_TKIP 0x00000004
246 #define IPW_CIPHER_CCMP 0x00000010
247 #define IPW_CIPHER_WEP104 0x00000020
248 #define IPW_CIPHER_CKIP 0x00000040
251 #define IPW_AUTH_OPEN 0
252 #define IPW_AUTH_SHARED 1
256 /* structure for command IPW_CMD_SET_SCAN_OPTIONS */
257 struct ipw_scan_options {
259 #define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001
260 #define IPW_SCAN_MIXED_CELL 0x00000002
261 #define IPW_SCAN_PASSIVE 0x00000008
265 /* structure for command IPW_CMD_SET_CONFIGURATION */
266 struct ipw_configuration {
268 #define IPW_CFG_PROMISCUOUS 0x00000004
269 #define IPW_CFG_PREAMBLE_AUTO 0x00000010
270 #define IPW_CFG_IBSS_AUTO_START 0x00000020
271 #define IPW_CFG_802_1x_ENABLE 0x00004000
272 #define IPW_CFG_BSS_MASK 0x00008000
273 #define IPW_CFG_IBSS_MASK 0x00010000
278 /* structure for command IPW_CMD_SET_WPA_IE */
283 uint8_t bssid[IEEE80211_ADDR_LEN];
285 struct ieee80211_ie_wpa ie;
288 /* element in AP table */
290 uint32_t reserved1[2];
291 uint8_t bssid[IEEE80211_ADDR_LEN];
298 uint8_t reserved4[28];
299 uint8_t essid[IEEE80211_NWID_LEN];
302 uint8_t reserved6[7];
306 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */
308 #define IPW_MEM_EEPROM_CTL 0x00300040
310 #define IPW_EEPROM_RADIO 0x11
311 #define IPW_EEPROM_MAC 0x21
312 #define IPW_EEPROM_CHANNEL_LIST 0x37
314 #define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
316 #define IPW_EEPROM_C (1 << 0) /* Serial Clock */
317 #define IPW_EEPROM_S (1 << 1) /* Chip Select */
318 #define IPW_EEPROM_D (1 << 2) /* Serial data input */
319 #define IPW_EEPROM_Q (1 << 4) /* Serial data output */
321 #define IPW_EEPROM_SHIFT_D 2
322 #define IPW_EEPROM_SHIFT_Q 4
325 * control and status registers access macros
327 #define CSR_READ_1(sc, reg) \
328 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
330 #define CSR_READ_2(sc, reg) \
331 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
333 #define CSR_READ_4(sc, reg) \
334 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
336 #define CSR_WRITE_1(sc, reg, val) \
337 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
339 #define CSR_WRITE_2(sc, reg, val) \
340 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
342 #define CSR_WRITE_4(sc, reg, val) \
343 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
345 #define CSR_WRITE_MULTI_1(sc, reg, buf, len) \
346 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \
350 * indirect memory space access macros
352 #define MEM_READ_1(sc, addr) \
353 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
354 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA))
356 #define MEM_READ_4(sc, addr) \
357 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \
358 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA))
360 #define MEM_WRITE_1(sc, addr, val) do { \
361 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
362 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
363 } while (/* CONSTCOND */0)
365 #define MEM_WRITE_2(sc, addr, val) do { \
366 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
368 } while (/* CONSTCOND */0)
370 #define MEM_WRITE_4(sc, addr, val) do { \
371 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
372 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
373 } while (/* CONSTCOND */0)
375 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
376 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
377 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \
378 } while (/* CONSTCOND */0)
381 * EEPROM access macro
383 #define IPW_EEPROM_CTL(sc, val) do { \
384 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \
385 DELAY(IPW_EEPROM_DELAY); \