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56 #ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
57 #define _SCIC_SDS_CONTROLLER_REGISTERS_H_
62 * @brief This file contains macros used to perform the register reads/writes
63 * to the SCU hardware.
70 #include <dev/isci/scil/scu_registers.h>
71 #include <dev/isci/scil/scic_sds_controller.h>
74 * @name SMU_REGISTER_ACCESS_MACROS
77 #define scic_sds_controller_smu_register_read(controller, reg) \
80 (controller)->smu_registers->reg \
83 #define scic_sds_controller_smu_register_write(controller, reg, value) \
86 (controller)->smu_registers->reg, \
92 * @name AFE_REGISTER_ACCESS_MACROS
95 #define scu_afe_register_write(controller, reg, value) \
98 (controller)->scu_registers->afe.reg, \
102 #define scu_afe_register_read(controller, reg) \
105 (controller)->scu_registers->afe.reg \
110 * @name SGPIO_PEG0_REGISTER_ACCESS_MACROS
113 #define scu_sgpio_peg0_register_read(controller, reg) \
116 (controller)->scu_registers->peg0.sgpio.reg \
119 #define scu_sgpio_peg0_register_write(controller, reg, value) \
120 scu_register_write( \
122 (controller)->scu_registers->peg0.sgpio.reg, \
128 * @name VIIT_REGISTER_ACCESS_MACROS
131 #define scu_controller_viit_register_write(controller, index, reg, value) \
132 scu_register_write( \
134 (controller)->scu_registers->peg0.viit[index].reg, \
140 * @name SCRATCH_RAM_REGISTER_ACCESS_MACROS
143 // Scratch RAM access may be needed before the scu_registers pointer
144 // has been initialized. So instead, explicitly cast BAR1 to a
145 // SCU_REGISTERS_T data structure.
147 // Scratch RAM is stored in the Zoning Permission Table for OROM use.
148 #define scu_controller_scratch_ram_register_write(controller, index, value) \
149 scu_register_write( \
151 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \
155 #define scu_controller_scratch_ram_register_read(controller, index) \
158 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \
161 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \
162 scu_register_write( \
164 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \
168 #define scu_controller_scratch_ram_register_read_ext(controller, index) \
171 ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \
176 //*****************************************************************************
178 //*****************************************************************************
181 * @name SMU_REGISTERS
184 #define SMU_PCP_WRITE(controller, value) \
185 scic_sds_controller_smu_register_write( \
186 controller, post_context_port, value \
189 #define SMU_TCR_READ(controller, value) \
190 scic_sds_controller_smu_register_read( \
191 controller, task_context_range \
194 #define SMU_TCR_WRITE(controller, value) \
195 scic_sds_controller_smu_register_write( \
196 controller, task_context_range, value \
199 #define SMU_HTTBAR_WRITE(controller, address) \
201 scic_sds_controller_smu_register_write( \
203 host_task_table_lower, \
204 sci_cb_physical_address_lower(address) \
206 scic_sds_controller_smu_register_write( \
208 host_task_table_upper, \
209 sci_cb_physical_address_upper(address) \
213 #define SMU_CQBAR_WRITE(controller, address) \
215 scic_sds_controller_smu_register_write( \
217 completion_queue_lower, \
218 sci_cb_physical_address_lower(address) \
220 scic_sds_controller_smu_register_write( \
222 completion_queue_upper, \
223 sci_cb_physical_address_upper(address) \
227 #define SMU_CQGR_WRITE(controller, value) \
228 scic_sds_controller_smu_register_write( \
229 controller, completion_queue_get, value \
232 #define SMU_CQGR_READ(controller, value) \
233 scic_sds_controller_smu_register_read( \
234 controller, completion_queue_get \
237 #define SMU_CQPR_WRITE(controller, value) \
238 scic_sds_controller_smu_register_write( \
239 controller, completion_queue_put, value \
242 #define SMU_RNCBAR_WRITE(controller, address) \
244 scic_sds_controller_smu_register_write( \
246 remote_node_context_lower, \
247 sci_cb_physical_address_lower(address) \
249 scic_sds_controller_smu_register_write( \
251 remote_node_context_upper, \
252 sci_cb_physical_address_upper(address) \
256 #define SMU_AMR_READ(controller) \
257 scic_sds_controller_smu_register_read( \
258 controller, address_modifier \
261 #define SMU_IMR_READ(controller) \
262 scic_sds_controller_smu_register_read( \
263 controller, interrupt_mask \
266 #define SMU_IMR_WRITE(controller, mask) \
267 scic_sds_controller_smu_register_write( \
268 controller, interrupt_mask, mask \
271 #define SMU_ISR_READ(controller) \
272 scic_sds_controller_smu_register_read( \
273 controller, interrupt_status \
276 #define SMU_ISR_WRITE(controller, status) \
277 scic_sds_controller_smu_register_write( \
278 controller, interrupt_status, status \
281 #define SMU_ICC_READ(controller) \
282 scic_sds_controller_smu_register_read( \
283 controller, interrupt_coalesce_control \
286 #define SMU_ICC_WRITE(controller, value) \
287 scic_sds_controller_smu_register_write( \
288 controller, interrupt_coalesce_control, value \
291 #define SMU_CQC_WRITE(controller, value) \
292 scic_sds_controller_smu_register_write( \
293 controller, completion_queue_control, value \
296 #define SMU_SMUSRCR_WRITE(controller, value) \
297 scic_sds_controller_smu_register_write( \
298 controller, soft_reset_control, value \
301 #define SMU_TCA_WRITE(controller, index, value) \
302 scic_sds_controller_smu_register_write( \
303 controller, task_context_assignment[index], value \
306 #define SMU_TCA_READ(controller, index) \
307 scic_sds_controller_smu_register_read( \
308 controller, task_context_assignment[index] \
311 #define SMU_DCC_READ(controller) \
312 scic_sds_controller_smu_register_read( \
313 controller, device_context_capacity \
316 #define SMU_DFC_READ(controller) \
317 scic_sds_controller_smu_register_read( \
318 controller, device_function_capacity \
321 #define SMU_SMUCSR_READ(controller) \
322 scic_sds_controller_smu_register_read( \
323 controller, control_status \
326 #define SMU_CGUCR_READ(controller) \
327 scic_sds_controller_smu_register_read( \
328 controller, clock_gating_control \
331 #define SMU_CGUCR_WRITE(controller, value) \
332 scic_sds_controller_smu_register_write( \
333 controller, clock_gating_control, value \
336 #define SMU_CQPR_READ(controller) \
337 scic_sds_controller_smu_register_read( \
338 controller, completion_queue_put \
344 * @name SCU_REGISTER_ACCESS_MACROS
347 #define scic_sds_controller_scu_register_read(controller, reg) \
350 (controller)->scu_registers->reg \
353 #define scic_sds_controller_scu_register_write(controller, reg, value) \
354 scu_register_write( \
356 (controller)->scu_registers->reg, \
362 //****************************************************************************
363 //* SCU SDMA REGISTERS
364 //****************************************************************************
367 * @name SCU_SDMA_REGISTER_ACCESS_MACROS
370 #define scu_sdma_register_read(controller, reg) \
373 (controller)->scu_registers->sdma.reg \
376 #define scu_sdma_register_write(controller, reg, value) \
377 scu_register_write( \
379 (controller)->scu_registers->sdma.reg, \
385 * @name SCU_SDMA_REGISTERS
388 #define SCU_PUFATHAR_WRITE(controller, address) \
390 scu_sdma_register_write( \
392 uf_address_table_lower, \
393 sci_cb_physical_address_lower(address) \
395 scu_sdma_register_write( \
397 uf_address_table_upper, \
398 sci_cb_physical_address_upper(address) \
402 #define SCU_UFHBAR_WRITE(controller, address) \
404 scu_sdma_register_write( \
406 uf_header_base_address_lower, \
407 sci_cb_physical_address_lower(address) \
409 scu_sdma_register_write( \
411 uf_header_base_address_upper, \
412 sci_cb_physical_address_upper(address) \
416 #define SCU_UFQC_READ(controller) \
417 scu_sdma_register_read( \
419 unsolicited_frame_queue_control \
422 #define SCU_UFQC_WRITE(controller, value) \
423 scu_sdma_register_write( \
425 unsolicited_frame_queue_control, \
429 #define SCU_UFQPP_READ(controller) \
430 scu_sdma_register_read( \
432 unsolicited_frame_put_pointer \
435 #define SCU_UFQPP_WRITE(controller, value) \
436 scu_sdma_register_write( \
438 unsolicited_frame_put_pointer, \
442 #define SCU_UFQGP_WRITE(controller, value) \
443 scu_sdma_register_write( \
445 unsolicited_frame_get_pointer, \
449 #define SCU_PDMACR_READ(controller) \
450 scu_sdma_register_read( \
455 #define SCU_PDMACR_WRITE(controller, value) \
456 scu_sdma_register_write( \
458 pdma_configuration, \
462 #define SCU_CDMACR_READ(controller) \
463 scu_sdma_register_read( \
468 #define SCU_CDMACR_WRITE(controller, value) \
469 scu_sdma_register_write( \
471 cdma_configuration, \
476 //*****************************************************************************
477 //* SCU CRAM AND FBRAM Registers
478 //*****************************************************************************
480 * @name SCU_CRAM_REGISTER_ACCESS_MACROS
483 #define scu_cram_register_read(controller, reg) \
486 (controller)->scu_registers->cram.reg \
489 #define scu_cram_register_write(controller, reg, value) \
490 scu_register_write( \
492 (controller)->scu_registers->cram.reg, \
498 * @name SCU_FBRAM_REGISTER_ACCESS_MACROS
501 #define scu_fbram_register_read(controller, reg) \
504 (controller)->scu_registers->fbram.reg \
507 #define scu_fbram_register_write(controller, reg, value) \
508 scu_register_write( \
510 (controller)->scu_registers->fbram.reg, \
517 * @name SCU_CRAM_REGISTERS
521 // SRAM ECC CONTROL REGISTER BITS
522 #define SIGNLE_BIT_ERROR_CORRECTION_ENABLE 0x00000001
523 #define MULTI_BIT_ERROR_REPORTING_ENABLE 0x00000002
524 #define SINGLE_BIT_ERROR_REPORTING_ENABLE 0x00000004
526 //SRAM ECC control register (SECR0)
527 #define SCU_SECR0_WRITE(controller, value) \
528 scu_cram_register_write( \
530 sram_ecc_control_0, \
536 * @name SCU_FBRAM_REGISTERS
540 //SRAM ECC control register (SECR1)
541 #define SCU_SECR1_WRITE(controller, value) \
542 scu_fbram_register_write( \
544 sram_ecc_control_1, \
550 //*****************************************************************************
551 //* SCU Port Task Scheduler Group Registers
552 //*****************************************************************************
555 * @name SCU_PTSG_REGISTER_ACCESS_MACROS
558 #define scu_ptsg_register_read(controller, reg) \
561 (controller)->scu_registers->peg0.ptsg.reg \
564 #define scu_ptsg_register_write(controller, reg, value) \
565 scu_register_write( \
567 (controller)->scu_registers->peg0.ptsg.reg, \
573 * @name SCU_PTSG_REGISTERS
576 #define SCU_PTSGCR_READ(controller) \
577 scu_ptsg_register_read( \
582 #define SCU_PTSGCR_WRITE(controller, value) \
583 scu_ptsg_register_write( \
589 #define SCU_PTSGRTC_READ(controller) \
590 scu_ptsg_register_read( \
598 #endif // __cplusplus
600 #endif // _SCIC_SDS_CONTROLLER_REGISTERS_H_