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53 #include <sys/cdefs.h>
54 __FBSDID("$FreeBSD$");
59 * @brief This file contains the method implementations utilized in writing
60 * out PCI data for the SCI core.
63 #include <dev/isci/scil/scic_user_callback.h>
65 #include <dev/isci/scil/scic_sds_pci.h>
66 #include <dev/isci/scil/scic_sds_controller.h>
69 * @brief This method reads from the driver the BARs that are needed to
70 * determine the virtual memory space for the controller registers
72 * @param[in] this_controller The controller for which to read the base
75 void scic_sds_pci_bar_initialization(
76 SCIC_SDS_CONTROLLER_T* this_controller
79 #ifdef ARLINGTON_BUILD
81 #define ARLINGTON_LEX_BAR 0
82 #define ARLINGTON_SMU_BAR 1
83 #define ARLINGTON_SCU_BAR 2
84 #define LEX_REGISTER_OFFSET 0x40000
86 this_controller->lex_registers =
87 ((char *)scic_cb_pci_get_bar(
88 this_controller, ARLINGTON_LEX_BAR) + LEX_REGISTER_OFFSET);
89 this_controller->smu_registers =
90 (SMU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SMU_BAR);
91 this_controller->scu_registers =
92 (SCU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SCU_BAR);
94 #else // !ARLINGTON_BUILD
96 #if !defined(ENABLE_PCI_IO_SPACE_ACCESS)
98 this_controller->smu_registers =
100 (char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SMU_BAR)
101 +(0x4000 * this_controller->controller_index));
102 this_controller->scu_registers =
104 (char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SCU_BAR)
105 +(0x400000 * this_controller->controller_index));
107 #else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
109 if (this_controller->controller_index == 0)
111 this_controller->smu_registers = (SMU_REGISTERS_T *)
112 scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0);
116 if (this_controller->pci_revision == SCU_PBG_HBA_REV_B0)
118 // SCU B0 violates PCI spec for size of IO bar this is corrected
119 // in subsequent version of the hardware so we can safely use the
120 // else condition below.
121 this_controller->smu_registers = (SMU_REGISTERS_T *)
122 (scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0) + 0x100);
126 this_controller->smu_registers = (SMU_REGISTERS_T *)
127 scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR1);
131 // No need to get the bar. We will be using the offset to write to
132 // input/output ports via 0xA0 and 0xA4.
133 this_controller->scu_registers = (SCU_REGISTERS_T *) 0;
135 #endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
137 #endif // ARLINGTON_BUILD
140 #if defined(ENABLE_PCI_IO_SPACE_ACCESS) && !defined(ARLINGTON_BUILD)
143 * @brief This method will read from PCI memory for the SMU register
144 * space via IO space access.
146 * @param[in] controller The controller for which to read a DWORD.
147 * @param[in] address This parameter depicts the address from
150 * @return The value being returned from the PCI memory location.
152 * @todo This PCI memory access calls likely need to be optimized into macro?
154 U32 scic_sds_pci_read_smu_dword(
155 SCI_CONTROLLER_HANDLE_T controller,
159 return scic_cb_pci_read_dword(controller, address);
163 * @brief This method will write to PCI memory for the SMU register
164 * space via IO space access.
166 * @param[in] controller The controller for which to read a DWORD.
167 * @param[in] address This parameter depicts the address into
169 * @param[out] write_value This parameter depicts the value being written
170 * into the PCI memory location.
172 * @todo This PCI memory access calls likely need to be optimized into macro?
174 void scic_sds_pci_write_smu_dword(
175 SCI_CONTROLLER_HANDLE_T controller,
180 scic_cb_pci_write_dword(controller, address, write_value);
184 * @brief This method will read from PCI memory for the SCU register
185 * space via IO space access.
187 * @param[in] controller The controller for which to read a DWORD.
188 * @param[in] address This parameter depicts the address from
191 * @return The value being returned from the PCI memory location.
193 * @todo This PCI memory access calls likely need to be optimized into macro?
195 U32 scic_sds_pci_read_scu_dword(
196 SCI_CONTROLLER_HANDLE_T controller,
200 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
202 scic_cb_pci_write_dword(
204 (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET),
208 return scic_cb_pci_read_dword(
210 (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET)
215 * @brief This method will write to PCI memory for the SCU register
216 * space via IO space access.
218 * @param[in] controller The controller for which to read a DWORD.
219 * @param[in] address This parameter depicts the address into
221 * @param[out] write_value This parameter depicts the value being written
222 * into the PCI memory location.
224 * @todo This PCI memory access calls likely need to be optimized into macro?
226 void scic_sds_pci_write_scu_dword(
227 SCI_CONTROLLER_HANDLE_T controller,
232 SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
234 scic_cb_pci_write_dword(
236 (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET),
240 scic_cb_pci_write_dword(
242 (void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET),
247 #endif // defined(ENABLE_PCI_IO_SPACE_ACCESS)