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54 #ifndef _SCIC_SDS_PCI_H_
55 #define _SCIC_SDS_PCI_H_
60 * @brief This file contains the prototypes/macros utilized in writing
61 * out PCI data for the SCI core.
68 #include <dev/isci/scil/sci_types.h>
70 #define PATSBURG_SMU_BAR 0
71 #define PATSBURG_SCU_BAR 1
72 #define PATSBURG_IO_SPACE_BAR0 2
73 #define PATSBURG_IO_SPACE_BAR1 3
75 #define SCIC_SDS_PCI_REVISION_A0 0
76 #define SCIC_SDS_PCI_REVISION_A2 2
77 #define SCIC_SDS_PCI_REVISION_B0 4
78 #define SCIC_SDS_PCI_REVISION_C0 5
79 #define SCIC_SDS_PCI_REVISION_C1 6
81 enum SCU_CONTROLLER_PCI_REVISION_CODE
83 SCU_PBG_HBA_REV_A0 = SCIC_SDS_PCI_REVISION_A0,
84 SCU_PBG_HBA_REV_A2 = SCIC_SDS_PCI_REVISION_A2,
85 SCU_PBG_HBA_REV_B0 = SCIC_SDS_PCI_REVISION_B0,
86 SCU_PBG_HBA_REV_C0 = SCIC_SDS_PCI_REVISION_C0,
87 SCU_PBG_HBA_REV_C1 = SCIC_SDS_PCI_REVISION_C1
90 struct SCIC_SDS_CONTROLLER;
92 void scic_sds_pci_bar_initialization(
93 struct SCIC_SDS_CONTROLLER * this_controller
96 #if !defined(ENABLE_PCI_IO_SPACE_ACCESS) || defined(ARLINGTON_BUILD)
98 #define scic_sds_pci_read_smu_dword scic_cb_pci_read_dword
99 #define scic_sds_pci_write_smu_dword scic_cb_pci_write_dword
100 #define scic_sds_pci_read_scu_dword scic_cb_pci_read_dword
101 #define scic_sds_pci_write_scu_dword scic_cb_pci_write_dword
103 #else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
105 // These two registers form the Data/Index pair equivalent in the
106 // SCU. They are only used for access registers in BAR 1, not BAR 0.
107 #define SCU_MMR_ADDRESS_WINDOW_OFFSET 0xA0
108 #define SCU_MMR_DATA_WINDOW_OFFSET 0xA4
110 U32 scic_sds_pci_read_smu_dword(
111 SCI_CONTROLLER_HANDLE_T controller,
115 void scic_sds_pci_write_smu_dword(
116 SCI_CONTROLLER_HANDLE_T controller,
121 U32 scic_sds_pci_read_scu_dword(
122 SCI_CONTROLLER_HANDLE_T controller,
126 void scic_sds_pci_write_scu_dword(
127 SCI_CONTROLLER_HANDLE_T controller,
132 #endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
136 #endif // __cplusplus
138 #endif // _SCIC_SDS_PCI_H_