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56 #ifndef _SCIC_SDS_PCI_H_
57 #define _SCIC_SDS_PCI_H_
62 * @brief This file contains the prototypes/macros utilized in writing
63 * out PCI data for the SCI core.
70 #include <dev/isci/scil/sci_types.h>
72 #define PATSBURG_SMU_BAR 0
73 #define PATSBURG_SCU_BAR 1
74 #define PATSBURG_IO_SPACE_BAR0 2
75 #define PATSBURG_IO_SPACE_BAR1 3
77 #define SCIC_SDS_PCI_REVISION_A0 0
78 #define SCIC_SDS_PCI_REVISION_A2 2
79 #define SCIC_SDS_PCI_REVISION_B0 4
80 #define SCIC_SDS_PCI_REVISION_C0 5
81 #define SCIC_SDS_PCI_REVISION_C1 6
83 enum SCU_CONTROLLER_PCI_REVISION_CODE
85 SCU_PBG_HBA_REV_A0 = SCIC_SDS_PCI_REVISION_A0,
86 SCU_PBG_HBA_REV_A2 = SCIC_SDS_PCI_REVISION_A2,
87 SCU_PBG_HBA_REV_B0 = SCIC_SDS_PCI_REVISION_B0,
88 SCU_PBG_HBA_REV_C0 = SCIC_SDS_PCI_REVISION_C0,
89 SCU_PBG_HBA_REV_C1 = SCIC_SDS_PCI_REVISION_C1
92 struct SCIC_SDS_CONTROLLER;
94 void scic_sds_pci_bar_initialization(
95 struct SCIC_SDS_CONTROLLER * this_controller
98 #if !defined(ENABLE_PCI_IO_SPACE_ACCESS) || defined(ARLINGTON_BUILD)
100 #define scic_sds_pci_read_smu_dword scic_cb_pci_read_dword
101 #define scic_sds_pci_write_smu_dword scic_cb_pci_write_dword
102 #define scic_sds_pci_read_scu_dword scic_cb_pci_read_dword
103 #define scic_sds_pci_write_scu_dword scic_cb_pci_write_dword
105 #else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
107 // These two registers form the Data/Index pair equivalent in the
108 // SCU. They are only used for access registers in BAR 1, not BAR 0.
109 #define SCU_MMR_ADDRESS_WINDOW_OFFSET 0xA0
110 #define SCU_MMR_DATA_WINDOW_OFFSET 0xA4
112 U32 scic_sds_pci_read_smu_dword(
113 SCI_CONTROLLER_HANDLE_T controller,
117 void scic_sds_pci_write_smu_dword(
118 SCI_CONTROLLER_HANDLE_T controller,
123 U32 scic_sds_pci_read_scu_dword(
124 SCI_CONTROLLER_HANDLE_T controller,
128 void scic_sds_pci_write_scu_dword(
129 SCI_CONTROLLER_HANDLE_T controller,
134 #endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
138 #endif // __cplusplus
140 #endif // _SCIC_SDS_PCI_H_