2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 #ifndef _SCIC_SDS_PHY_REGISTERS_H_
55 #define _SCIC_SDS_PHY_REGISTERS_H_
60 * @brief This file contains the macros used by the phy object to read/write
61 * to the SCU link layer registers.
68 #include <dev/isci/scil/scic_sds_controller.h>
70 //*****************************************************************************
71 //* SCU LINK LAYER REGISTER OPERATIONS
72 //*****************************************************************************
75 * Macro to read the transport layer register associated with this phy
78 #define scu_transport_layer_read(phy, reg) \
80 scic_sds_phy_get_controller(phy), \
81 (phy)->transport_layer_registers->reg \
85 * Macro to write the transport layer register associated with this phy
88 #define scu_transport_layer_write(phy, reg, value) \
90 scic_sds_phy_get_controller(phy), \
91 (phy)->transport_layer_registers->reg, \
95 //****************************************************************************
96 //* Transport Layer registers controlled by the phy object
97 //****************************************************************************
100 * This macro reads the Transport layer control register
102 #define SCU_TLCR_READ(phy) \
103 scu_transport_layer_read(phy, control)
106 * This macro writes the Transport layer control register
108 #define SCU_TLCR_WRITE(phy, value) \
109 scu_transport_layer_write(phy, control, value)
112 * This macro reads the Transport layer address translation register
114 #define SCU_TLADTR_READ(phy) \
115 scu_transport_layer_read(phy, address_translation)
118 * This macro writes the Transport layer address translation register
120 #define SCU_TLADTR_WRITE(phy) \
121 scu_transport_layer_write(phy, address_translation, value)
124 * This macro writes the STP Transport Layer Direct Attached RNi register.
126 #define SCU_STPTLDARNI_WRITE(phy, index) \
127 scu_transport_layer_write(phy, stp_rni, index)
130 * This macro reads the STP Transport Layer Direct Attached RNi register.
132 #define SCU_STPTLDARNI_READ(phy) \
133 scu_transport_layer_read(phy, stp_rni)
135 //*****************************************************************************
136 //* SCU LINK LAYER REGISTER OPERATIONS
137 //*****************************************************************************
140 * THis macro requests the SCU register write for the specified link layer
143 #define scu_link_layer_register_read(phy, reg) \
145 scic_sds_phy_get_controller(phy), \
146 (phy)->link_layer_registers->reg \
150 * This macro requests the SCU register read for the specified link layer
153 #define scu_link_layer_register_write(phy, reg, value) \
154 scu_register_write( \
155 scic_sds_phy_get_controller(phy), \
156 (phy)->link_layer_registers->reg, \
160 //*****************************************************************************
161 //* SCU LINK LAYER REGISTERS
162 //*****************************************************************************
164 /// This macro reads from the SAS Identify Frame PHY Identifier register
165 #define SCU_SAS_TIPID_READ(phy) \
166 scu_link_layer_register_read(phy, identify_frame_phy_id)
168 /// This macro writes to the SAS Identify Frame PHY Identifier register
169 #define SCU_SAS_TIPID_WRITE(phy, value) \
170 scu_link_layer_register_write(phy, identify_frame_phy_id, value)
172 /// This macro reads from the SAS Identification register
173 #define SCU_SAS_TIID_READ(phy) \
174 scu_link_layer_register_read(phy, transmit_identification)
176 /// This macro writes to the SAS Identification register
177 #define SCU_SAS_TIID_WRITE(phy, value) \
178 scu_link_layer_register_write(phy, transmit_identification, value)
180 /// This macro reads the SAS Device Name High register
181 #define SCU_SAS_TIDNH_READ(phy) \
182 scu_link_layer_register_read(phy, sas_device_name_high)
184 /// This macro writes the SAS Device Name High register
185 #define SCU_SAS_TIDNH_WRITE(phy, value) \
186 scu_link_layer_register_write(phy, sas_device_name_high, value)
188 /// This macro reads the SAS Device Name Low register
189 #define SCU_SAS_TIDNL_READ(phy) \
190 scu_link_layer_register_read(phy, sas_device_name_low)
192 /// This macro writes the SAS Device Name Low register
193 #define SCU_SAS_TIDNL_WRITE(phy, value) \
194 scu_link_layer_register_write(phy, sas_device_name_low, value)
196 /// This macro reads the Source SAS Address High register
197 #define SCU_SAS_TISSAH_READ(phy) \
198 scu_link_layer_register_read(phy, source_sas_address_high)
200 /// This macro writes the Source SAS Address High register
201 #define SCU_SAS_TISSAH_WRITE(phy, value) \
202 scu_link_layer_register_write(phy, source_sas_address_high, value)
204 /// This macro reads the Source SAS Address Low register
205 #define SCU_SAS_TISSAL_READ(phy) \
206 scu_link_layer_register_read(phy, source_sas_address_low)
208 /// This macro writes the Source SAS Address Low register
209 #define SCU_SAS_TISSAL_WRITE(phy, value) \
210 scu_link_layer_register_write(phy, source_sas_address_low, value)
212 /// This macro reads the PHY Configuration register
213 #define SCU_SAS_PCFG_READ(phy) \
214 scu_link_layer_register_read(phy, phy_configuration);
216 /// This macro writes the PHY Configuration register
217 #define SCU_SAS_PCFG_WRITE(phy, value) \
218 scu_link_layer_register_write(phy, phy_configuration, value)
220 /// This macro reads the PHY Enable Spinup register
221 #define SCU_SAS_ENSPINUP_READ(phy) \
222 scu_link_layer_register_read(phy, notify_enable_spinup_control)
224 /// This macro writes the PHY Enable Spinup register
225 #define SCU_SAS_ENSPINUP_WRITE(phy, value) \
226 scu_link_layer_register_write(phy, notify_enable_spinup_control, value)
228 /// This macro reads the CLKSM register
229 #define SCU_SAS_CLKSM_READ(phy) \
230 scu_link_layer_register_read(phy, clock_skew_management)
232 /// This macro writes the CLKSM register
233 #define SCU_SAS_CLKSM_WRITE(phy, value) \
234 scu_link_layer_register_write(phy, clock_skew_management, value)
236 /// This macro reads the PHY Capacity register
237 #define SCU_SAS_PHYCAP_READ(phy) \
238 scu_link_layer_register_read(phy, phy_capabilities)
240 /// This macro writes the PHY Capacity register
241 #define SCU_SAS_PHYCAP_WRITE(phy, value) \
242 scu_link_layer_register_write(phy, phy_capabilities, value)
244 /// This macro reads the Recieved PHY Capacity register
245 #define SCU_SAS_RECPHYCAP_READ(phy) \
246 scu_link_layer_register_read(phy, receive_phycap)
248 /// This macro reads the link layer control register
249 #define SCU_SAS_LLCTL_READ(phy) \
250 scu_link_layer_register_read(phy, link_layer_control);
252 /// This macro writes the link layer control register
253 #define SCU_SAS_LLCTL_WRITE(phy, value) \
254 scu_link_layer_register_write(phy, link_layer_control, value);
256 /// This macro reads the link layer status register
257 #define SCU_SAS_LLSTA_READ(phy) \
258 scu_link_layer_register_read(phy, link_layer_status);
260 #define SCU_SAS_ECENCR_READ(phy) \
261 scu_link_layer_register_read(phy, error_counter_event_notification_control)
263 #define SCU_SAS_ECENCR_WRITE(phy, value) \
264 scu_link_layer_register_write(phy, error_counter_event_notification_control, value)
268 #endif // __cplusplus
270 #endif // _SCIC_SDS_PHY_REGISTERS_H_