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54 #ifndef _SCU_BIOS_DEFINITIONS_H_
55 #define _SCU_BIOS_DEFINITIONS_H_
63 * This file can be used by an SCI Library based driver or
64 * stand-alone where the library is excluded. By excluding
65 * the SCI Library, inclusion of OS specific header files can
66 * be avoided. For example, a BIOS utility probably does not
67 * want to be bothered with inclusion of nested OS DDK include
68 * files that are not necessary for its function.
70 * To exclude the SCI Library, either uncomment the EXCLUDE_SCI_LIBRARY
71 * #define statement in environment.h or define the statement as an input
75 #include <dev/isci/environment.h>
77 #ifndef EXCLUDE_SCI_LIBRARY
78 #include <dev/isci/scil/sci_types.h>
79 #include <dev/isci/scil/intel_sas.h>
80 #include <dev/isci/scil/sci_controller_constants.h>
81 #endif /* EXCLUDE_SCI_LIBRARY */
85 // For Intel Storage Controller Unit OEM Block
86 #define SCI_OEM_PARAM_SIGNATURE "ISCUOEMB"
88 #define SCI_PREBOOT_SOURCE_INIT (0x00)
89 #define SCI_PREBOOT_SOURCE_OROM (0x80)
90 #define SCI_PREBOOT_SOURCE_EFI (0x81)
92 #define SCI_OEM_PARAM_VER_1_0 (0x10)
93 #define SCI_OEM_PARAM_VER_1_1 (0x11)
94 #define SCI_OEM_PARAM_VER_1_2 (0x12)
95 #define SCI_OEM_PARAM_VER_1_3 (0x13)
98 #define SCI_OEM_PARAM_VER_CUR SCI_OEM_PARAM_VER_1_3
100 // port configuration mode
101 #define SCI_BIOS_MODE_MPC (0x00)
102 #define SCI_BIOS_MODE_APC (0x01)
106 #define SCI_MAX_PHYS (4)
109 #ifndef SCI_MAX_PORTS
110 #define SCI_MAX_PORTS (4)
115 * @struct SCI_BIOS_OEM_PARAM_BLOCK_HDR
117 * @brief This structure defines the OEM Parameter block header.
119 typedef struct SCI_BIOS_OEM_PARAM_BLOCK_HDR
122 * This field contains the OEM Parameter Block Signature which is
123 * used by BIOS and driver software to identify that the memory location
124 * contains valid OEM Parameter data. The value must be set to
125 * SCI_OEM_PARAM_SIGNATURE which is the string "ISCUOEMB" which
126 * stands for Intel Storage Controller Unit OEM Block.
130 * This field contains the size in bytes of the complete OEM
131 * Parameter Block, both header and payload hdr_length +
132 * (num_elements * element_length).
134 U16 total_block_length;
136 * This field contains the size in bytes of the
137 * SCI_BIOS_OEM_PARAM_BLOCK_HDR. It also indicates the offset from
138 * the beginning of this data structure to where the actual
139 * parameter data payload begins.
143 * This field contains the version info defining the structure
144 * of the OEM Parameter block.
148 * This field contains a value indicating the preboot initialization
149 * method (Option ROM or UEFI driver) so that after OS transition,
150 * the OS driver can know the preboot method. OEMs who build a single
151 * flash image where the preboot method is unknown at manufacturing
152 * time should set this field to SCI_PREBOOT_SOURCE_INIT. Then
153 * after the block is retrieved into host memory and under preboot
154 * driver control, the OROM or UEFI driver can set this field
155 * appropriately (SCI_PREBOOT_SOURCE_OROM and SCI_PREBOOT_SOURCE_EFI,
160 * This field contains the number of parameter descriptor elements
161 * (i.e. controller_elements) following this header. The number of
162 * elements corresponds to the number of SCU controller units contained
164 * controller_element[0] = SCU0
165 * controller_element[1] = SCU1
169 * This field contains the size in bytes of the descriptor element(s)
174 * Reserve fields for future use.
178 } SCI_BIOS_OEM_PARAM_BLOCK_HDR_T;
182 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.0
184 * @brief This structure delineates the various OEM parameters that must
185 * be set for the Intel SAS Storage Controller Unit (SCU).
187 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT
190 * Per SCU Controller Data
195 * This field indicates the port configuration mode for
197 * Automatic Port Configuration(APC) or
198 * Manual Port Configuration (MPC).
200 * APC means the Platform OEM expects SCI to configure
201 * SAS Ports automatically according to the discovered SAS
202 * Address pairs of the endpoints, wide and/or narrow.
204 * MPC means the Platform OEM manually defines wide or narrow
205 * connectors by apriori assigning PHYs to SAS Ports.
207 * By default, the mode type is APC
208 * in APC mode, if ANY of the phy mask is non-zero,
209 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
210 * from scic_oem_parameters_set AND the default oem
211 * configuration will be applied
212 * in MPC mode, if ALL of the phy masks are zero,
213 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
214 * from scic_oem_parameters_set AND the default oem
215 * configuration will be applied
220 * This field specifies the maximum number of direct attached
221 * devices the OEM will allow to have powered up simultaneously
222 * on this controller. This allows the OEM to avoid exceeding
223 * power supply limits for this platform. A value of zero
224 * indicates there are no restrictions.
226 U8 max_number_concurrent_device_spin_up;
229 * This field indicates OEM's desired default
230 * Spread Spectrum Clocking (SSC) setting for Tx:
246 * This field specifies the phys to be contained inside a port.
247 * The bit position in the mask specifies the index of the phy
248 * to be contained in the port. Multiple bits (i.e. phys)
249 * can be contained in a single port:
250 * Bit 0 = This controller's PHY index 0 (0x01)
251 * Bit 1 = This controller's PHY index 1 (0x02)
252 * Bit 2 = This controller's PHY index 2 (0x04)
253 * Bit 3 = This controller's PHY index 3 (0x08)
255 * Refer to the mode_type field for rules regarding APC and MPC mode.
256 * General rule: For APC mode phy_mask = 0
260 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
263 * Per PHY Parameter data.
268 * This field indicates the SAS Address that will be transmitted on
269 * this PHY index. The field is defined as a union, however, the
270 * OEM should use the U8 array definition when encoding it to ensure
271 * correct byte ordering.
273 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
274 * SAS Addresses for all PHYs within a controller group SHALL be the
280 * The array should be stored in little endian order. For example,
281 * if the desired SAS Address is 0x50010B90_0003538D, then it
282 * should be stored in the following manner:
294 * This is the typedef'd version of the SAS Address used in
297 SCI_SAS_ADDRESS_T sci_format;
302 * These are the per PHY equalization settings associated with the
303 * AFE XCVR Tx Amplitude and Equalization Control Register Set
306 * Operational Note: The following Look-Up-Table registers are engaged
307 * by the AFE block after the following:
308 * - Software programs the Link Layer AFE Look Up Table Control
309 * Registers (AFE_LUTCR).
310 * - Software sets AFE XCVR Tx Control Register Tx Equalization
314 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
315 * LUTSel=00b. It contains the Tx Equalization settings that will be
316 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
318 U32 afe_tx_amp_control0;
321 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
322 * LUTSel=01b. It contains the Tx Equalization settings that will
323 * be used if a SATA 6.0Gbs device is direct-attached.
325 U32 afe_tx_amp_control1;
328 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
329 * LUTSel=10b. It contains the Tx Equalization settings that will
330 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
332 U32 afe_tx_amp_control2;
335 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
336 * LUTSel=11b. It contains the Tx Equalization settings that will
337 * be used if a SAS 6.0Gbs device is direct-attached.
339 U32 afe_tx_amp_control3;
341 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
343 } SCI_BIOS_OEM_PARAM_ELEMENT_T;
346 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.1
348 * @brief This structure delineates the various OEM parameters that must
349 * be set for the Intel SAS Storage Controller Unit (SCU).
351 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1
354 * Per SCU Controller Data
359 * This field indicates the port configuration mode for
361 * Automatic Port Configuration(APC) or
362 * Manual Port Configuration (MPC).
364 * APC means the Platform OEM expects SCI to configure
365 * SAS Ports automatically according to the discovered SAS
366 * Address pairs of the endpoints, wide and/or narrow.
368 * MPC means the Platform OEM manually defines wide or narrow
369 * connectors by apriori assigning PHYs to SAS Ports.
371 * By default, the mode type is APC
372 * in APC mode, if ANY of the phy mask is non-zero,
373 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
374 * from scic_oem_parameters_set AND the default oem
375 * configuration will be applied
376 * in MPC mode, if ALL of the phy masks are zero,
377 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
378 * from scic_oem_parameters_set AND the default oem
379 * configuration will be applied
384 * This field specifies the maximum number of direct attached
385 * devices the OEM will allow to have powered up simultaneously
386 * on this controller. This allows the OEM to avoid exceeding
387 * power supply limits for this platform. A value of zero
388 * indicates there are no restrictions.
390 U8 max_number_concurrent_device_spin_up;
393 * This bitfield indicates the OEM's desired default Tx
394 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
395 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
396 *--------------------------------------------------------------------*/
398 * NOTE: Max spread for SATA is +0 / -5000 PPM.
399 * Down-spreading SSC (only method allowed for SATA):
400 * SATA SSC Tx Disabled = 0x0
401 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
402 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
403 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
404 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
406 U8 ssc_sata_tx_spread_level : 4;
409 * SAS SSC Tx Disabled = 0x0
411 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
412 * Down-spreading SSC:
413 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
414 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
416 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
417 * Center-spreading SSC:
418 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
419 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
421 U8 ssc_sas_tx_spread_level : 3;
423 * NOTE: Refer to the SSC section of the SAS 2.x Specification
424 * for proper setting of this field. For standard SAS Initiator
425 * SAS PHY operation it should be 0 for Down-spreading.
426 * SAS SSC Tx spread type:
427 * Down-spreading SSC = 0
428 * Center-spreading SSC = 1
430 U8 ssc_sas_tx_type : 1;
431 /*--------------------------------------------------------------------*/
443 * This field specifies the phys to be contained inside a port.
444 * The bit position in the mask specifies the index of the phy
445 * to be contained in the port. Multiple bits (i.e. phys)
446 * can be contained in a single port:
447 * Bit 0 = This controller's PHY index 0 (0x01)
448 * Bit 1 = This controller's PHY index 1 (0x02)
449 * Bit 2 = This controller's PHY index 2 (0x04)
450 * Bit 3 = This controller's PHY index 3 (0x08)
452 * Refer to the mode_type field for rules regarding APC and MPC mode.
453 * General rule: For APC mode phy_mask = 0
457 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
460 * Per PHY Parameter data.
465 * This field indicates the SAS Address that will be transmitted on
466 * this PHY index. The field is defined as a union, however, the
467 * OEM should use the U8 array definition when encoding it to ensure
468 * correct byte ordering.
470 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
471 * SAS Addresses for all PHYs within a controller group SHALL be the
477 * The array should be stored in little endian order. For example,
478 * if the desired SAS Address is 0x50010B90_0003538D, then it
479 * should be stored in the following manner:
491 * This is the typedef'd version of the SAS Address used in
494 SCI_SAS_ADDRESS_T sci_format;
499 * These are the per PHY equalization settings associated with the
500 * AFE XCVR Tx Amplitude and Equalization Control Register Set
503 * Operational Note: The following Look-Up-Table registers are engaged
504 * by the AFE block after the following:
505 * - Software programs the Link Layer AFE Look Up Table Control
506 * Registers (AFE_LUTCR).
507 * - Software sets AFE XCVR Tx Control Register Tx Equalization
511 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
512 * LUTSel=00b. It contains the Tx Equalization settings that will be
513 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
515 U32 afe_tx_amp_control0;
518 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
519 * LUTSel=01b. It contains the Tx Equalization settings that will
520 * be used if a SATA 6.0Gbs device is direct-attached.
522 U32 afe_tx_amp_control1;
525 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
526 * LUTSel=10b. It contains the Tx Equalization settings that will
527 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
529 U32 afe_tx_amp_control2;
532 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
533 * LUTSel=11b. It contains the Tx Equalization settings that will
534 * be used if a SAS 6.0Gbs device is direct-attached.
536 U32 afe_tx_amp_control3;
538 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
540 } SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1_T;
543 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.2
545 * @brief This structure delineates the various OEM parameters that must
546 * be set for the Intel SAS Storage Controller Unit (SCU).
548 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2
551 * Per SCU Controller Data
556 * This field indicates the port configuration mode for
558 * Automatic Port Configuration(APC) or
559 * Manual Port Configuration (MPC).
561 * APC means the Platform OEM expects SCI to configure
562 * SAS Ports automatically according to the discovered SAS
563 * Address pairs of the endpoints, wide and/or narrow.
565 * MPC means the Platform OEM manually defines wide or narrow
566 * connectors by apriori assigning PHYs to SAS Ports.
568 * By default, the mode type is APC
569 * in APC mode, if ANY of the phy mask is non-zero,
570 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
571 * from scic_oem_parameters_set AND the default oem
572 * configuration will be applied
573 * in MPC mode, if ALL of the phy masks are zero,
574 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
575 * from scic_oem_parameters_set AND the default oem
576 * configuration will be applied
581 * This field specifies the maximum number of direct attached
582 * devices the OEM will allow to have powered up simultaneously
583 * on this controller. This allows the OEM to avoid exceeding
584 * power supply limits for this platform. A value of zero
585 * indicates there are no restrictions.
587 U8 max_number_concurrent_device_spin_up;
590 * This bitfield indicates the OEM's desired default Tx
591 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
592 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
593 *--------------------------------------------------------------------*/
595 * NOTE: Max spread for SATA is +0 / -5000 PPM.
596 * Down-spreading SSC (only method allowed for SATA):
597 * SATA SSC Tx Disabled = 0x0
598 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
599 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
600 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
601 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
603 U8 ssc_sata_tx_spread_level : 4;
606 * SAS SSC Tx Disabled = 0x0
608 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
609 * Down-spreading SSC:
610 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
611 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
613 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
614 * Center-spreading SSC:
615 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
616 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
618 U8 ssc_sas_tx_spread_level : 3;
620 * NOTE: Refer to the SSC section of the SAS 2.x Specification
621 * for proper setting of this field. For standard SAS Initiator
622 * SAS PHY operation it should be 0 for Down-spreading.
623 * SAS SSC Tx spread type:
624 * Down-spreading SSC = 0
625 * Center-spreading SSC = 1
627 U8 ssc_sas_tx_type : 1;
630 * This field indicates length of the SAS/SATA cable between
632 * This field is used make relationship between analog parameters of
633 * the phy in the silicon and length of the cable.
634 * Supported length: "short"- up to 3m, "long"- more than 3m
635 * This is bit mask field:
637 * BIT: 7 6 5 4 3 2 1 0 (LSB)
638 * ASSIGNMENT: <-><-><-><-><phy3><phy2><phy1><phy0>
640 * For short cable corresponding bit shall be reset,
641 * for long cable shall be set.
643 U8 long_cable_selection_mask;
653 * This field specifies the phys to be contained inside a port.
654 * The bit position in the mask specifies the index of the phy
655 * to be contained in the port. Multiple bits (i.e. phys)
656 * can be contained in a single port:
657 * Bit 0 = This controller's PHY index 0 (0x01)
658 * Bit 1 = This controller's PHY index 1 (0x02)
659 * Bit 2 = This controller's PHY index 2 (0x04)
660 * Bit 3 = This controller's PHY index 3 (0x08)
662 * Refer to the mode_type field for rules regarding APC and MPC mode.
663 * General rule: For APC mode phy_mask = 0
667 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
670 * Per PHY Parameter data.
675 * This field indicates the SAS Address that will be transmitted on
676 * this PHY index. The field is defined as a union, however, the
677 * OEM should use the U8 array definition when encoding it to ensure
678 * correct byte ordering.
680 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
681 * SAS Addresses for all PHYs within a controller group SHALL be the
687 * The array should be stored in little endian order. For example,
688 * if the desired SAS Address is 0x50010B90_0003538D, then it
689 * should be stored in the following manner:
701 * This is the typedef'd version of the SAS Address used in
704 SCI_SAS_ADDRESS_T sci_format;
709 * These are the per PHY equalization settings associated with the
710 * AFE XCVR Tx Amplitude and Equalization Control Register Set
713 * Operational Note: The following Look-Up-Table registers are engaged
714 * by the AFE block after the following:
715 * - Software programs the Link Layer AFE Look Up Table Control
716 * Registers (AFE_LUTCR).
717 * - Software sets AFE XCVR Tx Control Register Tx Equalization
721 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
722 * LUTSel=00b. It contains the Tx Equalization settings that will be
723 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
725 U32 afe_tx_amp_control0;
728 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
729 * LUTSel=01b. It contains the Tx Equalization settings that will
730 * be used if a SATA 6.0Gbs device is direct-attached.
732 U32 afe_tx_amp_control1;
735 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
736 * LUTSel=10b. It contains the Tx Equalization settings that will
737 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
739 U32 afe_tx_amp_control2;
742 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
743 * LUTSel=11b. It contains the Tx Equalization settings that will
744 * be used if a SAS 6.0Gbs device is direct-attached.
746 U32 afe_tx_amp_control3;
748 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
750 } SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2_T;
753 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.3
755 * @brief This structure delineates the various OEM parameters that must
756 * be set for the Intel SAS Storage Controller Unit (SCU).
758 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3
761 * Per SCU Controller Data
766 * This field indicates the port configuration mode for
768 * Automatic Port Configuration(APC) or
769 * Manual Port Configuration (MPC).
771 * APC means the Platform OEM expects SCI to configure
772 * SAS Ports automatically according to the discovered SAS
773 * Address pairs of the endpoints, wide and/or narrow.
775 * MPC means the Platform OEM manually defines wide or narrow
776 * connectors by apriori assigning PHYs to SAS Ports.
778 * By default, the mode type is APC
779 * in APC mode, if ANY of the phy mask is non-zero,
780 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
781 * from scic_oem_parameters_set AND the default oem
782 * configuration will be applied
783 * in MPC mode, if ALL of the phy masks are zero,
784 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
785 * from scic_oem_parameters_set AND the default oem
786 * configuration will be applied
791 * This field specifies the maximum number of direct attached
792 * devices the OEM will allow to have powered up simultaneously
793 * on this controller. This allows the OEM to avoid exceeding
794 * power supply limits for this platform. A value of zero
795 * indicates there are no restrictions.
797 U8 max_number_concurrent_device_spin_up;
800 * This bitfield indicates the OEM's desired default Tx
801 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
802 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
803 *--------------------------------------------------------------------*/
805 * NOTE: Max spread for SATA is +0 / -5000 PPM.
806 * Down-spreading SSC (only method allowed for SATA):
807 * SATA SSC Tx Disabled = 0x0
808 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
809 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
810 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
811 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
813 U8 ssc_sata_tx_spread_level : 4;
816 * SAS SSC Tx Disabled = 0x0
818 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
819 * Down-spreading SSC:
820 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
821 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
823 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
824 * Center-spreading SSC:
825 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
826 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
828 U8 ssc_sas_tx_spread_level : 3;
830 * NOTE: Refer to the SSC section of the SAS 2.x Specification
831 * for proper setting of this field. For standard SAS Initiator
832 * SAS PHY operation it should be 0 for Down-spreading.
833 * SAS SSC Tx spread type:
834 * Down-spreading SSC = 0
835 * Center-spreading SSC = 1
837 U8 ssc_sas_tx_type : 1;
840 * This field indicates length of the SAS/SATA cable between
842 * This field is used make relationship between analog parameters of
843 * the phy in the silicon and length of the cable.
844 * Supported cable attenuation levels:
845 * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 6m
846 * This is bit mask field:
849 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable length assignment
851 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length assignment
853 * BITS 7-4 are set when the cable length is assigned to medium
854 * BITS 3-0 are set when the cable length is assigned to long
855 * The BIT positions are clear when the cable length is assigned to short
856 * Setting the bits for both long and medium cable length is undefined.
858 * A value of 0x84 would assign
864 U8 cable_selection_mask;
874 * This field specifies the phys to be contained inside a port.
875 * The bit position in the mask specifies the index of the phy
876 * to be contained in the port. Multiple bits (i.e. phys)
877 * can be contained in a single port:
878 * Bit 0 = This controller's PHY index 0 (0x01)
879 * Bit 1 = This controller's PHY index 1 (0x02)
880 * Bit 2 = This controller's PHY index 2 (0x04)
881 * Bit 3 = This controller's PHY index 3 (0x08)
883 * Refer to the mode_type field for rules regarding APC and MPC mode.
884 * General rule: For APC mode phy_mask = 0
888 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
891 * Per PHY Parameter data.
896 * This field indicates the SAS Address that will be transmitted on
897 * this PHY index. The field is defined as a union, however, the
898 * OEM should use the U8 array definition when encoding it to ensure
899 * correct byte ordering.
901 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
902 * SAS Addresses for all PHYs within a controller group SHALL be the
908 * The array should be stored in little endian order. For example,
909 * if the desired SAS Address is 0x50010B90_0003538D, then it
910 * should be stored in the following manner:
922 * This is the typedef'd version of the SAS Address used in
925 SCI_SAS_ADDRESS_T sci_format;
930 * These are the per PHY equalization settings associated with the
931 * AFE XCVR Tx Amplitude and Equalization Control Register Set
934 * Operational Note: The following Look-Up-Table registers are engaged
935 * by the AFE block after the following:
936 * - Software programs the Link Layer AFE Look Up Table Control
937 * Registers (AFE_LUTCR).
938 * - Software sets AFE XCVR Tx Control Register Tx Equalization
942 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
943 * LUTSel=00b. It contains the Tx Equalization settings that will be
944 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
946 U32 afe_tx_amp_control0;
949 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
950 * LUTSel=01b. It contains the Tx Equalization settings that will
951 * be used if a SATA 6.0Gbs device is direct-attached.
953 U32 afe_tx_amp_control1;
956 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
957 * LUTSel=10b. It contains the Tx Equalization settings that will
958 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
960 U32 afe_tx_amp_control2;
963 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
964 * LUTSel=11b. It contains the Tx Equalization settings that will
965 * be used if a SAS 6.0Gbs device is direct-attached.
967 U32 afe_tx_amp_control3;
969 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
971 } SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3_T;
974 * @struct SCI_BIOS_OEM_PARAM_BLOCK
976 * @brief This structure defines the OEM Parameter block as it will be stored
977 * in the last 512 bytes of the PDR region in the SPI flash. It must be
978 * unpacked or pack(1).
980 typedef struct SCI_BIOS_OEM_PARAM_BLOCK
983 * OEM Parameter Block header.
985 SCI_BIOS_OEM_PARAM_BLOCK_HDR_T header;
988 * Per controller element descriptor containing the controller's
989 * parameter data. The prototype defines just one of these descriptors,
990 * however, the actual runtime number is determined by the num_elements
991 * field in the header.
993 SCI_BIOS_OEM_PARAM_ELEMENT_T controller_element[1];
995 } SCI_BIOS_OEM_PARAM_BLOCK_T;
999 #endif // __cplusplus
1001 #endif // _SCU_BIOS_DEFINITIONS_H_