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56 #ifndef _SCU_BIOS_DEFINITIONS_H_
57 #define _SCU_BIOS_DEFINITIONS_H_
65 * This file can be used by an SCI Library based driver or
66 * stand-alone where the library is excluded. By excluding
67 * the SCI Library, inclusion of OS specific header files can
68 * be avoided. For example, a BIOS utility probably does not
69 * want to be bothered with inclusion of nested OS DDK include
70 * files that are not necessary for its function.
72 * To exclude the SCI Library, either uncomment the EXCLUDE_SCI_LIBRARY
73 * #define statement in environment.h or define the statement as an input
77 #include <dev/isci/environment.h>
79 #ifndef EXCLUDE_SCI_LIBRARY
80 #include <dev/isci/scil/sci_types.h>
81 #include <dev/isci/scil/intel_sas.h>
82 #include <dev/isci/scil/sci_controller_constants.h>
83 #endif /* EXCLUDE_SCI_LIBRARY */
87 // For Intel Storage Controller Unit OEM Block
88 #define SCI_OEM_PARAM_SIGNATURE "ISCUOEMB"
90 #define SCI_PREBOOT_SOURCE_INIT (0x00)
91 #define SCI_PREBOOT_SOURCE_OROM (0x80)
92 #define SCI_PREBOOT_SOURCE_EFI (0x81)
94 #define SCI_OEM_PARAM_VER_1_0 (0x10)
95 #define SCI_OEM_PARAM_VER_1_1 (0x11)
96 #define SCI_OEM_PARAM_VER_1_2 (0x12)
97 #define SCI_OEM_PARAM_VER_1_3 (0x13)
100 #define SCI_OEM_PARAM_VER_CUR SCI_OEM_PARAM_VER_1_3
102 // port configuration mode
103 #define SCI_BIOS_MODE_MPC (0x00)
104 #define SCI_BIOS_MODE_APC (0x01)
108 #define SCI_MAX_PHYS (4)
111 #ifndef SCI_MAX_PORTS
112 #define SCI_MAX_PORTS (4)
117 * @struct SCI_BIOS_OEM_PARAM_BLOCK_HDR
119 * @brief This structure defines the OEM Parameter block header.
121 typedef struct SCI_BIOS_OEM_PARAM_BLOCK_HDR
124 * This field contains the OEM Parameter Block Signature which is
125 * used by BIOS and driver software to identify that the memory location
126 * contains valid OEM Parameter data. The value must be set to
127 * SCI_OEM_PARAM_SIGNATURE which is the string "ISCUOEMB" which
128 * stands for Intel Storage Controller Unit OEM Block.
132 * This field contains the size in bytes of the complete OEM
133 * Parameter Block, both header and payload hdr_length +
134 * (num_elements * element_length).
136 U16 total_block_length;
138 * This field contains the size in bytes of the
139 * SCI_BIOS_OEM_PARAM_BLOCK_HDR. It also indicates the offset from
140 * the beginning of this data structure to where the actual
141 * parameter data payload begins.
145 * This field contains the version info defining the structure
146 * of the OEM Parameter block.
150 * This field contains a value indicating the preboot initialization
151 * method (Option ROM or UEFI driver) so that after OS transition,
152 * the OS driver can know the preboot method. OEMs who build a single
153 * flash image where the preboot method is unknown at manufacturing
154 * time should set this field to SCI_PREBOOT_SOURCE_INIT. Then
155 * after the block is retrieved into host memory and under preboot
156 * driver control, the OROM or UEFI driver can set this field
157 * appropriately (SCI_PREBOOT_SOURCE_OROM and SCI_PREBOOT_SOURCE_EFI,
162 * This field contains the number of parameter descriptor elements
163 * (i.e. controller_elements) following this header. The number of
164 * elements corresponds to the number of SCU controller units contained
166 * controller_element[0] = SCU0
167 * controller_element[1] = SCU1
171 * This field contains the size in bytes of the descriptor element(s)
176 * Reserve fields for future use.
180 } SCI_BIOS_OEM_PARAM_BLOCK_HDR_T;
184 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.0
186 * @brief This structure delineates the various OEM parameters that must
187 * be set for the Intel SAS Storage Controller Unit (SCU).
189 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT
192 * Per SCU Controller Data
197 * This field indicates the port configuration mode for
199 * Automatic Port Configuration(APC) or
200 * Manual Port Configuration (MPC).
202 * APC means the Platform OEM expects SCI to configure
203 * SAS Ports automatically according to the discovered SAS
204 * Address pairs of the endpoints, wide and/or narrow.
206 * MPC means the Platform OEM manually defines wide or narrow
207 * connectors by apriori assigning PHYs to SAS Ports.
209 * By default, the mode type is APC
210 * in APC mode, if ANY of the phy mask is non-zero,
211 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
212 * from scic_oem_parameters_set AND the default oem
213 * configuration will be applied
214 * in MPC mode, if ALL of the phy masks are zero,
215 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
216 * from scic_oem_parameters_set AND the default oem
217 * configuration will be applied
222 * This field specifies the maximum number of direct attached
223 * devices the OEM will allow to have powered up simultaneously
224 * on this controller. This allows the OEM to avoid exceeding
225 * power supply limits for this platform. A value of zero
226 * indicates there are no restrictions.
228 U8 max_number_concurrent_device_spin_up;
231 * This field indicates OEM's desired default
232 * Spread Spectrum Clocking (SSC) setting for Tx:
248 * This field specifies the phys to be contained inside a port.
249 * The bit position in the mask specifies the index of the phy
250 * to be contained in the port. Multiple bits (i.e. phys)
251 * can be contained in a single port:
252 * Bit 0 = This controller's PHY index 0 (0x01)
253 * Bit 1 = This controller's PHY index 1 (0x02)
254 * Bit 2 = This controller's PHY index 2 (0x04)
255 * Bit 3 = This controller's PHY index 3 (0x08)
257 * Refer to the mode_type field for rules regarding APC and MPC mode.
258 * General rule: For APC mode phy_mask = 0
262 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
265 * Per PHY Parameter data.
270 * This field indicates the SAS Address that will be transmitted on
271 * this PHY index. The field is defined as a union, however, the
272 * OEM should use the U8 array definition when encoding it to ensure
273 * correct byte ordering.
275 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
276 * SAS Addresses for all PHYs within a controller group SHALL be the
282 * The array should be stored in little endian order. For example,
283 * if the desired SAS Address is 0x50010B90_0003538D, then it
284 * should be stored in the following manner:
296 * This is the typedef'd version of the SAS Address used in
299 SCI_SAS_ADDRESS_T sci_format;
304 * These are the per PHY equalization settings associated with the
305 * AFE XCVR Tx Amplitude and Equalization Control Register Set
308 * Operational Note: The following Look-Up-Table registers are engaged
309 * by the AFE block after the following:
310 * - Software programs the Link Layer AFE Look Up Table Control
311 * Registers (AFE_LUTCR).
312 * - Software sets AFE XCVR Tx Control Register Tx Equalization
316 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
317 * LUTSel=00b. It contains the Tx Equalization settings that will be
318 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
320 U32 afe_tx_amp_control0;
323 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
324 * LUTSel=01b. It contains the Tx Equalization settings that will
325 * be used if a SATA 6.0Gbs device is direct-attached.
327 U32 afe_tx_amp_control1;
330 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
331 * LUTSel=10b. It contains the Tx Equalization settings that will
332 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
334 U32 afe_tx_amp_control2;
337 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
338 * LUTSel=11b. It contains the Tx Equalization settings that will
339 * be used if a SAS 6.0Gbs device is direct-attached.
341 U32 afe_tx_amp_control3;
343 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
345 } SCI_BIOS_OEM_PARAM_ELEMENT_T;
348 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.1
350 * @brief This structure delineates the various OEM parameters that must
351 * be set for the Intel SAS Storage Controller Unit (SCU).
353 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1
356 * Per SCU Controller Data
361 * This field indicates the port configuration mode for
363 * Automatic Port Configuration(APC) or
364 * Manual Port Configuration (MPC).
366 * APC means the Platform OEM expects SCI to configure
367 * SAS Ports automatically according to the discovered SAS
368 * Address pairs of the endpoints, wide and/or narrow.
370 * MPC means the Platform OEM manually defines wide or narrow
371 * connectors by apriori assigning PHYs to SAS Ports.
373 * By default, the mode type is APC
374 * in APC mode, if ANY of the phy mask is non-zero,
375 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
376 * from scic_oem_parameters_set AND the default oem
377 * configuration will be applied
378 * in MPC mode, if ALL of the phy masks are zero,
379 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
380 * from scic_oem_parameters_set AND the default oem
381 * configuration will be applied
386 * This field specifies the maximum number of direct attached
387 * devices the OEM will allow to have powered up simultaneously
388 * on this controller. This allows the OEM to avoid exceeding
389 * power supply limits for this platform. A value of zero
390 * indicates there are no restrictions.
392 U8 max_number_concurrent_device_spin_up;
395 * This bitfield indicates the OEM's desired default Tx
396 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
397 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
398 *--------------------------------------------------------------------*/
400 * NOTE: Max spread for SATA is +0 / -5000 PPM.
401 * Down-spreading SSC (only method allowed for SATA):
402 * SATA SSC Tx Disabled = 0x0
403 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
404 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
405 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
406 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
408 U8 ssc_sata_tx_spread_level : 4;
411 * SAS SSC Tx Disabled = 0x0
413 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
414 * Down-spreading SSC:
415 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
416 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
418 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
419 * Center-spreading SSC:
420 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
421 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
423 U8 ssc_sas_tx_spread_level : 3;
425 * NOTE: Refer to the SSC section of the SAS 2.x Specification
426 * for proper setting of this field. For standard SAS Initiator
427 * SAS PHY operation it should be 0 for Down-spreading.
428 * SAS SSC Tx spread type:
429 * Down-spreading SSC = 0
430 * Center-spreading SSC = 1
432 U8 ssc_sas_tx_type : 1;
433 /*--------------------------------------------------------------------*/
445 * This field specifies the phys to be contained inside a port.
446 * The bit position in the mask specifies the index of the phy
447 * to be contained in the port. Multiple bits (i.e. phys)
448 * can be contained in a single port:
449 * Bit 0 = This controller's PHY index 0 (0x01)
450 * Bit 1 = This controller's PHY index 1 (0x02)
451 * Bit 2 = This controller's PHY index 2 (0x04)
452 * Bit 3 = This controller's PHY index 3 (0x08)
454 * Refer to the mode_type field for rules regarding APC and MPC mode.
455 * General rule: For APC mode phy_mask = 0
459 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
462 * Per PHY Parameter data.
467 * This field indicates the SAS Address that will be transmitted on
468 * this PHY index. The field is defined as a union, however, the
469 * OEM should use the U8 array definition when encoding it to ensure
470 * correct byte ordering.
472 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
473 * SAS Addresses for all PHYs within a controller group SHALL be the
479 * The array should be stored in little endian order. For example,
480 * if the desired SAS Address is 0x50010B90_0003538D, then it
481 * should be stored in the following manner:
493 * This is the typedef'd version of the SAS Address used in
496 SCI_SAS_ADDRESS_T sci_format;
501 * These are the per PHY equalization settings associated with the
502 * AFE XCVR Tx Amplitude and Equalization Control Register Set
505 * Operational Note: The following Look-Up-Table registers are engaged
506 * by the AFE block after the following:
507 * - Software programs the Link Layer AFE Look Up Table Control
508 * Registers (AFE_LUTCR).
509 * - Software sets AFE XCVR Tx Control Register Tx Equalization
513 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
514 * LUTSel=00b. It contains the Tx Equalization settings that will be
515 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
517 U32 afe_tx_amp_control0;
520 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
521 * LUTSel=01b. It contains the Tx Equalization settings that will
522 * be used if a SATA 6.0Gbs device is direct-attached.
524 U32 afe_tx_amp_control1;
527 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
528 * LUTSel=10b. It contains the Tx Equalization settings that will
529 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
531 U32 afe_tx_amp_control2;
534 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
535 * LUTSel=11b. It contains the Tx Equalization settings that will
536 * be used if a SAS 6.0Gbs device is direct-attached.
538 U32 afe_tx_amp_control3;
540 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
542 } SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1_T;
545 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.2
547 * @brief This structure delineates the various OEM parameters that must
548 * be set for the Intel SAS Storage Controller Unit (SCU).
550 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2
553 * Per SCU Controller Data
558 * This field indicates the port configuration mode for
560 * Automatic Port Configuration(APC) or
561 * Manual Port Configuration (MPC).
563 * APC means the Platform OEM expects SCI to configure
564 * SAS Ports automatically according to the discovered SAS
565 * Address pairs of the endpoints, wide and/or narrow.
567 * MPC means the Platform OEM manually defines wide or narrow
568 * connectors by apriori assigning PHYs to SAS Ports.
570 * By default, the mode type is APC
571 * in APC mode, if ANY of the phy mask is non-zero,
572 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
573 * from scic_oem_parameters_set AND the default oem
574 * configuration will be applied
575 * in MPC mode, if ALL of the phy masks are zero,
576 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
577 * from scic_oem_parameters_set AND the default oem
578 * configuration will be applied
583 * This field specifies the maximum number of direct attached
584 * devices the OEM will allow to have powered up simultaneously
585 * on this controller. This allows the OEM to avoid exceeding
586 * power supply limits for this platform. A value of zero
587 * indicates there are no restrictions.
589 U8 max_number_concurrent_device_spin_up;
592 * This bitfield indicates the OEM's desired default Tx
593 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
594 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
595 *--------------------------------------------------------------------*/
597 * NOTE: Max spread for SATA is +0 / -5000 PPM.
598 * Down-spreading SSC (only method allowed for SATA):
599 * SATA SSC Tx Disabled = 0x0
600 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
601 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
602 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
603 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
605 U8 ssc_sata_tx_spread_level : 4;
608 * SAS SSC Tx Disabled = 0x0
610 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
611 * Down-spreading SSC:
612 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
613 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
615 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
616 * Center-spreading SSC:
617 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
618 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
620 U8 ssc_sas_tx_spread_level : 3;
622 * NOTE: Refer to the SSC section of the SAS 2.x Specification
623 * for proper setting of this field. For standard SAS Initiator
624 * SAS PHY operation it should be 0 for Down-spreading.
625 * SAS SSC Tx spread type:
626 * Down-spreading SSC = 0
627 * Center-spreading SSC = 1
629 U8 ssc_sas_tx_type : 1;
632 * This field indicates length of the SAS/SATA cable between
634 * This field is used make relationship between analog parameters of
635 * the phy in the silicon and length of the cable.
636 * Supported length: "short"- up to 3m, "long"- more than 3m
637 * This is bit mask field:
639 * BIT: 7 6 5 4 3 2 1 0 (LSB)
640 * ASSIGNMENT: <-><-><-><-><phy3><phy2><phy1><phy0>
642 * For short cable corresponding bit shall be reset,
643 * for long cable shall be set.
645 U8 long_cable_selection_mask;
655 * This field specifies the phys to be contained inside a port.
656 * The bit position in the mask specifies the index of the phy
657 * to be contained in the port. Multiple bits (i.e. phys)
658 * can be contained in a single port:
659 * Bit 0 = This controller's PHY index 0 (0x01)
660 * Bit 1 = This controller's PHY index 1 (0x02)
661 * Bit 2 = This controller's PHY index 2 (0x04)
662 * Bit 3 = This controller's PHY index 3 (0x08)
664 * Refer to the mode_type field for rules regarding APC and MPC mode.
665 * General rule: For APC mode phy_mask = 0
669 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
672 * Per PHY Parameter data.
677 * This field indicates the SAS Address that will be transmitted on
678 * this PHY index. The field is defined as a union, however, the
679 * OEM should use the U8 array definition when encoding it to ensure
680 * correct byte ordering.
682 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
683 * SAS Addresses for all PHYs within a controller group SHALL be the
689 * The array should be stored in little endian order. For example,
690 * if the desired SAS Address is 0x50010B90_0003538D, then it
691 * should be stored in the following manner:
703 * This is the typedef'd version of the SAS Address used in
706 SCI_SAS_ADDRESS_T sci_format;
711 * These are the per PHY equalization settings associated with the
712 * AFE XCVR Tx Amplitude and Equalization Control Register Set
715 * Operational Note: The following Look-Up-Table registers are engaged
716 * by the AFE block after the following:
717 * - Software programs the Link Layer AFE Look Up Table Control
718 * Registers (AFE_LUTCR).
719 * - Software sets AFE XCVR Tx Control Register Tx Equalization
723 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
724 * LUTSel=00b. It contains the Tx Equalization settings that will be
725 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
727 U32 afe_tx_amp_control0;
730 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
731 * LUTSel=01b. It contains the Tx Equalization settings that will
732 * be used if a SATA 6.0Gbs device is direct-attached.
734 U32 afe_tx_amp_control1;
737 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
738 * LUTSel=10b. It contains the Tx Equalization settings that will
739 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
741 U32 afe_tx_amp_control2;
744 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
745 * LUTSel=11b. It contains the Tx Equalization settings that will
746 * be used if a SAS 6.0Gbs device is direct-attached.
748 U32 afe_tx_amp_control3;
750 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
752 } SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2_T;
755 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.3
757 * @brief This structure delineates the various OEM parameters that must
758 * be set for the Intel SAS Storage Controller Unit (SCU).
760 typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3
763 * Per SCU Controller Data
768 * This field indicates the port configuration mode for
770 * Automatic Port Configuration(APC) or
771 * Manual Port Configuration (MPC).
773 * APC means the Platform OEM expects SCI to configure
774 * SAS Ports automatically according to the discovered SAS
775 * Address pairs of the endpoints, wide and/or narrow.
777 * MPC means the Platform OEM manually defines wide or narrow
778 * connectors by apriori assigning PHYs to SAS Ports.
780 * By default, the mode type is APC
781 * in APC mode, if ANY of the phy mask is non-zero,
782 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
783 * from scic_oem_parameters_set AND the default oem
784 * configuration will be applied
785 * in MPC mode, if ALL of the phy masks are zero,
786 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned
787 * from scic_oem_parameters_set AND the default oem
788 * configuration will be applied
793 * This field specifies the maximum number of direct attached
794 * devices the OEM will allow to have powered up simultaneously
795 * on this controller. This allows the OEM to avoid exceeding
796 * power supply limits for this platform. A value of zero
797 * indicates there are no restrictions.
799 U8 max_number_concurrent_device_spin_up;
802 * This bitfield indicates the OEM's desired default Tx
803 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
804 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
805 *--------------------------------------------------------------------*/
807 * NOTE: Max spread for SATA is +0 / -5000 PPM.
808 * Down-spreading SSC (only method allowed for SATA):
809 * SATA SSC Tx Disabled = 0x0
810 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
811 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
812 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
813 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
815 U8 ssc_sata_tx_spread_level : 4;
818 * SAS SSC Tx Disabled = 0x0
820 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM
821 * Down-spreading SSC:
822 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
823 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
825 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM
826 * Center-spreading SSC:
827 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3
828 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6
830 U8 ssc_sas_tx_spread_level : 3;
832 * NOTE: Refer to the SSC section of the SAS 2.x Specification
833 * for proper setting of this field. For standard SAS Initiator
834 * SAS PHY operation it should be 0 for Down-spreading.
835 * SAS SSC Tx spread type:
836 * Down-spreading SSC = 0
837 * Center-spreading SSC = 1
839 U8 ssc_sas_tx_type : 1;
842 * This field indicates length of the SAS/SATA cable between
844 * This field is used make relationship between analog parameters of
845 * the phy in the silicon and length of the cable.
846 * Supported cable attenuation levels:
847 * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 6m
848 * This is bit mask field:
851 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable length assignment
853 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length assignment
855 * BITS 7-4 are set when the cable length is assigned to medium
856 * BITS 3-0 are set when the cable length is assigned to long
857 * The BIT positions are clear when the cable length is assigned to short
858 * Setting the bits for both long and medium cable length is undefined.
860 * A value of 0x84 would assign
866 U8 cable_selection_mask;
876 * This field specifies the phys to be contained inside a port.
877 * The bit position in the mask specifies the index of the phy
878 * to be contained in the port. Multiple bits (i.e. phys)
879 * can be contained in a single port:
880 * Bit 0 = This controller's PHY index 0 (0x01)
881 * Bit 1 = This controller's PHY index 1 (0x02)
882 * Bit 2 = This controller's PHY index 2 (0x04)
883 * Bit 3 = This controller's PHY index 3 (0x08)
885 * Refer to the mode_type field for rules regarding APC and MPC mode.
886 * General rule: For APC mode phy_mask = 0
890 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit
893 * Per PHY Parameter data.
898 * This field indicates the SAS Address that will be transmitted on
899 * this PHY index. The field is defined as a union, however, the
900 * OEM should use the U8 array definition when encoding it to ensure
901 * correct byte ordering.
903 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the
904 * SAS Addresses for all PHYs within a controller group SHALL be the
910 * The array should be stored in little endian order. For example,
911 * if the desired SAS Address is 0x50010B90_0003538D, then it
912 * should be stored in the following manner:
924 * This is the typedef'd version of the SAS Address used in
927 SCI_SAS_ADDRESS_T sci_format;
932 * These are the per PHY equalization settings associated with the
933 * AFE XCVR Tx Amplitude and Equalization Control Register Set
936 * Operational Note: The following Look-Up-Table registers are engaged
937 * by the AFE block after the following:
938 * - Software programs the Link Layer AFE Look Up Table Control
939 * Registers (AFE_LUTCR).
940 * - Software sets AFE XCVR Tx Control Register Tx Equalization
944 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR
945 * LUTSel=00b. It contains the Tx Equalization settings that will be
946 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached.
948 U32 afe_tx_amp_control0;
951 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR
952 * LUTSel=01b. It contains the Tx Equalization settings that will
953 * be used if a SATA 6.0Gbs device is direct-attached.
955 U32 afe_tx_amp_control1;
958 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR
959 * LUTSel=10b. It contains the Tx Equalization settings that will
960 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached.
962 U32 afe_tx_amp_control2;
965 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR
966 * LUTSel=11b. It contains the Tx Equalization settings that will
967 * be used if a SAS 6.0Gbs device is direct-attached.
969 U32 afe_tx_amp_control3;
971 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit
973 } SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3_T;
976 * @struct SCI_BIOS_OEM_PARAM_BLOCK
978 * @brief This structure defines the OEM Parameter block as it will be stored
979 * in the last 512 bytes of the PDR region in the SPI flash. It must be
980 * unpacked or pack(1).
982 typedef struct SCI_BIOS_OEM_PARAM_BLOCK
985 * OEM Parameter Block header.
987 SCI_BIOS_OEM_PARAM_BLOCK_HDR_T header;
990 * Per controller element descriptor containing the controller's
991 * parameter data. The prototype defines just one of these descriptors,
992 * however, the actual runtime number is determined by the num_elements
993 * field in the header.
995 SCI_BIOS_OEM_PARAM_ELEMENT_T controller_element[1];
997 } SCI_BIOS_OEM_PARAM_BLOCK_T;
1001 #endif // __cplusplus
1003 #endif // _SCU_BIOS_DEFINITIONS_H_