2 * Copyright (C) 2014 Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of Intel Corporation nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/errno.h>
37 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/priority.h>
42 #include <sys/syslog.h>
44 #include <machine/bus.h>
46 #include <machine/resource.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/smbus/smbconf.h>
54 #define ISMT_DESC_ENTRIES 32
56 /* Hardware Descriptor Constants - Control Field */
57 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
58 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
59 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
60 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
61 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
62 #define ISMT_DESC_INT 0x40 /* Interrupt */
63 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
65 /* Hardware Descriptor Constants - Status Field */
66 #define ISMT_DESC_SCS 0x01 /* Success */
67 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
68 #define ISMT_DESC_NAK 0x08 /* NAK Received */
69 #define ISMT_DESC_CRC 0x10 /* CRC Error */
70 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
71 #define ISMT_DESC_COL 0x40 /* Collisions */
72 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
75 #define ISMT_DESC_ADDR_RW(addr, is_read) ((addr) | (is_read))
77 /* iSMT General Register address offsets (SMBBAR + <addr>) */
78 #define ISMT_GR_GCTRL 0x000 /* General Control */
79 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
80 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
81 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
82 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
83 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
85 /* iSMT Master Registers */
86 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
87 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
88 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
89 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
90 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
92 /* iSMT Miscellaneous Registers */
93 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
95 /* General Control Register (GCTRL) bit definitions */
96 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
97 #define ISMT_GCTRL_KILL 0x08 /* Kill */
98 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
100 /* Master Control Register (MCTRL) bit definitions */
101 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
102 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
103 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
105 /* Master Status Register (MSTS) bit definitions */
106 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
107 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
108 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
109 #define ISMT_MSTS_IP 0x01 /* In Progress */
111 /* Master Descriptor Size (MDS) bit definitions */
112 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
114 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
115 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
116 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
117 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
118 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
119 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
121 /* MSI Control Register (MSICTL) bit definitions */
122 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
124 #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */
126 //#define ISMT_DEBUG device_printf
128 #define ISMT_DEBUG(...)
131 /* iSMT Hardware Descriptor */
133 uint8_t tgtaddr_rw; /* target address & r/w bit */
134 uint8_t wr_len_cmd; /* write length in bytes or a command */
135 uint8_t rd_len; /* read length */
136 uint8_t control; /* control bits */
137 uint8_t status; /* status bits */
138 uint8_t retry; /* collision retry and retry count */
139 uint8_t rxbytes; /* received bytes */
140 uint8_t txbytes; /* transmitted bytes */
141 uint32_t dptr_low; /* lower 32 bit of the data pointer */
142 uint32_t dptr_high; /* upper 32 bit of the data pointer */
145 #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc))
147 #define DMA_BUFFER_SIZE 64
153 struct thread *bus_reserved;
156 struct resource *intr_res;
159 bus_space_tag_t mmio_tag;
160 bus_space_handle_t mmio_handle;
162 struct resource *mmio_res;
166 struct ismt_desc *desc;
167 bus_dma_tag_t desc_dma_tag;
168 bus_dmamap_t desc_dma_map;
169 uint64_t desc_bus_addr;
172 bus_dma_tag_t dma_buffer_dma_tag;
173 bus_dmamap_t dma_buffer_dma_map;
174 uint64_t dma_buffer_bus_addr;
182 struct ismt_softc *sc = arg;
185 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MSTS);
186 ISMT_DEBUG(sc->pcidev, "%s MSTS=0x%x\n", __func__, val);
188 val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS);
189 bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, val);
195 ismt_callback(device_t dev, int index, void *data)
197 struct ismt_softc *sc;
200 sc = device_get_softc(dev);
203 case SMB_REQUEST_BUS:
204 acquired = atomic_cmpset_ptr(
205 (uintptr_t *)&sc->bus_reserved,
206 (uintptr_t)NULL, (uintptr_t)curthread);
207 ISMT_DEBUG(dev, "SMB_REQUEST_BUS acquired=%d\n", acquired);
213 case SMB_RELEASE_BUS:
214 KASSERT(sc->bus_reserved == curthread,
215 ("SMB_RELEASE_BUS called by wrong thread\n"));
216 ISMT_DEBUG(dev, "SMB_RELEASE_BUS\n");
217 atomic_store_rel_ptr((uintptr_t *)&sc->bus_reserved,
229 static struct ismt_desc *
230 ismt_alloc_desc(struct ismt_softc *sc)
232 struct ismt_desc *desc;
234 KASSERT(sc->bus_reserved == curthread,
235 ("curthread %p did not request bus (%p has reserved)\n",
236 curthread, sc->bus_reserved));
238 desc = &sc->desc[sc->head++];
239 if (sc->head == ISMT_DESC_ENTRIES)
242 memset(desc, 0, sizeof(*desc));
248 ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, uint8_t slave,
251 uint32_t err, fmhp, val;
253 desc->control |= ISMT_DESC_FAIR;
255 desc->control |= ISMT_DESC_INT;
257 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read);
258 desc->dptr_low = (sc->dma_buffer_bus_addr & 0xFFFFFFFFLL);
259 desc->dptr_high = (sc->dma_buffer_bus_addr >> 32);
263 fmhp = sc->head << 16;
264 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL);
265 val &= ~ISMT_MCTRL_FMHP;
267 bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val);
269 /* set the start bit */
270 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL);
271 val |= ISMT_MCTRL_SS;
272 bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val);
274 err = tsleep(sc, PWAIT, "ismt_wait", 5 * hz);
277 ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__);
278 return (SMB_ETIMEOUT);
281 ISMT_DEBUG(sc->pcidev, "%s status=0x%x\n", __func__, desc->status);
283 if (desc->status & ISMT_DESC_SCS)
286 if (desc->status & ISMT_DESC_NAK)
289 if (desc->status & ISMT_DESC_CRC)
290 return (SMB_EBUSERR);
292 if (desc->status & ISMT_DESC_COL)
295 if (desc->status & ISMT_DESC_LPR)
298 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
299 return (SMB_ETIMEOUT);
301 return (SMB_EBUSERR);
306 ismt_quick(device_t dev, u_char slave, int how)
308 struct ismt_desc *desc;
309 struct ismt_softc *sc;
312 ISMT_DEBUG(dev, "%s\n", __func__);
314 if (how != SMB_QREAD && how != SMB_QWRITE) {
315 return (SMB_ENOTSUPP);
318 sc = device_get_softc(dev);
319 desc = ismt_alloc_desc(sc);
320 is_read = (how == SMB_QREAD ? 1 : 0);
321 return (ismt_submit(sc, desc, slave, is_read));
325 ismt_sendb(device_t dev, u_char slave, char byte)
327 struct ismt_desc *desc;
328 struct ismt_softc *sc;
330 ISMT_DEBUG(dev, "%s\n", __func__);
332 sc = device_get_softc(dev);
333 desc = ismt_alloc_desc(sc);
334 desc->control = ISMT_DESC_CWRL;
335 desc->wr_len_cmd = byte;
337 return (ismt_submit(sc, desc, slave, 0));
341 ismt_recvb(device_t dev, u_char slave, char *byte)
343 struct ismt_desc *desc;
344 struct ismt_softc *sc;
347 ISMT_DEBUG(dev, "%s\n", __func__);
349 sc = device_get_softc(dev);
350 desc = ismt_alloc_desc(sc);
353 err = ismt_submit(sc, desc, slave, 1);
355 if (err != SMB_ENOERR)
358 *byte = sc->dma_buffer[0];
364 ismt_writeb(device_t dev, u_char slave, char cmd, char byte)
366 struct ismt_desc *desc;
367 struct ismt_softc *sc;
369 ISMT_DEBUG(dev, "%s\n", __func__);
371 sc = device_get_softc(dev);
372 desc = ismt_alloc_desc(sc);
373 desc->wr_len_cmd = 2;
374 sc->dma_buffer[0] = cmd;
375 sc->dma_buffer[1] = byte;
377 return (ismt_submit(sc, desc, slave, 0));
381 ismt_writew(device_t dev, u_char slave, char cmd, short word)
383 struct ismt_desc *desc;
384 struct ismt_softc *sc;
386 ISMT_DEBUG(dev, "%s\n", __func__);
388 sc = device_get_softc(dev);
389 desc = ismt_alloc_desc(sc);
390 desc->wr_len_cmd = 3;
391 sc->dma_buffer[0] = cmd;
392 sc->dma_buffer[1] = word & 0xFF;
393 sc->dma_buffer[2] = word >> 8;
395 return (ismt_submit(sc, desc, slave, 0));
399 ismt_readb(device_t dev, u_char slave, char cmd, char *byte)
401 struct ismt_desc *desc;
402 struct ismt_softc *sc;
405 ISMT_DEBUG(dev, "%s\n", __func__);
407 sc = device_get_softc(dev);
408 desc = ismt_alloc_desc(sc);
409 desc->control = ISMT_DESC_CWRL;
410 desc->wr_len_cmd = cmd;
413 err = ismt_submit(sc, desc, slave, 1);
415 if (err != SMB_ENOERR)
418 *byte = sc->dma_buffer[0];
424 ismt_readw(device_t dev, u_char slave, char cmd, short *word)
426 struct ismt_desc *desc;
427 struct ismt_softc *sc;
430 ISMT_DEBUG(dev, "%s\n", __func__);
432 sc = device_get_softc(dev);
433 desc = ismt_alloc_desc(sc);
434 desc->control = ISMT_DESC_CWRL;
435 desc->wr_len_cmd = cmd;
438 err = ismt_submit(sc, desc, slave, 1);
440 if (err != SMB_ENOERR)
443 *word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8);
449 ismt_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
451 struct ismt_desc *desc;
452 struct ismt_softc *sc;
455 ISMT_DEBUG(dev, "%s\n", __func__);
457 sc = device_get_softc(dev);
458 desc = ismt_alloc_desc(sc);
459 desc->wr_len_cmd = 3;
461 sc->dma_buffer[0] = cmd;
462 sc->dma_buffer[1] = sdata & 0xff;
463 sc->dma_buffer[2] = sdata >> 8;
465 err = ismt_submit(sc, desc, slave, 0);
467 if (err != SMB_ENOERR)
470 *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8);
476 ismt_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
478 struct ismt_desc *desc;
479 struct ismt_softc *sc;
481 ISMT_DEBUG(dev, "%s\n", __func__);
483 if (count == 0 || count > ISMT_MAX_BLOCK_SIZE)
486 sc = device_get_softc(dev);
487 desc = ismt_alloc_desc(sc);
488 desc->control = ISMT_DESC_I2C;
489 desc->wr_len_cmd = count + 1;
490 sc->dma_buffer[0] = cmd;
491 memcpy(&sc->dma_buffer[1], buf, count);
493 return (ismt_submit(sc, desc, slave, 0));
497 ismt_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
499 struct ismt_desc *desc;
500 struct ismt_softc *sc;
503 ISMT_DEBUG(dev, "%s\n", __func__);
505 if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE)
508 sc = device_get_softc(dev);
509 desc = ismt_alloc_desc(sc);
510 desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL;
511 desc->wr_len_cmd = cmd;
512 desc->rd_len = *count;
514 err = ismt_submit(sc, desc, slave, 0);
516 if (err != SMB_ENOERR)
519 memcpy(buf, sc->dma_buffer, desc->rxbytes);
520 *count = desc->rxbytes;
526 ismt_detach(device_t dev)
528 struct ismt_softc *sc;
531 ISMT_DEBUG(dev, "%s\n", __func__);
532 sc = device_get_softc(dev);
534 error = bus_generic_detach(dev);
538 device_delete_child(dev, sc->smbdev);
540 if (sc->intr_handle != NULL) {
541 bus_teardown_intr(dev, sc->intr_res, sc->intr_handle);
542 sc->intr_handle = NULL;
544 if (sc->intr_res != NULL) {
545 bus_release_resource(dev,
546 SYS_RES_IRQ, sc->intr_rid, sc->intr_res);
549 if (sc->using_msi == 1)
550 pci_release_msi(dev);
552 if (sc->mmio_res != NULL) {
553 bus_release_resource(dev,
554 SYS_RES_MEMORY, sc->mmio_rid, sc->mmio_res);
558 bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map);
559 bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map);
561 bus_dmamem_free(sc->desc_dma_tag, sc->desc,
563 bus_dmamem_free(sc->dma_buffer_dma_tag, sc->dma_buffer,
564 sc->dma_buffer_dma_map);
566 bus_dma_tag_destroy(sc->desc_dma_tag);
567 bus_dma_tag_destroy(sc->dma_buffer_dma_tag);
569 pci_disable_busmaster(dev);
575 ismt_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
577 uint64_t *bus_addr = (uint64_t *)arg;
579 KASSERT(error == 0, ("%s: error=%d\n", __func__, error));
580 KASSERT(nseg == 1, ("%s: nseg=%d\n", __func__, nseg));
582 *bus_addr = seg[0].ds_addr;
586 ismt_attach(device_t dev)
588 struct ismt_softc *sc = device_get_softc(dev);
589 int err, num_vectors, val;
592 pci_enable_busmaster(dev);
594 if ((sc->smbdev = device_add_child(dev, "smbus", -1)) == NULL) {
595 device_printf(dev, "no smbus child found\n");
600 sc->mmio_rid = PCIR_BAR(0);
601 sc->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
602 &sc->mmio_rid, RF_ACTIVE);
603 if (sc->mmio_res == NULL) {
604 device_printf(dev, "cannot allocate mmio region\n");
609 sc->mmio_tag = rman_get_bustag(sc->mmio_res);
610 sc->mmio_handle = rman_get_bushandle(sc->mmio_res);
612 /* Attach "smbus" child */
613 if ((err = bus_generic_attach(dev)) != 0) {
614 device_printf(dev, "failed to attach child: %d\n", err);
619 bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE,
620 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
621 DESC_SIZE, 1, DESC_SIZE,
622 0, NULL, NULL, &sc->desc_dma_tag);
624 bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE,
625 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
626 DMA_BUFFER_SIZE, 1, DMA_BUFFER_SIZE,
627 0, NULL, NULL, &sc->dma_buffer_dma_tag);
629 bus_dmamap_create(sc->desc_dma_tag, 0,
631 bus_dmamap_create(sc->dma_buffer_dma_tag, 0,
632 &sc->dma_buffer_dma_map);
634 bus_dmamem_alloc(sc->desc_dma_tag,
635 (void **)&sc->desc, BUS_DMA_WAITOK,
637 bus_dmamem_alloc(sc->dma_buffer_dma_tag,
638 (void **)&sc->dma_buffer, BUS_DMA_WAITOK,
639 &sc->dma_buffer_dma_map);
641 bus_dmamap_load(sc->desc_dma_tag,
642 sc->desc_dma_map, sc->desc, DESC_SIZE,
643 ismt_single_map, &sc->desc_bus_addr, 0);
644 bus_dmamap_load(sc->dma_buffer_dma_tag,
645 sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE,
646 ismt_single_map, &sc->dma_buffer_bus_addr, 0);
648 bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA,
649 (sc->desc_bus_addr & 0xFFFFFFFFLL));
650 bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA + 4,
651 (sc->desc_bus_addr >> 32));
653 /* initialize the Master Control Register (MCTRL) */
654 bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, ISMT_MCTRL_MEIE);
656 /* initialize the Master Status Register (MSTS) */
657 bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, 0);
659 /* initialize the Master Descriptor Size (MDS) */
660 val = bus_read_4(sc->mmio_res, ISMT_MSTR_MDS);
661 val &= ~ISMT_MDS_MASK;
662 val |= (ISMT_DESC_ENTRIES - 1);
663 bus_write_4(sc->mmio_res, ISMT_MSTR_MDS, val);
667 if (pci_msi_count(dev) == 0) {
673 if (pci_alloc_msi(dev, &num_vectors) != 0) {
679 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
680 &sc->intr_rid, RF_ACTIVE);
682 if (sc->intr_res == NULL) {
684 pci_release_msi(dev);
688 if (sc->using_msi == 0) {
690 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
691 &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE);
692 if (sc->intr_res == NULL) {
693 device_printf(dev, "cannot allocate irq\n");
699 ISMT_DEBUG(dev, "using_msi = %d\n", sc->using_msi);
701 err = bus_setup_intr(dev, sc->intr_res,
702 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ismt_intr, sc,
705 device_printf(dev, "cannot setup interrupt\n");
717 #define ID_INTEL_S1200_SMT0 0x0c598086
718 #define ID_INTEL_S1200_SMT1 0x0c5a8086
719 #define ID_INTEL_C2000_SMT 0x1f158086
722 ismt_probe(device_t dev)
726 switch (pci_get_devid(dev)) {
727 case ID_INTEL_S1200_SMT0:
728 desc = "Atom Processor S1200 SMBus 2.0 Controller 0";
730 case ID_INTEL_S1200_SMT1:
731 desc = "Atom Processor S1200 SMBus 2.0 Controller 1";
733 case ID_INTEL_C2000_SMT:
734 desc = "Atom Processor C2000 SMBus 2.0";
740 device_set_desc(dev, desc);
741 return (BUS_PROBE_DEFAULT);
745 static device_method_t ismt_pci_methods[] = {
746 DEVMETHOD(device_probe, ismt_probe),
747 DEVMETHOD(device_attach, ismt_attach),
748 DEVMETHOD(device_detach, ismt_detach),
750 DEVMETHOD(smbus_callback, ismt_callback),
751 DEVMETHOD(smbus_quick, ismt_quick),
752 DEVMETHOD(smbus_sendb, ismt_sendb),
753 DEVMETHOD(smbus_recvb, ismt_recvb),
754 DEVMETHOD(smbus_writeb, ismt_writeb),
755 DEVMETHOD(smbus_writew, ismt_writew),
756 DEVMETHOD(smbus_readb, ismt_readb),
757 DEVMETHOD(smbus_readw, ismt_readw),
758 DEVMETHOD(smbus_pcall, ismt_pcall),
759 DEVMETHOD(smbus_bwrite, ismt_bwrite),
760 DEVMETHOD(smbus_bread, ismt_bread),
765 static driver_t ismt_pci_driver = {
768 sizeof(struct ismt_softc)
771 static devclass_t ismt_pci_devclass;
773 DRIVER_MODULE(ismt, pci, ismt_pci_driver, ismt_pci_devclass, 0, 0);
774 DRIVER_MODULE(smbus, ismt, smbus_driver, smbus_devclass, 0, 0);
776 MODULE_DEPEND(ismt, pci, 1, 1, 1);
777 MODULE_DEPEND(ismt, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
778 MODULE_VERSION(ismt, 1);