2 * Copyright (c) 1997-2008 by Matthew Jacob
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice immediately at the beginning of the file, without modification,
10 * this list of conditions, and the following disclaimer.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/linker.h>
38 #include <sys/firmware.h>
40 #include <sys/stdint.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
46 #include <sys/malloc.h>
50 #include <dev/ofw/openfirm.h>
51 #include <machine/ofw_machdep.h>
54 #include <dev/isp/isp_freebsd.h>
56 static uint32_t isp_pci_rd_reg(ispsoftc_t *, int);
57 static void isp_pci_wr_reg(ispsoftc_t *, int, uint32_t);
58 static uint32_t isp_pci_rd_reg_1080(ispsoftc_t *, int);
59 static void isp_pci_wr_reg_1080(ispsoftc_t *, int, uint32_t);
60 static uint32_t isp_pci_rd_reg_2400(ispsoftc_t *, int);
61 static void isp_pci_wr_reg_2400(ispsoftc_t *, int, uint32_t);
62 static uint32_t isp_pci_rd_reg_2600(ispsoftc_t *, int);
63 static void isp_pci_wr_reg_2600(ispsoftc_t *, int, uint32_t);
64 static int isp_pci_rd_isr(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
65 static int isp_pci_rd_isr_2300(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
66 static int isp_pci_rd_isr_2400(ispsoftc_t *, uint16_t *, uint16_t *, uint16_t *);
67 static int isp_pci_mbxdma(ispsoftc_t *);
68 static int isp_pci_dmasetup(ispsoftc_t *, XS_T *, void *);
71 static void isp_pci_reset0(ispsoftc_t *);
72 static void isp_pci_reset1(ispsoftc_t *);
73 static void isp_pci_dumpregs(ispsoftc_t *, const char *);
75 static struct ispmdvec mdvec = {
81 isp_common_dmateardown,
86 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
89 static struct ispmdvec mdvec_1080 = {
95 isp_common_dmateardown,
100 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
103 static struct ispmdvec mdvec_12160 = {
109 isp_common_dmateardown,
114 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64
117 static struct ispmdvec mdvec_2100 = {
123 isp_common_dmateardown,
129 static struct ispmdvec mdvec_2200 = {
135 isp_common_dmateardown,
141 static struct ispmdvec mdvec_2300 = {
147 isp_common_dmateardown,
153 static struct ispmdvec mdvec_2400 = {
159 isp_common_dmateardown,
165 static struct ispmdvec mdvec_2500 = {
171 isp_common_dmateardown,
177 static struct ispmdvec mdvec_2600 = {
183 isp_common_dmateardown,
189 #ifndef PCIM_CMD_INVEN
190 #define PCIM_CMD_INVEN 0x10
192 #ifndef PCIM_CMD_BUSMASTEREN
193 #define PCIM_CMD_BUSMASTEREN 0x0004
195 #ifndef PCIM_CMD_PERRESPEN
196 #define PCIM_CMD_PERRESPEN 0x0040
198 #ifndef PCIM_CMD_SEREN
199 #define PCIM_CMD_SEREN 0x0100
201 #ifndef PCIM_CMD_INTX_DISABLE
202 #define PCIM_CMD_INTX_DISABLE 0x0400
206 #define PCIR_COMMAND 0x04
209 #ifndef PCIR_CACHELNSZ
210 #define PCIR_CACHELNSZ 0x0c
213 #ifndef PCIR_LATTIMER
214 #define PCIR_LATTIMER 0x0d
218 #define PCIR_ROMADDR 0x30
221 #ifndef PCI_VENDOR_QLOGIC
222 #define PCI_VENDOR_QLOGIC 0x1077
225 #ifndef PCI_PRODUCT_QLOGIC_ISP1020
226 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
229 #ifndef PCI_PRODUCT_QLOGIC_ISP1080
230 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080
233 #ifndef PCI_PRODUCT_QLOGIC_ISP10160
234 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016
237 #ifndef PCI_PRODUCT_QLOGIC_ISP12160
238 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216
241 #ifndef PCI_PRODUCT_QLOGIC_ISP1240
242 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240
245 #ifndef PCI_PRODUCT_QLOGIC_ISP1280
246 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280
249 #ifndef PCI_PRODUCT_QLOGIC_ISP2100
250 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
253 #ifndef PCI_PRODUCT_QLOGIC_ISP2200
254 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200
257 #ifndef PCI_PRODUCT_QLOGIC_ISP2300
258 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300
261 #ifndef PCI_PRODUCT_QLOGIC_ISP2312
262 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312
265 #ifndef PCI_PRODUCT_QLOGIC_ISP2322
266 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322
269 #ifndef PCI_PRODUCT_QLOGIC_ISP2422
270 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422
273 #ifndef PCI_PRODUCT_QLOGIC_ISP2432
274 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432
277 #ifndef PCI_PRODUCT_QLOGIC_ISP2532
278 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532
281 #ifndef PCI_PRODUCT_QLOGIC_ISP6312
282 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312
285 #ifndef PCI_PRODUCT_QLOGIC_ISP6322
286 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322
289 #ifndef PCI_PRODUCT_QLOGIC_ISP5432
290 #define PCI_PRODUCT_QLOGIC_ISP5432 0x5432
293 #ifndef PCI_PRODUCT_QLOGIC_ISP2031
294 #define PCI_PRODUCT_QLOGIC_ISP2031 0x2031
297 #ifndef PCI_PRODUCT_QLOGIC_ISP8031
298 #define PCI_PRODUCT_QLOGIC_ISP8031 0x8031
301 #define PCI_QLOGIC_ISP5432 \
302 ((PCI_PRODUCT_QLOGIC_ISP5432 << 16) | PCI_VENDOR_QLOGIC)
304 #define PCI_QLOGIC_ISP1020 \
305 ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
307 #define PCI_QLOGIC_ISP1080 \
308 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC)
310 #define PCI_QLOGIC_ISP10160 \
311 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC)
313 #define PCI_QLOGIC_ISP12160 \
314 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC)
316 #define PCI_QLOGIC_ISP1240 \
317 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC)
319 #define PCI_QLOGIC_ISP1280 \
320 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC)
322 #define PCI_QLOGIC_ISP2100 \
323 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
325 #define PCI_QLOGIC_ISP2200 \
326 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC)
328 #define PCI_QLOGIC_ISP2300 \
329 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC)
331 #define PCI_QLOGIC_ISP2312 \
332 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC)
334 #define PCI_QLOGIC_ISP2322 \
335 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC)
337 #define PCI_QLOGIC_ISP2422 \
338 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC)
340 #define PCI_QLOGIC_ISP2432 \
341 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC)
343 #define PCI_QLOGIC_ISP2532 \
344 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC)
346 #define PCI_QLOGIC_ISP6312 \
347 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC)
349 #define PCI_QLOGIC_ISP6322 \
350 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC)
352 #define PCI_QLOGIC_ISP2031 \
353 ((PCI_PRODUCT_QLOGIC_ISP2031 << 16) | PCI_VENDOR_QLOGIC)
355 #define PCI_QLOGIC_ISP8031 \
356 ((PCI_PRODUCT_QLOGIC_ISP8031 << 16) | PCI_VENDOR_QLOGIC)
359 * Odd case for some AMI raid cards... We need to *not* attach to this.
361 #define AMI_RAID_SUBVENDOR_ID 0x101e
363 #define PCI_DFLT_LTNCY 0x40
364 #define PCI_DFLT_LNSZ 0x10
366 static int isp_pci_probe (device_t);
367 static int isp_pci_attach (device_t);
368 static int isp_pci_detach (device_t);
371 #define ISP_PCD(isp) ((struct isp_pcisoftc *)isp)->pci_dev
372 struct isp_pcisoftc {
375 struct resource * regs;
376 struct resource * regs1;
377 struct resource * regs2;
387 int16_t pci_poff[_NREG_BLKS];
393 static device_method_t isp_pci_methods[] = {
394 /* Device interface */
395 DEVMETHOD(device_probe, isp_pci_probe),
396 DEVMETHOD(device_attach, isp_pci_attach),
397 DEVMETHOD(device_detach, isp_pci_detach),
401 static driver_t isp_pci_driver = {
402 "isp", isp_pci_methods, sizeof (struct isp_pcisoftc)
404 static devclass_t isp_devclass;
405 DRIVER_MODULE(isp, pci, isp_pci_driver, isp_devclass, 0, 0);
406 MODULE_DEPEND(isp, cam, 1, 1, 1);
407 MODULE_DEPEND(isp, firmware, 1, 1, 1);
408 static int isp_nvports = 0;
411 isp_pci_probe(device_t dev)
413 switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) {
414 case PCI_QLOGIC_ISP1020:
415 device_set_desc(dev, "Qlogic ISP 1020/1040 PCI SCSI Adapter");
417 case PCI_QLOGIC_ISP1080:
418 device_set_desc(dev, "Qlogic ISP 1080 PCI SCSI Adapter");
420 case PCI_QLOGIC_ISP1240:
421 device_set_desc(dev, "Qlogic ISP 1240 PCI SCSI Adapter");
423 case PCI_QLOGIC_ISP1280:
424 device_set_desc(dev, "Qlogic ISP 1280 PCI SCSI Adapter");
426 case PCI_QLOGIC_ISP10160:
427 device_set_desc(dev, "Qlogic ISP 10160 PCI SCSI Adapter");
429 case PCI_QLOGIC_ISP12160:
430 if (pci_get_subvendor(dev) == AMI_RAID_SUBVENDOR_ID) {
433 device_set_desc(dev, "Qlogic ISP 12160 PCI SCSI Adapter");
435 case PCI_QLOGIC_ISP2100:
436 device_set_desc(dev, "Qlogic ISP 2100 PCI FC-AL Adapter");
438 case PCI_QLOGIC_ISP2200:
439 device_set_desc(dev, "Qlogic ISP 2200 PCI FC-AL Adapter");
441 case PCI_QLOGIC_ISP2300:
442 device_set_desc(dev, "Qlogic ISP 2300 PCI FC-AL Adapter");
444 case PCI_QLOGIC_ISP2312:
445 device_set_desc(dev, "Qlogic ISP 2312 PCI FC-AL Adapter");
447 case PCI_QLOGIC_ISP2322:
448 device_set_desc(dev, "Qlogic ISP 2322 PCI FC-AL Adapter");
450 case PCI_QLOGIC_ISP2422:
451 device_set_desc(dev, "Qlogic ISP 2422 PCI FC-AL Adapter");
453 case PCI_QLOGIC_ISP2432:
454 device_set_desc(dev, "Qlogic ISP 2432 PCI FC-AL Adapter");
456 case PCI_QLOGIC_ISP2532:
457 device_set_desc(dev, "Qlogic ISP 2532 PCI FC-AL Adapter");
459 case PCI_QLOGIC_ISP5432:
460 device_set_desc(dev, "Qlogic ISP 5432 PCI FC-AL Adapter");
462 case PCI_QLOGIC_ISP6312:
463 device_set_desc(dev, "Qlogic ISP 6312 PCI FC-AL Adapter");
465 case PCI_QLOGIC_ISP6322:
466 device_set_desc(dev, "Qlogic ISP 6322 PCI FC-AL Adapter");
468 case PCI_QLOGIC_ISP2031:
469 device_set_desc(dev, "Qlogic ISP 2031 PCI FC-AL Adapter");
471 case PCI_QLOGIC_ISP8031:
472 device_set_desc(dev, "Qlogic ISP 8031 PCI FCoE Adapter");
477 if (isp_announced == 0 && bootverbose) {
478 printf("Qlogic ISP Driver, FreeBSD Version %d.%d, "
479 "Core Version %d.%d\n",
480 ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
481 ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
485 * XXXX: Here is where we might load the f/w module
486 * XXXX: (or increase a reference count to it).
488 return (BUS_PROBE_DEFAULT);
492 isp_get_generic_options(device_t dev, ispsoftc_t *isp)
497 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "fwload_disable", &tval) == 0 && tval != 0) {
498 isp->isp_confopts |= ISP_CFG_NORELOAD;
501 if (resource_int_value(device_get_name(dev), device_get_unit(dev), "ignore_nvram", &tval) == 0 && tval != 0) {
502 isp->isp_confopts |= ISP_CFG_NONVRAM;
505 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "debug", &tval);
507 isp->isp_dblev = tval;
509 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR;
512 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO;
515 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "vports", &tval);
516 if (tval > 0 && tval <= 254) {
520 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), "quickboot_time", &tval);
521 isp_quickboot_time = tval;
525 isp_get_specific_options(device_t dev, int chan, ispsoftc_t *isp)
529 char prefix[12], name[16];
534 snprintf(prefix, sizeof(prefix), "chan%d.", chan);
535 snprintf(name, sizeof(name), "%siid", prefix);
536 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
539 ISP_FC_PC(isp, chan)->default_id = 109 - chan;
542 ISP_SPI_PC(isp, chan)->iid = OF_getscsinitid(dev);
544 ISP_SPI_PC(isp, chan)->iid = 7;
549 ISP_FC_PC(isp, chan)->default_id = tval - chan;
551 ISP_SPI_PC(isp, chan)->iid = tval;
553 isp->isp_confopts |= ISP_CFG_OWNLOOPID;
560 snprintf(name, sizeof(name), "%srole", prefix);
561 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
565 case ISP_ROLE_INITIATOR:
566 case ISP_ROLE_TARGET:
568 device_printf(dev, "Chan %d setting role to 0x%x\n", chan, tval);
576 tval = ISP_DEFAULT_ROLES;
578 ISP_FC_PC(isp, chan)->def_role = tval;
581 snprintf(name, sizeof(name), "%sfullduplex", prefix);
582 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
583 name, &tval) == 0 && tval != 0) {
584 isp->isp_confopts |= ISP_CFG_FULL_DUPLEX;
587 snprintf(name, sizeof(name), "%stopology", prefix);
588 if (resource_string_value(device_get_name(dev), device_get_unit(dev),
589 name, (const char **) &sptr) == 0 && sptr != 0) {
590 if (strcmp(sptr, "lport") == 0) {
591 isp->isp_confopts |= ISP_CFG_LPORT;
592 } else if (strcmp(sptr, "nport") == 0) {
593 isp->isp_confopts |= ISP_CFG_NPORT;
594 } else if (strcmp(sptr, "lport-only") == 0) {
595 isp->isp_confopts |= ISP_CFG_LPORT_ONLY;
596 } else if (strcmp(sptr, "nport-only") == 0) {
597 isp->isp_confopts |= ISP_CFG_NPORT_ONLY;
602 snprintf(name, sizeof(name), "%snofctape", prefix);
603 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
606 isp->isp_confopts |= ISP_CFG_NOFCTAPE;
610 snprintf(name, sizeof(name), "%sfctape", prefix);
611 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
614 isp->isp_confopts &= ~ISP_CFG_NOFCTAPE;
615 isp->isp_confopts |= ISP_CFG_FCTAPE;
620 * Because the resource_*_value functions can neither return
621 * 64 bit integer values, nor can they be directly coerced
622 * to interpret the right hand side of the assignment as
623 * you want them to interpret it, we have to force WWN
624 * hint replacement to specify WWN strings with a leading
625 * 'w' (e..g w50000000aaaa0001). Sigh.
628 snprintf(name, sizeof(name), "%sportwwn", prefix);
629 tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
630 name, (const char **) &sptr);
631 if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
633 ISP_FC_PC(isp, chan)->def_wwpn = strtouq(sptr, &eptr, 16);
634 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwpn == -1) {
635 device_printf(dev, "mangled portwwn hint '%s'\n", sptr);
636 ISP_FC_PC(isp, chan)->def_wwpn = 0;
641 snprintf(name, sizeof(name), "%snodewwn", prefix);
642 tval = resource_string_value(device_get_name(dev), device_get_unit(dev),
643 name, (const char **) &sptr);
644 if (tval == 0 && sptr != 0 && *sptr++ == 'w') {
646 ISP_FC_PC(isp, chan)->def_wwnn = strtouq(sptr, &eptr, 16);
647 if (eptr < sptr + 16 || ISP_FC_PC(isp, chan)->def_wwnn == 0) {
648 device_printf(dev, "mangled nodewwn hint '%s'\n", sptr);
649 ISP_FC_PC(isp, chan)->def_wwnn = 0;
654 snprintf(name, sizeof(name), "%sloop_down_limit", prefix);
655 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
657 if (tval >= 0 && tval < 0xffff) {
658 ISP_FC_PC(isp, chan)->loop_down_limit = tval;
660 ISP_FC_PC(isp, chan)->loop_down_limit = isp_loop_down_limit;
664 snprintf(name, sizeof(name), "%sgone_device_time", prefix);
665 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
667 if (tval >= 0 && tval < 0xffff) {
668 ISP_FC_PC(isp, chan)->gone_device_time = tval;
670 ISP_FC_PC(isp, chan)->gone_device_time = isp_gone_device_time;
675 isp_pci_attach(device_t dev)
677 int i, locksetup = 0;
678 uint32_t data, cmd, linesz, did;
679 struct isp_pcisoftc *pcs;
684 pcs = device_get_softc(dev);
686 device_printf(dev, "cannot get softc\n");
689 memset(pcs, 0, sizeof (*pcs));
695 if (sizeof (bus_addr_t) > 4)
696 isp->isp_osinfo.sixtyfourbit = 1;
699 * Get Generic Options
702 isp_get_generic_options(dev, isp);
704 linesz = PCI_DFLT_LNSZ;
705 pcs->irq = pcs->regs = pcs->regs2 = NULL;
706 pcs->rgd = pcs->rtp = pcs->iqd = 0;
709 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF;
710 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF;
711 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF;
712 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF;
713 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF;
715 switch (pci_get_devid(dev)) {
716 case PCI_QLOGIC_ISP1020:
718 isp->isp_mdvec = &mdvec;
719 isp->isp_type = ISP_HA_SCSI_UNKNOWN;
721 case PCI_QLOGIC_ISP1080:
723 isp->isp_mdvec = &mdvec_1080;
724 isp->isp_type = ISP_HA_SCSI_1080;
725 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
727 case PCI_QLOGIC_ISP1240:
729 isp->isp_mdvec = &mdvec_1080;
730 isp->isp_type = ISP_HA_SCSI_1240;
732 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
734 case PCI_QLOGIC_ISP1280:
736 isp->isp_mdvec = &mdvec_1080;
737 isp->isp_type = ISP_HA_SCSI_1280;
738 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
740 case PCI_QLOGIC_ISP10160:
742 isp->isp_mdvec = &mdvec_12160;
743 isp->isp_type = ISP_HA_SCSI_10160;
744 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
746 case PCI_QLOGIC_ISP12160:
749 isp->isp_mdvec = &mdvec_12160;
750 isp->isp_type = ISP_HA_SCSI_12160;
751 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = ISP1080_DMA_REGS_OFF;
753 case PCI_QLOGIC_ISP2100:
755 isp->isp_mdvec = &mdvec_2100;
756 isp->isp_type = ISP_HA_FC_2100;
757 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
758 if (pci_get_revid(dev) < 3) {
760 * XXX: Need to get the actual revision
761 * XXX: number of the 2100 FB. At any rate,
762 * XXX: lower cache line size for early revision
768 case PCI_QLOGIC_ISP2200:
770 isp->isp_mdvec = &mdvec_2200;
771 isp->isp_type = ISP_HA_FC_2200;
772 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2100_OFF;
774 case PCI_QLOGIC_ISP2300:
776 isp->isp_mdvec = &mdvec_2300;
777 isp->isp_type = ISP_HA_FC_2300;
778 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
780 case PCI_QLOGIC_ISP2312:
781 case PCI_QLOGIC_ISP6312:
783 isp->isp_mdvec = &mdvec_2300;
784 isp->isp_type = ISP_HA_FC_2312;
785 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
787 case PCI_QLOGIC_ISP2322:
788 case PCI_QLOGIC_ISP6322:
790 isp->isp_mdvec = &mdvec_2300;
791 isp->isp_type = ISP_HA_FC_2322;
792 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2300_OFF;
794 case PCI_QLOGIC_ISP2422:
795 case PCI_QLOGIC_ISP2432:
797 isp->isp_nchan += isp_nvports;
798 isp->isp_mdvec = &mdvec_2400;
799 isp->isp_type = ISP_HA_FC_2400;
800 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
802 case PCI_QLOGIC_ISP2532:
804 isp->isp_nchan += isp_nvports;
805 isp->isp_mdvec = &mdvec_2500;
806 isp->isp_type = ISP_HA_FC_2500;
807 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
809 case PCI_QLOGIC_ISP5432:
811 isp->isp_mdvec = &mdvec_2500;
812 isp->isp_type = ISP_HA_FC_2500;
813 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
815 case PCI_QLOGIC_ISP2031:
816 case PCI_QLOGIC_ISP8031:
818 isp->isp_nchan += isp_nvports;
819 isp->isp_mdvec = &mdvec_2600;
820 isp->isp_type = ISP_HA_FC_2600;
821 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS2400_OFF;
824 device_printf(dev, "unknown device type\n");
828 isp->isp_revision = pci_get_revid(dev);
831 pcs->rtp = SYS_RES_MEMORY;
832 pcs->rgd = PCIR_BAR(0);
833 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
835 pcs->rtp1 = SYS_RES_MEMORY;
836 pcs->rgd1 = PCIR_BAR(2);
837 pcs->regs1 = bus_alloc_resource_any(dev, pcs->rtp1, &pcs->rgd1,
839 pcs->rtp2 = SYS_RES_MEMORY;
840 pcs->rgd2 = PCIR_BAR(4);
841 pcs->regs2 = bus_alloc_resource_any(dev, pcs->rtp2, &pcs->rgd2,
844 pcs->rtp = SYS_RES_MEMORY;
845 pcs->rgd = PCIR_BAR(1);
846 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp, &pcs->rgd,
848 if (pcs->regs == NULL) {
849 pcs->rtp = SYS_RES_IOPORT;
850 pcs->rgd = PCIR_BAR(0);
851 pcs->regs = bus_alloc_resource_any(dev, pcs->rtp,
852 &pcs->rgd, RF_ACTIVE);
855 if (pcs->regs == NULL) {
856 device_printf(dev, "Unable to map any ports\n");
860 device_printf(dev, "Using %s space register mapping\n",
861 (pcs->rtp == SYS_RES_IOPORT)? "I/O" : "Memory");
863 isp->isp_regs = pcs->regs;
864 isp->isp_regs2 = pcs->regs2;
867 psize = sizeof (fcparam);
868 xsize = sizeof (struct isp_fc);
870 psize = sizeof (sdparam);
871 xsize = sizeof (struct isp_spi);
873 psize *= isp->isp_nchan;
874 xsize *= isp->isp_nchan;
875 isp->isp_param = malloc(psize, M_DEVBUF, M_NOWAIT | M_ZERO);
876 if (isp->isp_param == NULL) {
877 device_printf(dev, "cannot allocate parameter data\n");
880 isp->isp_osinfo.pc.ptr = malloc(xsize, M_DEVBUF, M_NOWAIT | M_ZERO);
881 if (isp->isp_osinfo.pc.ptr == NULL) {
882 device_printf(dev, "cannot allocate parameter data\n");
887 * Now that we know who we are (roughly) get/set specific options
889 for (i = 0; i < isp->isp_nchan; i++) {
890 isp_get_specific_options(dev, i, isp);
893 isp->isp_osinfo.fw = NULL;
894 if (isp->isp_osinfo.fw == NULL) {
895 snprintf(fwname, sizeof (fwname), "isp_%04x", did);
896 isp->isp_osinfo.fw = firmware_get(fwname);
898 if (isp->isp_osinfo.fw != NULL) {
899 isp_prt(isp, ISP_LOGCONFIG, "loaded firmware %s", fwname);
900 isp->isp_mdvec->dv_ispfw = isp->isp_osinfo.fw->data;
904 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
906 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
907 cmd |= PCIM_CMD_SEREN | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_INVEN;
908 if (IS_2300(isp)) { /* per QLogic errata */
909 cmd &= ~PCIM_CMD_INVEN;
911 if (IS_2322(isp) || pci_get_devid(dev) == PCI_QLOGIC_ISP6312) {
912 cmd &= ~PCIM_CMD_INTX_DISABLE;
915 cmd &= ~PCIM_CMD_INTX_DISABLE;
917 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
920 * Make sure the Cache Line Size register is set sensibly.
922 data = pci_read_config(dev, PCIR_CACHELNSZ, 1);
923 if (data == 0 || (linesz != PCI_DFLT_LNSZ && data != linesz)) {
924 isp_prt(isp, ISP_LOGDEBUG0, "set PCI line size to %d from %d", linesz, data);
926 pci_write_config(dev, PCIR_CACHELNSZ, data, 1);
930 * Make sure the Latency Timer is sane.
932 data = pci_read_config(dev, PCIR_LATTIMER, 1);
933 if (data < PCI_DFLT_LTNCY) {
934 data = PCI_DFLT_LTNCY;
935 isp_prt(isp, ISP_LOGDEBUG0, "set PCI latency to %d", data);
936 pci_write_config(dev, PCIR_LATTIMER, data, 1);
940 * Make sure we've disabled the ROM.
942 data = pci_read_config(dev, PCIR_ROMADDR, 4);
944 pci_write_config(dev, PCIR_ROMADDR, data, 4);
947 /* 26XX chips support only MSI-X, so start from them. */
948 pcs->msicount = imin(pci_msix_count(dev), 1);
949 if (pcs->msicount > 0 &&
950 (i = pci_alloc_msix(dev, &pcs->msicount)) == 0) {
956 if (pcs->msicount == 0 && (IS_24XX(isp) || IS_2322(isp))) {
958 * Older chips support both MSI and MSI-X, but I have
959 * feeling that older firmware may not support MSI-X,
960 * but we have no way to check the firmware flag here.
962 pcs->msicount = imin(pci_msi_count(dev), 1);
963 if (pcs->msicount > 0 &&
964 pci_alloc_msi(dev, &pcs->msicount) == 0) {
970 pcs->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &pcs->iqd, RF_ACTIVE | RF_SHAREABLE);
971 if (pcs->irq == NULL) {
972 device_printf(dev, "could not allocate interrupt\n");
976 /* Make sure the lock is set up. */
977 mtx_init(&isp->isp_osinfo.lock, "isp", NULL, MTX_DEF);
980 if (isp_setup_intr(dev, pcs->irq, ISP_IFLAGS, NULL, isp_platform_intr, isp, &pcs->ih)) {
981 device_printf(dev, "could not setup interrupt\n");
986 * Last minute checks...
988 if (IS_23XX(isp) || IS_24XX(isp)) {
989 isp->isp_port = pci_get_function(dev);
993 * Make sure we're in reset state.
996 if (isp_reinit(isp, 1) != 0) {
1001 if (isp_attach(isp)) {
1011 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1014 mtx_destroy(&isp->isp_osinfo.lock);
1017 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1019 if (pcs->msicount) {
1020 pci_release_msi(dev);
1023 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1025 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1);
1027 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
1028 if (pcs->pci_isp.isp_param) {
1029 free(pcs->pci_isp.isp_param, M_DEVBUF);
1030 pcs->pci_isp.isp_param = NULL;
1032 if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1033 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1034 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1040 isp_pci_detach(device_t dev)
1042 struct isp_pcisoftc *pcs;
1046 pcs = device_get_softc(dev);
1050 isp = (ispsoftc_t *) pcs;
1051 status = isp_detach(isp);
1057 (void) bus_teardown_intr(dev, pcs->irq, pcs->ih);
1060 mtx_destroy(&isp->isp_osinfo.lock);
1061 (void) bus_release_resource(dev, SYS_RES_IRQ, pcs->iqd, pcs->irq);
1062 if (pcs->msicount) {
1063 pci_release_msi(dev);
1065 (void) bus_release_resource(dev, pcs->rtp, pcs->rgd, pcs->regs);
1067 (void) bus_release_resource(dev, pcs->rtp1, pcs->rgd1, pcs->regs1);
1069 (void) bus_release_resource(dev, pcs->rtp2, pcs->rgd2, pcs->regs2);
1071 * XXX: THERE IS A LOT OF LEAKAGE HERE
1073 if (pcs->pci_isp.isp_param) {
1074 free(pcs->pci_isp.isp_param, M_DEVBUF);
1075 pcs->pci_isp.isp_param = NULL;
1077 if (pcs->pci_isp.isp_osinfo.pc.ptr) {
1078 free(pcs->pci_isp.isp_osinfo.pc.ptr, M_DEVBUF);
1079 pcs->pci_isp.isp_osinfo.pc.ptr = NULL;
1084 #define IspVirt2Off(a, x) \
1085 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \
1086 _BLK_REG_SHFT] + ((x) & 0xfff))
1088 #define BXR2(isp, off) bus_read_2((isp)->isp_regs, (off))
1089 #define BXW2(isp, off, v) bus_write_2((isp)->isp_regs, (off), (v))
1090 #define BXR4(isp, off) bus_read_4((isp)->isp_regs, (off))
1091 #define BXW4(isp, off, v) bus_write_4((isp)->isp_regs, (off), (v))
1092 #define B2R4(isp, off) bus_read_4((isp)->isp_regs2, (off))
1093 #define B2W4(isp, off, v) bus_write_4((isp)->isp_regs2, (off), (v))
1095 static ISP_INLINE int
1096 isp_pci_rd_debounced(ispsoftc_t *isp, int off, uint16_t *rp)
1098 uint32_t val0, val1;
1102 val0 = BXR2(isp, IspVirt2Off(isp, off));
1103 val1 = BXR2(isp, IspVirt2Off(isp, off));
1104 } while (val0 != val1 && ++i < 1000);
1113 isp_pci_rd_isr(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1118 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) {
1121 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) {
1125 isr = BXR2(isp, IspVirt2Off(isp, BIU_ISR));
1126 sema = BXR2(isp, IspVirt2Off(isp, BIU_SEMA));
1128 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema);
1129 isr &= INT_PENDING_MASK(isp);
1130 sema &= BIU_SEMA_LOCK;
1131 if (isr == 0 && sema == 0) {
1135 if ((*semap = sema) != 0) {
1137 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, info)) {
1141 *info = BXR2(isp, IspVirt2Off(isp, OUTMAILBOX0));
1148 isp_pci_rd_isr_2300(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1150 uint32_t hccr, r2hisr;
1152 if (!(BXR2(isp, IspVirt2Off(isp, BIU_ISR) & BIU2100_ISR_RISC_INT))) {
1156 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU_R2HSTSLO));
1157 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1158 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1162 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1163 case ISPR2HST_ROM_MBX_OK:
1164 case ISPR2HST_ROM_MBX_FAIL:
1165 case ISPR2HST_MBX_OK:
1166 case ISPR2HST_MBX_FAIL:
1167 case ISPR2HST_ASYNC_EVENT:
1170 case ISPR2HST_RIO_16:
1171 *info = ASYNC_RIO16_1;
1174 case ISPR2HST_FPOST:
1175 *info = ASYNC_CMD_CMPLT;
1178 case ISPR2HST_FPOST_CTIO:
1179 *info = ASYNC_CTIO_DONE;
1182 case ISPR2HST_RSPQ_UPDATE:
1186 hccr = ISP_READ(isp, HCCR);
1187 if (hccr & HCCR_PAUSE) {
1188 ISP_WRITE(isp, HCCR, HCCR_RESET);
1189 isp_prt(isp, ISP_LOGERR, "RISC paused at interrupt (%x->%x)", hccr, ISP_READ(isp, HCCR));
1190 ISP_WRITE(isp, BIU_ICR, 0);
1192 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1196 *info = (r2hisr >> 16);
1201 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint16_t *isrp, uint16_t *semap, uint16_t *info)
1205 r2hisr = BXR4(isp, IspVirt2Off(isp, BIU2400_R2HSTSLO));
1206 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr);
1207 if ((r2hisr & BIU_R2HST_INTR) == 0) {
1211 switch ((*isrp = r2hisr & BIU_R2HST_ISTAT_MASK)) {
1212 case ISPR2HST_ROM_MBX_OK:
1213 case ISPR2HST_ROM_MBX_FAIL:
1214 case ISPR2HST_MBX_OK:
1215 case ISPR2HST_MBX_FAIL:
1216 case ISPR2HST_ASYNC_EVENT:
1219 case ISPR2HST_RSPQ_UPDATE:
1220 case ISPR2HST_RSPQ_UPDATE2:
1221 case ISPR2HST_ATIO_UPDATE:
1222 case ISPR2HST_ATIO_RSPQ_UPDATE:
1223 case ISPR2HST_ATIO_UPDATE2:
1227 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
1228 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr);
1231 *info = (r2hisr >> 16);
1236 isp_pci_rd_reg(ispsoftc_t *isp, int regoff)
1241 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1243 * We will assume that someone has paused the RISC processor.
1245 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1246 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf | BIU_PCI_CONF1_SXP);
1247 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1249 rv = BXR2(isp, IspVirt2Off(isp, regoff));
1250 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1251 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1252 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1258 isp_pci_wr_reg(ispsoftc_t *isp, int regoff, uint32_t val)
1262 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1264 * We will assume that someone has paused the RISC processor.
1266 oldconf = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1267 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1268 oldconf | BIU_PCI_CONF1_SXP);
1269 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1271 BXW2(isp, IspVirt2Off(isp, regoff), val);
1272 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1273 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1274 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oldconf);
1275 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1281 isp_pci_rd_reg_1080(ispsoftc_t *isp, int regoff)
1283 uint32_t rv, oc = 0;
1285 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1288 * We will assume that someone has paused the RISC processor.
1290 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1291 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1292 if (regoff & SXP_BANK1_SELECT)
1293 tc |= BIU_PCI1080_CONF1_SXP1;
1295 tc |= BIU_PCI1080_CONF1_SXP0;
1296 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1297 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1298 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1299 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1300 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1301 oc | BIU_PCI1080_CONF1_DMA);
1302 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1304 rv = BXR2(isp, IspVirt2Off(isp, regoff));
1306 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1307 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1313 isp_pci_wr_reg_1080(ispsoftc_t *isp, int regoff, uint32_t val)
1317 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) {
1320 * We will assume that someone has paused the RISC processor.
1322 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1323 tc = oc & ~BIU_PCI1080_CONF1_DMA;
1324 if (regoff & SXP_BANK1_SELECT)
1325 tc |= BIU_PCI1080_CONF1_SXP1;
1327 tc |= BIU_PCI1080_CONF1_SXP0;
1328 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), tc);
1329 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1330 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) {
1331 oc = BXR2(isp, IspVirt2Off(isp, BIU_CONF1));
1332 BXW2(isp, IspVirt2Off(isp, BIU_CONF1),
1333 oc | BIU_PCI1080_CONF1_DMA);
1334 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1336 BXW2(isp, IspVirt2Off(isp, regoff), val);
1337 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1339 BXW2(isp, IspVirt2Off(isp, BIU_CONF1), oc);
1340 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, BIU_CONF1), 2, -1);
1345 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff)
1348 int block = regoff & _BLK_REG_MASK;
1354 return (BXR2(isp, IspVirt2Off(isp, regoff)));
1356 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK read at 0x%x", regoff);
1357 return (0xffffffff);
1359 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK read at 0x%x", regoff);
1360 return (0xffffffff);
1362 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK read at 0x%x", regoff);
1363 return (0xffffffff);
1365 isp_prt(isp, ISP_LOGERR, "unknown block read at 0x%x", regoff);
1366 return (0xffffffff);
1370 case BIU2400_FLASH_ADDR:
1371 case BIU2400_FLASH_DATA:
1375 case BIU2400_REQINP:
1376 case BIU2400_REQOUTP:
1377 case BIU2400_RSPINP:
1378 case BIU2400_RSPOUTP:
1379 case BIU2400_PRI_REQINP:
1380 case BIU2400_PRI_REQOUTP:
1381 case BIU2400_ATIO_RSPINP:
1382 case BIU2400_ATIO_RSPOUTP:
1387 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1389 case BIU2400_R2HSTSLO:
1390 rv = BXR4(isp, IspVirt2Off(isp, regoff));
1392 case BIU2400_R2HSTSHI:
1393 rv = BXR4(isp, IspVirt2Off(isp, regoff)) >> 16;
1396 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
1405 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
1407 int block = regoff & _BLK_REG_MASK;
1413 BXW2(isp, IspVirt2Off(isp, regoff), val);
1414 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 2, -1);
1417 isp_prt(isp, ISP_LOGERR, "SXP_BLOCK write at 0x%x", regoff);
1420 isp_prt(isp, ISP_LOGERR, "RISC_BLOCK write at 0x%x", regoff);
1423 isp_prt(isp, ISP_LOGERR, "DMA_BLOCK write at 0x%x", regoff);
1426 isp_prt(isp, ISP_LOGERR, "unknown block write at 0x%x", regoff);
1431 case BIU2400_FLASH_ADDR:
1432 case BIU2400_FLASH_DATA:
1436 case BIU2400_REQINP:
1437 case BIU2400_REQOUTP:
1438 case BIU2400_RSPINP:
1439 case BIU2400_RSPOUTP:
1440 case BIU2400_PRI_REQINP:
1441 case BIU2400_PRI_REQOUTP:
1442 case BIU2400_ATIO_RSPINP:
1443 case BIU2400_ATIO_RSPOUTP:
1448 BXW4(isp, IspVirt2Off(isp, regoff), val);
1449 #ifdef MEMORYBARRIERW
1450 if (regoff == BIU2400_REQINP ||
1451 regoff == BIU2400_RSPOUTP ||
1452 regoff == BIU2400_PRI_REQINP ||
1453 regoff == BIU2400_ATIO_RSPOUTP)
1454 MEMORYBARRIERW(isp, SYNC_REG,
1455 IspVirt2Off(isp, regoff), 4, -1)
1458 MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
1461 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
1468 isp_pci_rd_reg_2600(ispsoftc_t *isp, int regoff)
1473 case BIU2400_PRI_REQINP:
1474 case BIU2400_PRI_REQOUTP:
1475 isp_prt(isp, ISP_LOGERR, "unknown register read at 0x%x",
1479 case BIU2400_REQINP:
1480 rv = B2R4(isp, 0x00);
1482 case BIU2400_REQOUTP:
1483 rv = B2R4(isp, 0x04);
1485 case BIU2400_RSPINP:
1486 rv = B2R4(isp, 0x08);
1488 case BIU2400_RSPOUTP:
1489 rv = B2R4(isp, 0x0c);
1491 case BIU2400_ATIO_RSPINP:
1492 rv = B2R4(isp, 0x10);
1494 case BIU2400_ATIO_RSPOUTP:
1495 rv = B2R4(isp, 0x14);
1498 rv = isp_pci_rd_reg_2400(isp, regoff);
1505 isp_pci_wr_reg_2600(ispsoftc_t *isp, int regoff, uint32_t val)
1510 case BIU2400_PRI_REQINP:
1511 case BIU2400_PRI_REQOUTP:
1512 isp_prt(isp, ISP_LOGERR, "unknown register write at 0x%x",
1515 case BIU2400_REQINP:
1518 case BIU2400_REQOUTP:
1521 case BIU2400_RSPINP:
1524 case BIU2400_RSPOUTP:
1527 case BIU2400_ATIO_RSPINP:
1530 case BIU2400_ATIO_RSPOUTP:
1534 isp_pci_wr_reg_2400(isp, regoff, val);
1537 B2W4(isp, off, val);
1547 imc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1549 struct imush *imushp = (struct imush *) arg;
1551 if (!(imushp->error = error))
1552 imushp->maddr = segs[0].ds_addr;
1556 isp_pci_mbxdma(ispsoftc_t *isp)
1559 uint32_t len, nsegs;
1560 int i, error, cmap = 0;
1561 bus_size_t slim; /* segment size */
1562 bus_addr_t llim; /* low limit of unavailable dma */
1563 bus_addr_t hlim; /* high limit of unavailable dma */
1568 * Already been here? If so, leave...
1570 if (isp->isp_rquest) {
1575 if (isp->isp_maxcmds == 0) {
1576 isp_prt(isp, ISP_LOGERR, "maxcmds not set");
1581 hlim = BUS_SPACE_MAXADDR;
1582 if (IS_ULTRA2(isp) || IS_FC(isp) || IS_1240(isp)) {
1583 if (sizeof (bus_size_t) > 4) {
1584 slim = (bus_size_t) (1ULL << 32);
1586 slim = (bus_size_t) (1UL << 31);
1588 llim = BUS_SPACE_MAXADDR;
1590 llim = BUS_SPACE_MAXADDR_32BIT;
1594 len = isp->isp_maxcmds * sizeof (struct isp_pcmd);
1595 isp->isp_osinfo.pcmd_pool = (struct isp_pcmd *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1597 if (isp->isp_osinfo.sixtyfourbit) {
1598 nsegs = ISP_NSEG64_MAX;
1600 nsegs = ISP_NSEG_MAX;
1603 if (isp_dma_tag_create(BUS_DMA_ROOTARG(ISP_PCD(isp)), 1, slim, llim, hlim, NULL, NULL, BUS_SPACE_MAXSIZE, nsegs, slim, 0, &isp->isp_osinfo.dmat)) {
1604 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1606 isp_prt(isp, ISP_LOGERR, "could not create master dma tag");
1610 len = sizeof (isp_hdl_t) * isp->isp_maxcmds;
1611 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK | M_ZERO);
1612 for (len = 0; len < isp->isp_maxcmds - 1; len++) {
1613 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1];
1615 isp->isp_xffree = isp->isp_xflist;
1618 * Allocate and map the request queue and a region for external
1619 * DMA addressable command/status structures (22XX and later).
1621 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1622 if (isp->isp_type >= ISP_HA_FC_2200)
1623 len += (N_XCMDS * XCMD_SIZE);
1624 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim,
1625 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1626 len, 1, len, 0, &isp->isp_osinfo.reqdmat)) {
1627 isp_prt(isp, ISP_LOGERR, "cannot create request DMA tag");
1630 if (bus_dmamem_alloc(isp->isp_osinfo.reqdmat, (void **)&base,
1631 BUS_DMA_COHERENT, &isp->isp_osinfo.reqmap) != 0) {
1632 isp_prt(isp, ISP_LOGERR, "cannot allocate request DMA memory");
1633 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat);
1636 isp->isp_rquest = base;
1638 if (bus_dmamap_load(isp->isp_osinfo.reqdmat, isp->isp_osinfo.reqmap,
1639 base, len, imc, &im, 0) || im.error) {
1640 isp_prt(isp, ISP_LOGERR, "error loading request DMA map %d", im.error);
1643 isp_prt(isp, ISP_LOGDEBUG0, "request area @ 0x%jx/0x%jx",
1644 (uintmax_t)im.maddr, (uintmax_t)len);
1645 isp->isp_rquest_dma = im.maddr;
1646 base += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1647 im.maddr += ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp));
1648 if (isp->isp_type >= ISP_HA_FC_2200) {
1649 isp->isp_osinfo.ecmd_dma = im.maddr;
1650 isp->isp_osinfo.ecmd_free = (isp_ecmd_t *)base;
1651 isp->isp_osinfo.ecmd_base = isp->isp_osinfo.ecmd_free;
1652 for (ecmd = isp->isp_osinfo.ecmd_free;
1653 ecmd < &isp->isp_osinfo.ecmd_free[N_XCMDS]; ecmd++) {
1654 if (ecmd == &isp->isp_osinfo.ecmd_free[N_XCMDS - 1])
1657 ecmd->next = ecmd + 1;
1662 * Allocate and map the result queue.
1664 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1665 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim,
1666 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1667 len, 1, len, 0, &isp->isp_osinfo.respdmat)) {
1668 isp_prt(isp, ISP_LOGERR, "cannot create response DMA tag");
1671 if (bus_dmamem_alloc(isp->isp_osinfo.respdmat, (void **)&base,
1672 BUS_DMA_COHERENT, &isp->isp_osinfo.respmap) != 0) {
1673 isp_prt(isp, ISP_LOGERR, "cannot allocate response DMA memory");
1674 bus_dma_tag_destroy(isp->isp_osinfo.respdmat);
1677 isp->isp_result = base;
1679 if (bus_dmamap_load(isp->isp_osinfo.respdmat, isp->isp_osinfo.respmap,
1680 base, len, imc, &im, 0) || im.error) {
1681 isp_prt(isp, ISP_LOGERR, "error loading response DMA map %d", im.error);
1684 isp_prt(isp, ISP_LOGDEBUG0, "response area @ 0x%jx/0x%jx",
1685 (uintmax_t)im.maddr, (uintmax_t)len);
1686 isp->isp_result_dma = im.maddr;
1688 #ifdef ISP_TARGET_MODE
1690 * Allocate and map ATIO queue on 24xx with target mode.
1693 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp));
1694 if (isp_dma_tag_create(isp->isp_osinfo.dmat, QENTRY_LEN, slim,
1695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1696 len, 1, len, 0, &isp->isp_osinfo.atiodmat)) {
1697 isp_prt(isp, ISP_LOGERR, "cannot create ATIO DMA tag");
1700 if (bus_dmamem_alloc(isp->isp_osinfo.atiodmat, (void **)&base,
1701 BUS_DMA_COHERENT, &isp->isp_osinfo.atiomap) != 0) {
1702 isp_prt(isp, ISP_LOGERR, "cannot allocate ATIO DMA memory");
1703 bus_dma_tag_destroy(isp->isp_osinfo.atiodmat);
1706 isp->isp_atioq = base;
1708 if (bus_dmamap_load(isp->isp_osinfo.atiodmat, isp->isp_osinfo.atiomap,
1709 base, len, imc, &im, 0) || im.error) {
1710 isp_prt(isp, ISP_LOGERR, "error loading ATIO DMA map %d", im.error);
1713 isp_prt(isp, ISP_LOGDEBUG0, "ATIO area @ 0x%jx/0x%jx",
1714 (uintmax_t)im.maddr, (uintmax_t)len);
1715 isp->isp_atioq_dma = im.maddr;
1720 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim,
1721 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1722 2*QENTRY_LEN, 1, 2*QENTRY_LEN, 0, &isp->isp_osinfo.iocbdmat)) {
1725 if (bus_dmamem_alloc(isp->isp_osinfo.iocbdmat,
1726 (void **)&base, BUS_DMA_COHERENT, &isp->isp_osinfo.iocbmap) != 0)
1728 isp->isp_iocb = base;
1730 if (bus_dmamap_load(isp->isp_osinfo.iocbdmat, isp->isp_osinfo.iocbmap,
1731 base, 2*QENTRY_LEN, imc, &im, 0) || im.error)
1733 isp->isp_iocb_dma = im.maddr;
1735 if (isp_dma_tag_create(isp->isp_osinfo.dmat, 64, slim,
1736 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1737 ISP_FC_SCRLEN, 1, ISP_FC_SCRLEN, 0, &isp->isp_osinfo.scdmat))
1739 for (cmap = 0; cmap < isp->isp_nchan; cmap++) {
1740 struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1741 if (bus_dmamem_alloc(isp->isp_osinfo.scdmat,
1742 (void **)&base, BUS_DMA_COHERENT, &fc->scmap) != 0)
1744 FCPARAM(isp, cmap)->isp_scratch = base;
1746 if (bus_dmamap_load(isp->isp_osinfo.scdmat, fc->scmap,
1747 base, ISP_FC_SCRLEN, imc, &im, 0) || im.error) {
1748 bus_dmamem_free(isp->isp_osinfo.scdmat,
1752 FCPARAM(isp, cmap)->isp_scdma = im.maddr;
1753 if (!IS_2100(isp)) {
1754 for (i = 0; i < INITIAL_NEXUS_COUNT; i++) {
1755 struct isp_nexus *n = malloc(sizeof (struct isp_nexus), M_DEVBUF, M_NOWAIT | M_ZERO);
1757 while (fc->nexus_free_list) {
1758 n = fc->nexus_free_list;
1759 fc->nexus_free_list = n->next;
1764 n->next = fc->nexus_free_list;
1765 fc->nexus_free_list = n;
1771 for (i = 0; i < isp->isp_maxcmds; i++) {
1772 struct isp_pcmd *pcmd = &isp->isp_osinfo.pcmd_pool[i];
1773 error = bus_dmamap_create(isp->isp_osinfo.dmat, 0, &pcmd->dmap);
1775 isp_prt(isp, ISP_LOGERR, "error %d creating per-cmd DMA maps", error);
1777 bus_dmamap_destroy(isp->isp_osinfo.dmat, isp->isp_osinfo.pcmd_pool[i].dmap);
1781 callout_init_mtx(&pcmd->wdog, &isp->isp_osinfo.lock, 0);
1782 if (i == isp->isp_maxcmds-1) {
1785 pcmd->next = &isp->isp_osinfo.pcmd_pool[i+1];
1788 isp->isp_osinfo.pcmd_free = &isp->isp_osinfo.pcmd_pool[0];
1794 while (--cmap >= 0) {
1795 struct isp_fc *fc = ISP_FC_PC(isp, cmap);
1796 bus_dmamap_unload(isp->isp_osinfo.scdmat, fc->scmap);
1797 bus_dmamem_free(isp->isp_osinfo.scdmat,
1798 FCPARAM(isp, cmap)->isp_scratch, fc->scmap);
1799 while (fc->nexus_free_list) {
1800 struct isp_nexus *n = fc->nexus_free_list;
1801 fc->nexus_free_list = n->next;
1805 bus_dma_tag_destroy(isp->isp_osinfo.scdmat);
1806 bus_dmamap_unload(isp->isp_osinfo.iocbdmat, isp->isp_osinfo.iocbmap);
1807 bus_dmamem_free(isp->isp_osinfo.iocbdmat, isp->isp_iocb,
1808 isp->isp_osinfo.iocbmap);
1809 bus_dma_tag_destroy(isp->isp_osinfo.iocbdmat);
1812 if (isp->isp_rquest_dma != 0) {
1813 bus_dmamap_unload(isp->isp_osinfo.reqdmat,
1814 isp->isp_osinfo.reqmap);
1816 if (isp->isp_rquest != NULL) {
1817 bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_rquest,
1818 isp->isp_osinfo.reqmap);
1819 bus_dma_tag_destroy(isp->isp_osinfo.reqdmat);
1821 if (isp->isp_result_dma != 0) {
1822 bus_dmamap_unload(isp->isp_osinfo.respdmat,
1823 isp->isp_osinfo.respmap);
1825 if (isp->isp_result != NULL) {
1826 bus_dmamem_free(isp->isp_osinfo.respdmat, isp->isp_result,
1827 isp->isp_osinfo.respmap);
1828 bus_dma_tag_destroy(isp->isp_osinfo.respdmat);
1830 #ifdef ISP_TARGET_MODE
1832 if (isp->isp_atioq_dma != 0) {
1833 bus_dmamap_unload(isp->isp_osinfo.atiodmat,
1834 isp->isp_osinfo.atiomap);
1836 if (isp->isp_atioq != NULL) {
1837 bus_dmamem_free(isp->isp_osinfo.reqdmat, isp->isp_atioq,
1838 isp->isp_osinfo.atiomap);
1839 bus_dma_tag_destroy(isp->isp_osinfo.atiodmat);
1843 free(isp->isp_xflist, M_DEVBUF);
1844 free(isp->isp_osinfo.pcmd_pool, M_DEVBUF);
1845 isp->isp_rquest = NULL;
1853 void *rq; /* original request */
1858 #define MUSHERR_NOQENTRIES -2
1860 #ifdef ISP_TARGET_MODE
1861 static void tdma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1862 static void tdma2(void *, bus_dma_segment_t *, int, int);
1865 tdma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1869 mp->mapsize = mapsize;
1870 tdma2(arg, dm_segs, nseg, error);
1874 tdma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1878 struct ccb_scsiio *csio;
1882 mp = (mush_t *) arg;
1887 csio = mp->cmd_token;
1891 if (isp->isp_osinfo.sixtyfourbit) {
1892 if (nseg >= ISP_NSEG64_MAX) {
1893 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1897 if (rq->req_header.rqs_entry_type == RQSTYPE_CTIO2) {
1898 rq->req_header.rqs_entry_type = RQSTYPE_CTIO3;
1901 if (nseg >= ISP_NSEG_MAX) {
1902 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1907 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1908 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1909 ddir = ISP_TO_DEVICE;
1910 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1911 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1912 ddir = ISP_FROM_DEVICE;
1924 error = isp_send_tgt_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, &csio->sense_data, csio->sense_len);
1927 mp->error = MUSHERR_NOQENTRIES;
1936 static void dma2_2(void *, bus_dma_segment_t *, int, bus_size_t, int);
1937 static void dma2(void *, bus_dma_segment_t *, int, int);
1940 dma2_2(void *arg, bus_dma_segment_t *dm_segs, int nseg, bus_size_t mapsize, int error)
1944 mp->mapsize = mapsize;
1945 dma2(arg, dm_segs, nseg, error);
1949 dma2(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
1953 struct ccb_scsiio *csio;
1957 mp = (mush_t *) arg;
1962 csio = mp->cmd_token;
1966 if (isp->isp_osinfo.sixtyfourbit) {
1967 if (nseg >= ISP_NSEG64_MAX) {
1968 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG64_MAX);
1972 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) {
1973 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS;
1974 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) {
1975 rq->req_header.rqs_entry_type = RQSTYPE_A64;
1978 if (nseg >= ISP_NSEG_MAX) {
1979 isp_prt(isp, ISP_LOGERR, "number of segments (%d) exceed maximum we can support (%d)", nseg, ISP_NSEG_MAX);
1984 if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1985 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREREAD);
1986 ddir = ISP_FROM_DEVICE;
1987 } else if ((csio->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1988 bus_dmamap_sync(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap, BUS_DMASYNC_PREWRITE);
1989 ddir = ISP_TO_DEVICE;
1999 error = isp_send_cmd(isp, rq, dm_segs, nseg, XS_XFRLEN(csio), ddir, (ispds64_t *)csio->req_map);
2002 mp->error = MUSHERR_NOQENTRIES;
2013 isp_pci_dmasetup(ispsoftc_t *isp, struct ccb_scsiio *csio, void *ff)
2016 void (*eptr)(void *, bus_dma_segment_t *, int, int);
2017 void (*eptr2)(void *, bus_dma_segment_t *, int, bus_size_t, int);
2022 mp->cmd_token = csio;
2027 #ifdef ISP_TARGET_MODE
2028 if (csio->ccb_h.func_code == XPT_CONT_TARGET_IO) {
2039 error = bus_dmamap_load_ccb(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap,
2040 (union ccb *)csio, eptr, mp, 0);
2041 if (error == EINPROGRESS) {
2042 bus_dmamap_unload(isp->isp_osinfo.dmat, PISP_PCMD(csio)->dmap);
2044 isp_prt(isp, ISP_LOGERR, "deferred dma allocation not supported");
2045 } else if (error && mp->error == 0) {
2047 isp_prt(isp, ISP_LOGERR, "error %d in dma mapping code", error);
2052 int retval = CMD_COMPLETE;
2053 if (mp->error == MUSHERR_NOQENTRIES) {
2054 retval = CMD_EAGAIN;
2055 } else if (mp->error == EFBIG) {
2056 csio->ccb_h.status = CAM_REQ_TOO_BIG;
2057 } else if (mp->error == EINVAL) {
2058 csio->ccb_h.status = CAM_REQ_INVALID;
2060 csio->ccb_h.status = CAM_UNREC_HBA_ERROR;
2064 return (CMD_QUEUED);
2068 isp_pci_reset0(ispsoftc_t *isp)
2070 ISP_DISABLE_INTS(isp);
2074 isp_pci_reset1(ispsoftc_t *isp)
2076 if (!IS_24XX(isp)) {
2077 /* Make sure the BIOS is disabled */
2078 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
2080 /* and enable interrupts */
2081 ISP_ENABLE_INTS(isp);
2085 isp_pci_dumpregs(ispsoftc_t *isp, const char *msg)
2087 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp;
2089 printf("%s: %s\n", device_get_nameunit(isp->isp_dev), msg);
2091 printf("%s:\n", device_get_nameunit(isp->isp_dev));
2093 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1));
2095 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR));
2096 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR),
2097 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA));
2098 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR));
2102 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
2103 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n",
2104 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS),
2105 ISP_READ(isp, CDMA_FIFO_STS));
2106 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n",
2107 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS),
2108 ISP_READ(isp, DDMA_FIFO_STS));
2109 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n",
2110 ISP_READ(isp, SXP_INTERRUPT),
2111 ISP_READ(isp, SXP_GROSS_ERR),
2112 ISP_READ(isp, SXP_PINS_CTRL));
2113 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
2115 printf(" mbox regs: %x %x %x %x %x\n",
2116 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1),
2117 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3),
2118 ISP_READ(isp, OUTMAILBOX4));
2119 printf(" PCI Status Command/Status=%x\n",
2120 pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1));