3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
5 * Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org>
6 * Copyright (c) 1997-2009 by Matthew Jacob
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
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33 * Machine Independent (well, as best as possible) register
34 * definitions for Qlogic ISP SCSI adapters.
40 * Hardware definitions for the Qlogic ISP registers.
44 * This defines types of access to various registers.
50 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only
51 * if RISC processor in ISP is paused.
55 * NB: The *_BLOCK definitions have no specific hardware meaning.
56 * They serve simply to note to the MD layer which block of
57 * registers offsets are being accessed.
60 #define _BLK_REG_SHFT 7
61 #define _BLK_REG_MASK (1 << _BLK_REG_SHFT)
62 #define BIU_BLOCK (0 << _BLK_REG_SHFT)
63 #define MBOX_BLOCK (1 << _BLK_REG_SHFT)
65 #define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
66 #define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
67 #define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
68 #define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
69 #define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
70 #define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
71 #define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
72 #define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
73 #define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
74 #define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
75 #define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
76 #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
77 #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
78 #define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
79 #define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
80 #define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
83 * 2400 Interface Offsets and Register Definitions
85 * The 2400 looks quite different in terms of registers from other QLogic cards.
86 * It is getting to be a genuine pain and challenge to keep the same model
89 #define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) /* Flash Access Address */
90 #define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) /* Flash Data */
91 #define BIU2400_CSR (BIU_BLOCK+0x08) /* ISP Control/Status */
92 #define BIU2400_ICR (BIU_BLOCK+0x0C) /* ISP to PCI Interrupt Control */
93 #define BIU2400_ISR (BIU_BLOCK+0x10) /* ISP to PCI Interrupt Status */
95 #define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
96 #define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
97 #define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
98 #define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
100 #define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
101 #define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */
103 #define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
104 #define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */
106 #define BIU2400_R2HSTS (BIU_BLOCK+0x44) /* RISC to Host Status */
108 #define BIU2400_HCCR (BIU_BLOCK+0x48) /* Host Command and Control Status */
109 #define BIU2400_GPIOD (BIU_BLOCK+0x4C) /* General Purpose I/O Data */
110 #define BIU2400_GPIOE (BIU_BLOCK+0x50) /* General Purpose I/O Enable */
111 #define BIU2400_IOBBA (BIU_BLOCK+0x54) /* I/O Bus Base Address */
112 #define BIU2400_HSEMA (BIU_BLOCK+0x58) /* Host-to-Host Semaphore */
114 /* BIU2400_FLASH_ADDR definitions */
115 #define BIU2400_FLASH_DFLAG (1 << 30)
117 /* BIU2400_CSR definitions */
118 #define BIU2400_NVERR (1 << 18)
119 #define BIU2400_DMA_ACTIVE (1 << 17) /* RO */
120 #define BIU2400_DMA_STOP (1 << 16)
121 #define BIU2400_FUNCTION (1 << 15) /* RO */
122 #define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
123 #define BIU2400_CSR_64BIT (1 << 2) /* RO */
124 #define BIU2400_FLASH_ENABLE (1 << 1)
125 #define BIU2400_SOFT_RESET (1 << 0)
127 /* BIU2400_ICR definitions */
128 #define BIU2400_ICR_ENA_RISC_INT 0x8
129 #define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
131 /* BIU2400_ISR definitions */
132 #define BIU2400_ISR_RISC_INT 0x8
134 /* BIU2400_HCCR definitions */
135 #define HCCR_2400_CMD_NOP 0x00000000
136 #define HCCR_2400_CMD_RESET 0x10000000
137 #define HCCR_2400_CMD_CLEAR_RESET 0x20000000
138 #define HCCR_2400_CMD_PAUSE 0x30000000
139 #define HCCR_2400_CMD_RELEASE 0x40000000
140 #define HCCR_2400_CMD_SET_HOST_INT 0x50000000
141 #define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000
142 #define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000
144 #define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
145 #define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */
146 #define HCCR_2400_RISC_RESET (1 << 5) /* RO */
150 * Mailbox Block Register Offsets
152 #define INMAILBOX0 (MBOX_BLOCK+0x0)
153 #define INMAILBOX1 (MBOX_BLOCK+0x2)
154 #define INMAILBOX2 (MBOX_BLOCK+0x4)
155 #define INMAILBOX3 (MBOX_BLOCK+0x6)
156 #define INMAILBOX4 (MBOX_BLOCK+0x8)
157 #define INMAILBOX5 (MBOX_BLOCK+0xA)
158 #define INMAILBOX6 (MBOX_BLOCK+0xC)
159 #define INMAILBOX7 (MBOX_BLOCK+0xE)
161 #define OUTMAILBOX0 (MBOX_BLOCK+0x0)
162 #define OUTMAILBOX1 (MBOX_BLOCK+0x2)
163 #define OUTMAILBOX2 (MBOX_BLOCK+0x4)
164 #define OUTMAILBOX3 (MBOX_BLOCK+0x6)
165 #define OUTMAILBOX4 (MBOX_BLOCK+0x8)
166 #define OUTMAILBOX5 (MBOX_BLOCK+0xA)
167 #define OUTMAILBOX6 (MBOX_BLOCK+0xC)
168 #define OUTMAILBOX7 (MBOX_BLOCK+0xE)
170 #define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1))
171 #define ISP_NMBOX(isp) 32
172 #define MAX_MAILBOX 32
174 /* if timeout == 0, then default timeout is picked */
175 #define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */
177 uint16_t param[MAX_MAILBOX];
178 uint32_t ibits; /* bits to add for register copyin */
179 uint32_t obits; /* bits to add for register copyout */
180 uint32_t ibitm; /* bits to mask for register copyin */
181 uint32_t obitm; /* bits to mask for register copyout */
182 uint32_t logval; /* Bitmask of status codes to log */
187 #define MBSINIT(mbxp, code, loglev, timo) \
188 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \
189 (mbxp)->ibitm = ~0; \
190 (mbxp)->obitm = ~0; \
191 (mbxp)->param[0] = code; \
192 (mbxp)->lineno = __LINE__; \
193 (mbxp)->func = __func__; \
194 (mbxp)->logval = loglev; \
195 (mbxp)->timeout = timo
198 * Defines for Interrupts
200 #define ISP_INTS_ENABLED(isp) \
201 (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK)
203 #define ISP_ENABLE_INTS(isp) \
204 ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)
206 #define ISP_DISABLE_INTS(isp) \
207 ISP_WRITE(isp, BIU2400_ICR, 0)
210 * NVRAM Definitions (PCI cards only)
214 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum.
216 #define ISP2400_NVRAM_PORT_ADDR(c) (0x100 * (c) + 0x80)
217 #define ISP2400_NVRAM_SIZE 512
219 #define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8))
220 #define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8))
221 #define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8))
223 #define ISP2400_NVRAM_PORT_NAME(c) (\
224 (((uint64_t)(c)[20]) << 56) | \
225 (((uint64_t)(c)[21]) << 48) | \
226 (((uint64_t)(c)[22]) << 40) | \
227 (((uint64_t)(c)[23]) << 32) | \
228 (((uint64_t)(c)[24]) << 24) | \
229 (((uint64_t)(c)[25]) << 16) | \
230 (((uint64_t)(c)[26]) << 8) | \
231 (((uint64_t)(c)[27]) << 0))
233 #define ISP2400_NVRAM_NODE_NAME(c) (\
234 (((uint64_t)(c)[28]) << 56) | \
235 (((uint64_t)(c)[29]) << 48) | \
236 (((uint64_t)(c)[30]) << 40) | \
237 (((uint64_t)(c)[31]) << 32) | \
238 (((uint64_t)(c)[32]) << 24) | \
239 (((uint64_t)(c)[33]) << 16) | \
240 (((uint64_t)(c)[34]) << 8) | \
241 (((uint64_t)(c)[35]) << 0))
243 #define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8))
244 #define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8))
245 #define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8))
246 #define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8))
248 #define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \
249 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24))
250 #define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \
251 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24))
252 #define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
253 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))
255 #endif /* _ISPREG_H */