1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
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18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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28 * in the file called COPYING.
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31 * Intel Linux Wireless <ilw@linux.intel.com>
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63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
77 * CSR (control and status registers)
79 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * whenever platform supplies power to device, even when device is in
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
84 * Use iwl_write32() and iwl_read32() family to access these registers;
85 * these provide simple PCI bus access, without waking up the MAC.
86 * Do not use iwl_write_direct32() family for these registers;
87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
91 * NOTE: Device does need to be awake in order to read this memory
92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101 #define IWM_CSR_GP_CNTRL (0x024)
103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
104 #define IWM_CSR_INT_PERIODIC_REG (0x005)
107 * Hardware revision info
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
114 #define IWM_CSR_HW_REV (0x028)
117 * EEPROM and OTP (one-time-programmable) memory reads
119 * NOTE: Device must be awake, initialized via apm_ops.init(),
122 #define IWM_CSR_EEPROM_REG (0x02c)
123 #define IWM_CSR_EEPROM_GP (0x030)
124 #define IWM_CSR_OTP_GP_REG (0x034)
126 #define IWM_CSR_GIO_REG (0x03C)
127 #define IWM_CSR_GP_UCODE_REG (0x048)
128 #define IWM_CSR_GP_DRIVER_REG (0x050)
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
132 * SET/CLR registers set/clear bit(s) if "1" is written.
134 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
139 #define IWM_CSR_MBOX_SET_REG (0x088)
140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
142 #define IWM_CSR_LED_REG (0x094)
143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
147 /* GIO Chicken Bits (PCI Express bus link power management) */
148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
150 /* Analog phase-lock-loop configuration */
151 #define IWM_CSR_ANA_PLL_CFG (0x20c)
154 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
156 * See also IWM_CSR_HW_REV register.
158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
159 * 1-0: "Dash" (-) value, as in C-1, etc.
161 #define IWM_CSR_HW_REV_WA_REG (0x22C)
163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
195 * acknowledged (reset) by host writing "1" to flagged bits. */
196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
209 IWM_CSR_INT_BIT_HW_ERR | \
210 IWM_CSR_INT_BIT_FH_TX | \
211 IWM_CSR_INT_BIT_SW_ERR | \
212 IWM_CSR_INT_BIT_RF_KILL | \
213 IWM_CSR_INT_BIT_SW_RX | \
214 IWM_CSR_INT_BIT_WAKEUP | \
215 IWM_CSR_INT_BIT_ALIVE | \
216 IWM_CSR_INT_BIT_RX_PERIODIC)
218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
228 IWM_CSR_FH_INT_BIT_RX_CHNL0)
230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
231 IWM_CSR_FH_INT_BIT_TX_CHNL0)
234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
247 * GP (general purpose) CONTROL REGISTER
250 * Indicates state of (platform's) hardware RF-Kill switch
251 * 26-24: POWER_SAVE_TYPE
252 * Indicates current power-saving mode:
253 * 000 -- No power saving
254 * 001 -- MAC power-down
255 * 010 -- PHY (radio) power-down
258 * Indicates current system configuration, reflecting pins on chip
259 * as forced high/low by device circuit board.
261 * Indicates MAC is entering a power-saving sleep power-down.
262 * Not a good time to access device-internal resources.
264 * Host sets this to request and maintain MAC wakeup, to allow host
265 * access to device-internal resources. Host must wait for
266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
269 * Host sets this to put device into fully operational D0 power mode.
270 * Host resets this after SW_RESET to put device into low power mode.
272 * Indicates MAC (ucode processor, etc.) is powered up and can run.
273 * Internal resources are accessible.
274 * NOTE: This does not indicate that the processor is actually running.
275 * NOTE: This does not indicate that device has completed
276 * init or post-power-down restore of internal SRAM memory.
277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
278 * SRAM is restored and uCode is in normal operation mode.
279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
280 * do not need to save/restore it.
281 * NOTE: After device reset, this bit remains "0" until host sets
284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
292 #define IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
304 IWM_SILICON_A_STEP = 0,
310 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
311 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
312 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
313 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
314 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
315 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
316 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
317 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
318 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
319 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
320 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
321 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
322 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
323 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
324 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
325 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
326 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
327 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
330 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
331 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
332 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
333 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
336 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
337 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
338 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
339 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
341 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
343 /* One-time-programmable memory general purpose reg */
344 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
345 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
346 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
347 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
350 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
351 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
352 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
353 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
354 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
358 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
361 * UCODE-DRIVER GP (general purpose) mailbox register 1
362 * Host driver and uCode write and/or read this register to communicate with
366 * Host sets this to request permanent halt of uCode, same as
367 * sending CARD_STATE command with "halt" bit set.
369 * Host sets this to request exit from CT_KILL state, i.e. host thinks
370 * device temperature is low enough to continue normal operation.
372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
373 * to release uCode to clear all Tx and command queues, enter
374 * unassociated mode, and power down.
375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
377 * Host sets this when issuing CARD_STATE command to request
380 * uCode sets this when preparing a power-saving power-down.
381 * uCode resets this when power-up is complete and SRAM is sane.
382 * NOTE: device saves internal SRAM data to host when powering down,
383 * and must restore this data after powering back up.
384 * MAC_SLEEP is the best indication that restore is complete.
385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
386 * do not need to save/restore it.
388 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
389 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
390 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
391 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
392 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
399 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
400 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
402 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
404 /* GIO Chicken Bits (PCI Express bus link power management) */
405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
406 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
409 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
410 #define IWM_CSR_LED_REG_TURN_ON (0x60)
411 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
414 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
417 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
420 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
421 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
422 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
424 /* SECURE boot registers */
425 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
426 enum iwm_secure_boot_config_reg {
427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
431 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
432 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
433 enum iwm_secure_boot_status_reg {
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
441 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
442 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
444 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
445 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
447 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
448 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
450 #define IWM_CSR_SECURE_TIME_OUT (100)
452 /* extended range in FW SRAM */
453 #define IWM_FW_MEM_EXTENDED_START 0x40000
454 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
456 /* FW chicken bits */
457 #define IWM_LMPM_CHICK 0xa01ff8
458 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
460 #define IWM_UREG_CHICK 0xa05c00
461 #define IWM_UREG_CHICK_MSI_ENABLE 0x01000000
462 #define IWM_UREG_CHICK_MSIX_ENABLE 0x02000000
464 #define IWM_FH_TCSR_0_REG0 (0x1D00)
467 * HBUS (Host-side Bus)
469 * HBUS registers are mapped directly into PCI bus space, but are used
470 * to indirectly access device's internal memory or registers that
471 * may be powered-down.
473 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
474 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
475 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
476 * internal resources.
478 * Do not use iwl_write32()/iwl_read32() family to access these registers;
479 * these provide only simple PCI bus access, without waking up the MAC.
481 #define IWM_HBUS_BASE (0x400)
484 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
485 * structures, error log, event log, verifying uCode load).
486 * First write to address register, then read from or write to data register
487 * to complete the job. Once the address register is set up, accesses to
488 * data registers auto-increment the address by one dword.
489 * Bit usage for address registers (read or write):
490 * 0-31: memory address within device
492 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
493 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
494 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
495 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
497 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
498 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
499 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
502 * Registers for accessing device's internal peripheral registers
503 * (e.g. SCD, BSM, etc.). First write to address register,
504 * then read from or write to data register to complete the job.
505 * Bit usage for address registers (read or write):
506 * 0-15: register address (offset) within device
507 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
509 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
510 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
511 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
512 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
514 /* enable the ID buf for read */
515 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
516 #define IWM_WFMP_MAC_ADDR_0 0xa03080
517 #define IWM_WFMP_MAC_ADDR_1 0xa03084
518 #define IWM_LMPM_PMG_EN 0xa01cec
519 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
520 #define IWM_RFIC_REG_RD 0xad0470
521 #define IWM_WFPM_CTRL_REG 0xa03030
522 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
523 #define IWM_ENABLE_WFPM 0x80000000
525 #define IWM_AUX_MISC_REG 0xa200b0
526 #define IWM_HW_STEP_LOCATION_BITS 24
528 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
529 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
530 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
531 #define IWM_RSA_ENABLE 0xa24b08
532 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
533 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
534 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
535 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
536 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
537 #define IWM_SB_CPU_1_STATUS 0xa01e30
538 #define IWM_SB_CPU_2_STATUS 0Xa01e34
540 /* Used to enable DBGM */
541 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
544 * Per-Tx-queue write pointer (index, really!)
545 * Indicates index to next TFD that driver will fill (1 past latest filled).
547 * 0-7: queue write index
548 * 11-8: queue selector
550 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
552 /**********************************************************
554 **********************************************************/
556 * host interrupt timeout value
557 * used with setting interrupt coalescing timer
558 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
560 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
562 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
563 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
564 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
565 #define IWM_HOST_INT_OPER_MODE (1 << 31)
567 /*****************************************************************************
568 * 7000/3000 series SHR DTS addresses *
569 *****************************************************************************/
571 /* Diode Results Register Structure: */
572 enum iwm_dtd_diode_reg {
573 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
574 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
575 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
576 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
577 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
578 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
579 /* Those are the masks INSIDE the flags bit-field: */
580 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
581 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
582 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
583 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
595 * enum iwm_ucode_tlv_flag - ucode API flags
596 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
597 * was a separate TLV but moved here to save space.
598 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
599 * treats good CRC threshold as a boolean
600 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
601 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
602 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
603 * offload profile config command.
604 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
605 * (rather than two) IPv6 addresses
606 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
607 * from the probe request template.
608 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
609 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
610 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
611 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
612 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
613 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
615 enum iwm_ucode_tlv_flag {
616 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
617 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
618 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
619 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
620 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
621 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
622 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
623 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
624 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
625 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
626 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
627 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
630 #define IWM_UCODE_TLV_FLAG_BITS \
631 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
632 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
633 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
634 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
637 * enum iwm_ucode_tlv_api - ucode api
638 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
639 * longer than the passive one, which is essential for fragmented scan.
640 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
641 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
642 * @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format
643 * @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
644 * iteration complete notification, and the timestamp reported for RX
645 * received during scan, are reported in TSF of the mac specified in the
647 * @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
648 * ADD_MODIFY_STA_KEY_API_S_VER_2.
649 * @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement.
650 * @IWM_UCODE_TLV_API_NAN2_VER2: This ucode supports NAN API version 2
651 * @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
652 * @IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY: Quota command includes a field
653 * indicating low latency direction.
654 * @IWM_UCODE_TLV_API_DEPRECATE_TTAK: RX status flag TTAK ok (bit 7) is
656 * @IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2: This ucode supports version 8
657 * of scan request: SCAN_REQUEST_CMD_UMAC_API_S_VER_8
658 * @IWM_UCODE_TLV_API_FRAG_EBS: This ucode supports fragmented EBS
659 * @IWM_UCODE_TLV_API_REDUCE_TX_POWER: This ucode supports v5 of
660 * the REDUCE_TX_POWER_CMD.
661 * @IWM_UCODE_TLV_API_SHORT_BEACON_NOTIF: This ucode supports the short
662 * version of the beacon notification.
663 * @IWM_UCODE_TLV_API_BEACON_FILTER_V4: This ucode supports v4 of
664 * BEACON_FILTER_CONFIG_API_S_VER_4.
665 * @IWM_UCODE_TLV_API_REGULATORY_NVM_INFO: This ucode supports v4 of
666 * REGULATORY_NVM_GET_INFO_RSP_API_S.
667 * @IWM_UCODE_TLV_API_FTM_NEW_RANGE_REQ: This ucode supports v7 of
668 * LOCATION_RANGE_REQ_CMD_API_S and v6 of LOCATION_RANGE_RESP_NTFY_API_S.
669 * @IWM_UCODE_TLV_API_SCAN_OFFLOAD_CHANS: This ucode supports v2 of
670 * SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S and v3 of
671 * SCAN_OFFLOAD_PROFILES_QUERY_RSP_S.
672 * @IWM_UCODE_TLV_API_MBSSID_HE: This ucode supports v2 of
673 * STA_CONTEXT_DOT11AX_API_S
674 * @IWM_UCODE_TLV_CAPA_SAR_TABLE_VER: This ucode supports different sar
677 * @IWM_NUM_UCODE_TLV_API: number of bits used
679 enum iwm_ucode_tlv_api {
680 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8,
681 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9,
682 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18,
683 IWM_UCODE_TLV_API_NEW_VERSION = 20,
684 IWM_UCODE_TLV_API_SCAN_TSF_REPORT = 28,
685 IWM_UCODE_TLV_API_TKIP_MIC_KEYS = 29,
686 IWM_UCODE_TLV_API_STA_TYPE = 30,
687 IWM_UCODE_TLV_API_NAN2_VER2 = 31,
688 IWM_UCODE_TLV_API_ADAPTIVE_DWELL = 32,
689 IWM_UCODE_TLV_API_OCE = 33,
690 IWM_UCODE_TLV_API_NEW_BEACON_TEMPLATE = 34,
691 IWM_UCODE_TLV_API_NEW_RX_STATS = 35,
692 IWM_UCODE_TLV_API_WOWLAN_KEY_MATERIAL = 36,
693 IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY = 38,
694 IWM_UCODE_TLV_API_DEPRECATE_TTAK = 41,
695 IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 = 42,
696 IWM_UCODE_TLV_API_FRAG_EBS = 44,
697 IWM_UCODE_TLV_API_REDUCE_TX_POWER = 45,
698 IWM_UCODE_TLV_API_SHORT_BEACON_NOTIF = 46,
699 IWM_UCODE_TLV_API_BEACON_FILTER_V4 = 47,
700 IWM_UCODE_TLV_API_REGULATORY_NVM_INFO = 48,
701 IWM_UCODE_TLV_API_FTM_NEW_RANGE_REQ = 49,
702 IWM_UCODE_TLV_API_SCAN_OFFLOAD_CHANS = 50,
703 IWM_UCODE_TLV_API_MBSSID_HE = 52,
704 IWM_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE = 53,
705 IWM_UCODE_TLV_API_FTM_RTT_ACCURACY = 54,
706 IWM_UCODE_TLV_API_SAR_TABLE_VER = 55,
707 IWM_UCODE_TLV_API_ADWELL_HB_DEF_N_AP = 57,
708 IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER = 58,
710 IWM_NUM_UCODE_TLV_API = 128,
714 * enum iwm_ucode_tlv_capa - ucode capabilities
715 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
716 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
717 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
718 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
719 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
720 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
721 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
722 * tx power value into TPC Report action frame and Link Measurement Report
724 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
725 * channel in DS parameter set element in probe requests.
726 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
728 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
729 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
730 * which also implies support for the scheduler configuration command
731 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
732 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
733 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
734 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
735 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
736 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
737 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
738 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
739 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
740 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
741 * sources for the MCC. This TLV bit is a future replacement to
742 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
744 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
745 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
746 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
747 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
749 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
750 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
751 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
752 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
753 * antenna the beacon should be transmitted
754 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
755 * from AP and will send it upon d0i3 exit.
756 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
757 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
758 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
759 * thresholds reporting
760 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
761 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
763 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
764 * memory addresses from the firmware.
765 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
766 * @IWM_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger
767 * command size (command version 4) that supports toggling ACK TX
770 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
772 enum iwm_ucode_tlv_capa {
773 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
774 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
775 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
776 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
777 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
778 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
779 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
780 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
781 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
782 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
783 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
784 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
785 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
786 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
787 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
788 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
789 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
790 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
791 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
792 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
793 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
794 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
795 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
796 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
797 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
798 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
799 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
800 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
801 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
802 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
803 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
804 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
805 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
806 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
807 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
808 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
809 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
810 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
811 IWM_UCODE_TLV_CAPA_TX_POWER_ACK = 84,
813 IWM_NUM_UCODE_TLV_CAPA = 128
816 /* The default calibrate table size if not specified by firmware file */
817 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
818 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
819 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
821 /* The default max probe length if not specified by the firmware file */
822 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
825 * enumeration of ucode section.
826 * This enumeration is used directly for older firmware (before 16.0).
827 * For new firmware, there can be up to 4 sections (see below) but the
828 * first one packaged into the firmware file is the DATA section and
829 * some debugging code accesses that.
832 IWM_UCODE_SECTION_DATA,
833 IWM_UCODE_SECTION_INST,
836 * For 16.0 uCode and above, there is no differentiation between sections,
837 * just an offset to the HW address.
839 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
840 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
842 /* uCode version contains 4 values: Major/Minor/API/Serial */
843 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
844 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
845 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
846 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
849 * Calibration control struct.
850 * Sent as part of the phy configuration command.
851 * @flow_trigger: bitmap for which calibrations to perform according to
853 * @event_trigger: bitmap for which calibrations to perform according to
856 struct iwm_tlv_calib_ctrl {
857 uint32_t flow_trigger;
858 uint32_t event_trigger;
861 enum iwm_fw_phy_cfg {
862 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
863 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
864 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
865 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
866 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
867 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
868 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
869 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
870 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
871 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
874 #define IWM_UCODE_MAX_CS 1
877 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
878 * @cipher: a cipher suite selector
879 * @flags: cipher scheme flags (currently reserved for a future use)
880 * @hdr_len: a size of MPDU security header
881 * @pn_len: a size of PN
882 * @pn_off: an offset of pn from the beginning of the security header
883 * @key_idx_off: an offset of key index byte in the security header
884 * @key_idx_mask: a bit mask of key_idx bits
885 * @key_idx_shift: bit shift needed to get key_idx
886 * @mic_len: mic length in bytes
887 * @hw_cipher: a HW cipher index used in host commands
889 struct iwm_fw_cipher_scheme {
896 uint8_t key_idx_mask;
897 uint8_t key_idx_shift;
903 * struct iwm_fw_cscheme_list - a cipher scheme list
904 * @size: a number of entries
905 * @cs: cipher scheme entries
907 struct iwm_fw_cscheme_list {
909 struct iwm_fw_cipher_scheme cs[];
917 * BEGIN iwl-fw-file.h
920 /* v1/v2 uCode file layout */
921 struct iwm_ucode_header {
922 uint32_t ver; /* major/minor/API/serial */
925 uint32_t inst_size; /* bytes of runtime code */
926 uint32_t data_size; /* bytes of runtime data */
927 uint32_t init_size; /* bytes of init code */
928 uint32_t init_data_size; /* bytes of init data */
929 uint32_t boot_size; /* bytes of bootstrap code */
930 uint8_t data[0]; /* in same order as sizes */
933 uint32_t build; /* build number */
934 uint32_t inst_size; /* bytes of runtime code */
935 uint32_t data_size; /* bytes of runtime data */
936 uint32_t init_size; /* bytes of init code */
937 uint32_t init_data_size; /* bytes of init data */
938 uint32_t boot_size; /* bytes of bootstrap code */
939 uint8_t data[0]; /* in same order as sizes */
945 * new TLV uCode file layout
947 * The new TLV file format contains TLVs, that each specify
948 * some piece of data.
951 enum iwm_ucode_tlv_type {
952 IWM_UCODE_TLV_INVALID = 0, /* unused */
953 IWM_UCODE_TLV_INST = 1,
954 IWM_UCODE_TLV_DATA = 2,
955 IWM_UCODE_TLV_INIT = 3,
956 IWM_UCODE_TLV_INIT_DATA = 4,
957 IWM_UCODE_TLV_BOOT = 5,
958 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
959 IWM_UCODE_TLV_PAN = 7,
960 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
961 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
962 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
963 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
964 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
965 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
966 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
967 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
968 IWM_UCODE_TLV_WOWLAN_INST = 16,
969 IWM_UCODE_TLV_WOWLAN_DATA = 17,
970 IWM_UCODE_TLV_FLAGS = 18,
971 IWM_UCODE_TLV_SEC_RT = 19,
972 IWM_UCODE_TLV_SEC_INIT = 20,
973 IWM_UCODE_TLV_SEC_WOWLAN = 21,
974 IWM_UCODE_TLV_DEF_CALIB = 22,
975 IWM_UCODE_TLV_PHY_SKU = 23,
976 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
977 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
978 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
979 IWM_UCODE_TLV_NUM_OF_CPU = 27,
980 IWM_UCODE_TLV_CSCHEME = 28,
983 * Following two are not in our base tag, but allow
984 * handling ucode version 9.
986 IWM_UCODE_TLV_API_CHANGES_SET = 29,
987 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
989 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
990 IWM_UCODE_TLV_PAGING = 32,
991 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
992 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
993 IWM_UCODE_TLV_FW_VERSION = 36,
994 IWM_UCODE_TLV_FW_DBG_DEST = 38,
995 IWM_UCODE_TLV_FW_DBG_CONF = 39,
996 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
997 IWM_UCODE_TLV_CMD_VERSIONS = 48,
998 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
999 IWM_UCODE_TLV_FW_MEM_SEG = 51,
1002 struct iwm_ucode_tlv {
1003 uint32_t type; /* see above */
1004 uint32_t length; /* not including type/length fields */
1008 struct iwm_ucode_api {
1013 struct iwm_ucode_capa {
1018 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
1020 struct iwm_tlv_ucode_header {
1022 * The TLV style ucode header is distinguished from
1023 * the v1/v2 style header by first four bytes being
1024 * zero, as such is an invalid combination of
1025 * major/minor/API/serial versions.
1029 uint8_t human_readable[64];
1030 uint32_t ver; /* major/minor/API/serial */
1034 * The data contained herein has a TLV layout,
1035 * see above for the TLV header and types.
1036 * Note that each TLV is padded to a length
1037 * that is a multiple of 4 for alignment.
1051 * Registers in this file are internal, not PCI bus memory mapped.
1052 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
1054 #define IWM_PRPH_BASE (0x00000)
1055 #define IWM_PRPH_END (0xFFFFF)
1057 /* APMG (power management) constants */
1058 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1059 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1060 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1061 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1062 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1063 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1064 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1065 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1066 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1067 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1068 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1070 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1071 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1072 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1074 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1075 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1076 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1077 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1078 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1079 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1080 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1082 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1084 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1086 /* Device system time */
1087 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1089 /* Device NMI register */
1090 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1091 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1092 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1093 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1094 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1097 * Device reset for family 8000
1098 * write to bit 24 in order to reset the CPU
1100 #define IWM_RELEASE_CPU_RESET 0x300c
1101 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1104 /*****************************************************************************
1105 * 7000/3000 series SHR DTS addresses *
1106 *****************************************************************************/
1108 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1109 #define IWM_DTSC_CFG_MODE (0x00a10604)
1110 #define IWM_DTSC_VREF_AVG (0x00a10648)
1111 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1112 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1113 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1119 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1120 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1121 * host DRAM. It steers each frame's Tx command (which contains the frame
1122 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1123 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1124 * but one DMA channel may take input from several queues.
1126 * Tx DMA FIFOs have dedicated purposes.
1128 * For 5000 series and up, they are used differently
1129 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1131 * 0 -- EDCA BK (background) frames, lowest priority
1132 * 1 -- EDCA BE (best effort) frames, normal priority
1133 * 2 -- EDCA VI (video) frames, higher priority
1134 * 3 -- EDCA VO (voice) and management frames, highest priority
1140 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1141 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1142 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1144 * The driver sets up each queue to work in one of two modes:
1146 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1147 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1148 * contains TFDs for a unique combination of Recipient Address (RA)
1149 * and Traffic Identifier (TID), that is, traffic of a given
1150 * Quality-Of-Service (QOS) priority, destined for a single station.
1152 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1153 * each frame within the BA window, including whether it's been transmitted,
1154 * and whether it's been acknowledged by the receiving station. The device
1155 * automatically processes block-acks received from the receiving STA,
1156 * and reschedules un-acked frames to be retransmitted (successful
1157 * Tx completion may end up being out-of-order).
1159 * The driver must maintain the queue's Byte Count table in host DRAM
1161 * This mode does not support fragmentation.
1163 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1164 * The device may automatically retry Tx, but will retry only one frame
1165 * at a time, until receiving ACK from receiving station, or reaching
1166 * retry limit and giving up.
1168 * The command queue (#4/#9) must use this mode!
1169 * This mode does not require use of the Byte Count table in host DRAM.
1171 * Driver controls scheduler operation via 3 means:
1172 * 1) Scheduler registers
1173 * 2) Shared scheduler data base in internal SRAM
1174 * 3) Shared data in host DRAM
1178 * When loading, driver should allocate memory for:
1179 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1180 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1181 * (1024 bytes for each queue).
1183 * After receiving "Alive" response from uCode, driver must initialize
1184 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1185 * the driver can't issue commands!):
1187 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1190 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1191 * can keep track of at one time when creating block-ack chains of frames.
1192 * Note that "64" matches the number of ack bits in a block-ack packet.
1194 #define IWM_SCD_WIN_SIZE 64
1195 #define IWM_SCD_FRAME_LIMIT 64
1197 #define IWM_SCD_TXFIFO_POS_TID (0)
1198 #define IWM_SCD_TXFIFO_POS_RA (4)
1199 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1202 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1203 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1204 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1205 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1206 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1208 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1209 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1210 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1211 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1212 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1213 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1214 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1215 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1216 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1217 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1220 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1221 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1224 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1225 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1227 /* Translation Data */
1228 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1229 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1231 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1232 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1234 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1235 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1237 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1238 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1240 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1242 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1243 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1244 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1245 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1246 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1247 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1248 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1249 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1250 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1251 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1252 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1254 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1257 return IWM_SCD_BASE + 0x18 + chnl * 4;
1258 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1261 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1264 return IWM_SCD_BASE + 0x68 + chnl * 4;
1265 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1268 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1271 return IWM_SCD_BASE + 0x10c + chnl * 4;
1272 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1275 /*********************** END TX SCHEDULER *************************************/
1277 /* Oscillator clock */
1278 #define IWM_OSC_CLK (0xa04068)
1279 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1289 /****************************/
1290 /* Flow Handler Definitions */
1291 /****************************/
1294 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1295 * Addresses are offsets from device's PCI hardware base address.
1297 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1298 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1301 * Keep-Warm (KW) buffer base address.
1303 * Driver must allocate a 4KByte buffer that is for keeping the
1304 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1305 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1306 * from going into a power-savings mode that would cause higher DRAM latency,
1307 * and possible data over/under-runs, before all Tx/Rx is complete.
1309 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1310 * of the buffer, which must be 4K aligned. Once this is set up, the device
1311 * automatically invokes keep-warm accesses when normal accesses might not
1312 * be sufficient to maintain fast DRAM response.
1315 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1317 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1321 * TFD Circular Buffers Base (CBBC) addresses
1323 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1324 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1325 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1326 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1327 * aligned (address bits 0-7 must be 0).
1328 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1329 * for them are in different places.
1331 * Bit fields in each pointer register:
1332 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1334 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1335 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1336 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1337 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1338 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1339 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1341 /* Find TFD CB base pointer for given queue */
1342 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1345 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1347 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1348 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1353 * Rx SRAM Control and Status Registers (RSCSR)
1355 * These registers provide handshake between driver and device for the Rx queue
1356 * (this queue handles *all* command responses, notifications, Rx data, etc.
1357 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1358 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1359 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1360 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1361 * mapping between RBDs and RBs.
1363 * Driver must allocate host DRAM memory for the following, and set the
1364 * physical address of each into device registers:
1366 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1367 * entries (although any power of 2, up to 4096, is selectable by driver).
1368 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1369 * (typically 4K, although 8K or 16K are also selectable by driver).
1370 * Driver sets up RB size and number of RBDs in the CB via Rx config
1371 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1373 * Bit fields within one RBD:
1374 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1376 * Driver sets physical address [35:8] of base of RBD circular buffer
1377 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1379 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1380 * (RBs) have been filled, via a "write pointer", actually the index of
1381 * the RB's corresponding RBD within the circular buffer. Driver sets
1382 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1384 * Bit fields in lower dword of Rx status buffer (upper dword not used
1386 * 31-12: Not used by driver
1387 * 11- 0: Index of last filled Rx buffer descriptor
1388 * (device writes, driver reads this value)
1390 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1391 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1392 * and update the device's "write" index register,
1393 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1395 * This "write" index corresponds to the *next* RBD that the driver will make
1396 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1397 * the circular buffer. This value should initially be 0 (before preparing any
1398 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1399 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1400 * "read" index has advanced past 1! See below).
1401 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1403 * As the device fills RBs (referenced from contiguous RBDs within the circular
1404 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1405 * to tell the driver the index of the latest filled RBD. The driver must
1406 * read this "read" index from DRAM after receiving an Rx interrupt from device
1408 * The driver must also internally keep track of a third index, which is the
1409 * next RBD to process. When receiving an Rx interrupt, driver should process
1410 * all filled but unprocessed RBs up to, but not including, the RB
1411 * corresponding to the "read" index. For example, if "read" index becomes "1",
1412 * driver may process the RB pointed to by RBD 0. Depending on volume of
1413 * traffic, there may be many RBs to process.
1415 * If read index == write index, device thinks there is no room to put new data.
1416 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1417 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1418 * and "read" indexes; that is, make sure that there are no more than 254
1419 * buffers waiting to be filled.
1421 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1422 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1423 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1426 * Physical base address of 8-byte Rx Status buffer.
1428 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1430 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1433 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1435 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1437 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1440 * Rx write pointer (index, really!).
1442 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1443 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1445 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1446 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1448 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1449 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1452 * Rx Config/Status Registers (RCSR)
1453 * Rx Config Reg for channel 0 (only channel used)
1455 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1456 * normal operation (see bit fields).
1458 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1459 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1460 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1463 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1464 * '10' operate normally
1466 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1467 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1469 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1470 * '10' 12K, '11' 16K.
1472 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1473 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1474 * typical value 0x10 (about 1/2 msec)
1477 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1478 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1479 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1481 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1482 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1483 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1485 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1486 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1487 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1488 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1489 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1490 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1492 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1493 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1494 #define IWM_RX_RB_TIMEOUT (0x11)
1496 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1497 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1498 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1500 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1501 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1502 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1503 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1505 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1506 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1507 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1510 * Rx Shared Status Registers (RSSR)
1512 * After stopping Rx DMA channel (writing 0 to
1513 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1514 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1517 * 24: 1 = Channel 0 is idle
1519 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1520 * contain default values that should not be altered by the driver.
1522 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1523 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1525 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1526 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1527 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1528 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1530 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1532 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1534 /* 9000 rx series registers */
1536 #define IWM_RFH_Q0_FRBDCB_BA_LSB 0xa08000
1537 #define IWM_RFH_Q_FRBDCB_BA_LSB (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
1538 /* Write index table */
1539 #define IWM_RFH_Q0_FRBDCB_WIDX 0xa08080
1540 #define IWM_RFH_Q_FRBDCB_WIDX (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)
1541 /* Write index table - shadow registers */
1542 #define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1c80
1543 #define IWM_RFH_Q_FRBDCB_WIDX_TRG (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
1544 /* Read index table */
1545 #define IWM_RFH_Q0_FRBDCB_RIDX 0xa080c0
1546 #define IWM_RFH_Q_FRBDCB_RIDX (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)
1547 /* Used list table */
1548 #define IWM_RFH_Q0_URBDCB_BA_LSB 0xa08100
1549 #define IWM_RFH_Q_URBDCB_BA_LSB (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
1550 /* Write index table */
1551 #define IWM_RFH_Q0_URBDCB_WIDX 0xa08180
1552 #define IWM_RFH_Q_URBDCB_WIDX (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)
1554 #define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xa08200
1555 #define IWM_RFH_Q_URBD_STTS_WPTR_LSB (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
1557 #define IWM_RFH_GEN_STATUS 0xa09808
1558 #define IWM_RXF_DMA_IDLE 0x80000000
1560 /* DMA configuration */
1561 #define IWM_RFH_RXF_DMA_CFG 0xa09820
1562 #define IWM_RFH_RXF_DMA_RB_SIZE_1K 0x00010000
1563 #define IWM_RFH_RXF_DMA_RB_SIZE_2K 0x00020000
1564 #define IWM_RFH_RXF_DMA_RB_SIZE_4K 0x00040000
1565 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 0x00900000
1566 #define IWM_RFH_RXF_DMA_MIN_RB_4_8 0x03000000
1567 #define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK 0x04000000
1568 #define IWM_RFH_DMA_EN_ENABLE_VAL 0x80000000
1570 #define IWM_RFH_GEN_CFG 0xa09800
1571 #define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP 0x00000001
1572 #define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP 0x00000002
1573 #define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
1574 #define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
1576 #define IWM_RFH_RXF_RXQ_ACTIVE 0xa0980c
1578 /* end of 9000 rx series registers */
1580 /* TFDB Area - TFDs buffer table */
1581 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1582 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1583 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1584 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1585 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1588 * Transmit DMA Channel Control/Status Registers (TCSR)
1590 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1591 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1592 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1594 * To use a Tx DMA channel, driver must initialize its
1595 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1597 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1598 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1600 * All other bits should be 0.
1603 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1604 * '10' operate normally
1605 * 29- 4: Reserved, set to "0"
1606 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1607 * 2- 0: Reserved, set to "0"
1609 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1610 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1612 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1613 #define IWM_FH_TCSR_CHNL_NUM (8)
1615 /* TCSR: tx_config register values */
1616 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1617 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1618 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1619 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1620 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1621 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1623 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1624 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1626 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1627 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1629 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1630 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1631 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1633 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1634 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1635 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1637 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1638 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1639 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1641 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1642 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1643 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1645 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1646 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1649 * Tx Shared Status Registers (TSSR)
1651 * After stopping Tx DMA channel (writing 0 to
1652 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1653 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1654 * (channel's buffers empty | no pending requests).
1657 * 31-24: 1 = Channel buffers empty (channel 7:0)
1658 * 23-16: 1 = No pending requests (channel 7:0)
1660 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1661 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1663 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1666 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1667 * 31: Indicates an address error when accessed to internal memory
1668 * uCode/driver must write "1" in order to clear this flag
1669 * 30: Indicates that Host did not send the expected number of dwords to FH
1670 * uCode/driver must write "1" in order to clear this flag
1671 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1672 * command was received from the scheduler while the TRB was already full
1673 * with previous command
1674 * uCode/driver must write "1" in order to clear this flag
1675 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1676 * bit is set, it indicates that the FH has received a full indication
1677 * from the RTC TxFIFO and the current value of the TxCredit counter was
1678 * not equal to zero. This mean that the credit mechanism was not
1679 * synchronized to the TxFIFO status
1680 * uCode/driver must write "1" in order to clear this flag
1682 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1683 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1685 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1687 /* Tx service channels */
1688 #define IWM_FH_SRVC_CHNL (9)
1689 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1690 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1691 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1692 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1694 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1695 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1698 /* Instruct FH to increment the retry count of a packet when
1699 * it is brought from the memory to TX-FIFO
1701 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1703 #define IWM_RX_QUEUE_SIZE 256
1704 #define IWM_RX_QUEUE_MASK 255
1705 #define IWM_RX_QUEUE_SIZE_LOG 8
1708 * RX related structures and functions
1710 #define IWM_RX_FREE_BUFFERS 64
1711 #define IWM_RX_LOW_WATERMARK 8
1714 * struct iwm_rb_status - reseve buffer status
1715 * host memory mapped FH registers
1716 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1717 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1718 * @finished_rb_num [0:11] - Indicates the index of the current RB
1719 * in which the last frame was written to
1720 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1721 * which was transferred
1723 struct iwm_rb_status {
1724 uint16_t closed_rb_num;
1725 uint16_t closed_fr_num;
1726 uint16_t finished_rb_num;
1727 uint16_t finished_fr_nam;
1732 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1733 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1734 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1735 IWM_TFD_QUEUE_SIZE_BC_DUP)
1736 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1737 #define IWM_NUM_OF_TBS 20
1739 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1741 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1744 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1746 * This structure contains dma address and length of transmission address
1748 * @lo: low [31:0] portion of the dma address of TX buffer
1749 * every even is unaligned on 16 bit boundary
1750 * @hi_n_len 0-3 [35:32] portion of dma
1751 * 4-15 length of the tx buffer
1761 * Transmit Frame Descriptor (TFD)
1763 * @ __reserved1[3] reserved
1764 * @ num_tbs 0-4 number of active tbs
1766 * 6-7 padding (not used)
1767 * @ tbs[20] transmit frame buffer descriptors
1770 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1771 * Both driver and device share these circular buffers, each of which must be
1772 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1774 * Driver must indicate the physical address of the base of each
1775 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1777 * Each TFD contains pointer/size information for up to 20 data buffers
1778 * in host DRAM. These buffers collectively contain the (one) frame described
1779 * by the TFD. Each buffer must be a single contiguous block of memory within
1780 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1781 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1782 * Tx frame, up to 8 KBytes in size.
1784 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1787 uint8_t __reserved1[3];
1789 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1793 /* Keep Warm Size */
1794 #define IWM_KW_SIZE 0x1000 /* 4k */
1796 /* Fixed (non-configurable) rx data from phy */
1799 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1800 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1801 * @tfd_offset 0-12 - tx command byte count
1802 * 12-16 - station index
1804 struct iwm_agn_scd_bc_tbl {
1805 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1813 * BEGIN mvm/fw-api.h
1816 /* Maximum number of Tx queues. */
1817 #define IWM_MAX_QUEUES 31
1819 /* Tx queue numbers */
1821 IWM_OFFCHANNEL_QUEUE = 8,
1831 IWM_TX_FIFO_MCAST = 5,
1832 IWM_TX_FIFO_CMD = 7,
1835 #define IWM_STATION_COUNT 16
1840 IWM_REPLY_ERROR = 0x2,
1842 IWM_INIT_COMPLETE_NOTIF = 0x4,
1844 /* PHY context commands */
1845 IWM_PHY_CONTEXT_CMD = 0x8,
1848 /* UMAC scan commands */
1849 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1850 IWM_SCAN_CFG_CMD = 0xc,
1851 IWM_SCAN_REQ_UMAC = 0xd,
1852 IWM_SCAN_ABORT_UMAC = 0xe,
1853 IWM_SCAN_COMPLETE_UMAC = 0xf,
1856 IWM_ADD_STA_KEY = 0x17,
1858 IWM_REMOVE_STA = 0x19,
1862 IWM_TXPATH_FLUSH = 0x1e,
1863 IWM_MGMT_MCAST_KEY = 0x1f,
1865 /* scheduler config */
1866 IWM_SCD_QUEUE_CFG = 0x1d,
1871 /* MAC and Binding commands */
1872 IWM_MAC_CONTEXT_CMD = 0x28,
1873 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1874 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1875 IWM_BINDING_CONTEXT_CMD = 0x2b,
1876 IWM_TIME_QUOTA_CMD = 0x2c,
1877 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1881 /* paging block to FW cpu2 */
1882 IWM_FW_PAGING_BLOCK_CMD = 0x4f,
1885 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1886 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1887 IWM_HOT_SPOT_CMD = 0x53,
1888 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1889 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1890 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1891 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1892 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1895 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1896 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1897 IWM_PHY_DB_CMD = 0x6c,
1899 /* Power - legacy power table command */
1900 IWM_POWER_TABLE_CMD = 0x77,
1901 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1902 IWM_LTR_CONFIG = 0xee,
1904 /* Thermal Throttling*/
1905 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1908 IWM_NVM_ACCESS_CMD = 0x88,
1910 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1912 IWM_BEACON_NOTIFICATION = 0x90,
1913 IWM_BEACON_TEMPLATE_CMD = 0x91,
1914 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1915 IWM_BT_CONFIG = 0x9b,
1916 IWM_STATISTICS_NOTIFICATION = 0x9d,
1917 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1919 /* RF-KILL commands and notifications */
1920 IWM_CARD_STATE_CMD = 0xa0,
1921 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1923 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1925 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1927 /* Power - new power table command */
1928 IWM_MAC_PM_POWER_TABLE = 0xa9,
1930 IWM_REPLY_RX_PHY_CMD = 0xc0,
1931 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1932 IWM_BA_NOTIF = 0xc5,
1934 /* Location Aware Regulatory */
1935 IWM_MCC_UPDATE_CMD = 0xc8,
1936 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1939 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1940 IWM_BT_COEX_PROT_ENV = 0xcd,
1941 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1942 IWM_BT_COEX_CI = 0x5d,
1944 IWM_REPLY_SF_CFG_CMD = 0xd1,
1945 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1947 /* DTS measurements */
1948 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1949 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1951 IWM_REPLY_DEBUG_CMD = 0xf0,
1952 IWM_DEBUG_LOG_MSG = 0xf7,
1954 IWM_MCAST_FILTER_CMD = 0xd0,
1956 /* D3 commands/notifications */
1957 IWM_D3_CONFIG_CMD = 0xd3,
1958 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1959 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1960 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1962 /* for WoWLAN in particular */
1963 IWM_WOWLAN_PATTERNS = 0xe0,
1964 IWM_WOWLAN_CONFIGURATION = 0xe1,
1965 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1966 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1967 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1968 IWM_WOWLAN_GET_STATUSES = 0xe5,
1969 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1971 /* and for NetDetect */
1972 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1973 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1974 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1975 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1976 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1979 enum iwm_phy_ops_subcmd_ids {
1980 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0,
1981 IWM_CTDP_CONFIG_CMD = 0x03,
1982 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04,
1983 IWM_CT_KILL_NOTIFICATION = 0xFE,
1984 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF,
1987 /* command groups */
1989 IWM_LEGACY_GROUP = 0x0,
1990 IWM_LONG_GROUP = 0x1,
1991 IWM_SYSTEM_GROUP = 0x2,
1992 IWM_MAC_CONF_GROUP = 0x3,
1993 IWM_PHY_OPS_GROUP = 0x4,
1994 IWM_DATA_PATH_GROUP = 0x5,
1995 IWM_PROT_OFFLOAD_GROUP = 0xb,
1999 * struct iwm_cmd_response - generic response struct for most commands
2000 * @status: status of the command asked, changes for each one
2002 struct iwm_cmd_response {
2007 * struct iwm_tx_ant_cfg_cmd
2008 * @valid: valid antenna configuration
2010 struct iwm_tx_ant_cfg_cmd {
2015 * struct iwm_reduce_tx_power_cmd - TX power reduction command
2016 * IWM_REDUCE_TX_POWER_CMD = 0x9f
2017 * @flags: (reserved for future implementation)
2018 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
2019 * @pwr_restriction: TX power restriction in dBms.
2021 struct iwm_reduce_tx_power_cmd {
2023 uint8_t mac_context_id;
2024 uint16_t pwr_restriction;
2025 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
2027 enum iwm_dev_tx_power_cmd_mode {
2028 IWM_TX_POWER_MODE_SET_MAC = 0,
2029 IWM_TX_POWER_MODE_SET_DEVICE = 1,
2030 IWM_TX_POWER_MODE_SET_CHAINS = 2,
2031 IWM_TX_POWER_MODE_SET_ACK = 3,
2032 }; /* TX_POWER_REDUCED_FLAGS_TYPE_API_E_VER_4 */;
2034 #define IWM_NUM_CHAIN_LIMITS 2
2035 #define IWM_NUM_SUB_BANDS 5
2038 * struct iwm_dev_tx_power_cmd - TX power reduction command
2039 * @set_mode: see &enum iwl_dev_tx_power_cmd_mode
2040 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
2041 * @pwr_restriction: TX power restriction in 1/8 dBms.
2042 * @dev_24: device TX power restriction in 1/8 dBms
2043 * @dev_52_low: device TX power restriction upper band - low
2044 * @dev_52_high: device TX power restriction upper band - high
2045 * @per_chain_restriction: per chain restrictions
2047 struct iwm_dev_tx_power_cmd_v3 {
2049 uint32_t mac_context_id;
2050 uint16_t pwr_restriction;
2052 uint16_t dev_52_low;
2053 uint16_t dev_52_high;
2054 uint16_t per_chain_restriction[IWM_NUM_CHAIN_LIMITS][IWM_NUM_SUB_BANDS];
2055 } __packed; /* TX_REDUCED_POWER_API_S_VER_3 */
2057 #define IWM_DEV_MAX_TX_POWER 0x7FFF
2060 * struct iwm_dev_tx_power_cmd - TX power reduction command
2061 * @v3: version 3 of the command, embedded here for easier software handling
2062 * @enable_ack_reduction: enable or disable close range ack TX power
2065 struct iwm_dev_tx_power_cmd {
2066 /* v4 is just an extension of v3 - keep this here */
2067 struct iwm_dev_tx_power_cmd_v3 v3;
2068 uint8_t enable_ack_reduction;
2069 uint8_t reserved[3];
2070 } __packed; /* TX_REDUCED_POWER_API_S_VER_4 */
2073 * Calibration control struct.
2074 * Sent as part of the phy configuration command.
2075 * @flow_trigger: bitmap for which calibrations to perform according to
2077 * @event_trigger: bitmap for which calibrations to perform according to
2080 struct iwm_calib_ctrl {
2081 uint32_t flow_trigger;
2082 uint32_t event_trigger;
2085 /* This enum defines the bitmap of various calibrations to enable in both
2086 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
2088 enum iwm_calib_cfg {
2089 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
2090 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
2091 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
2092 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
2093 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
2094 IWM_CALIB_CFG_DC_IDX = (1 << 5),
2095 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
2096 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
2097 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
2098 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
2099 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
2100 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
2101 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
2102 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
2103 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
2104 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
2105 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
2106 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
2107 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
2111 * Phy configuration command.
2113 struct iwm_phy_cfg_cmd {
2115 struct iwm_calib_ctrl calib_control;
2118 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
2119 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
2120 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
2121 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
2122 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
2123 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
2124 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
2125 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
2126 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
2127 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
2130 /* Target of the IWM_NVM_ACCESS_CMD */
2132 IWM_NVM_ACCESS_TARGET_CACHE = 0,
2133 IWM_NVM_ACCESS_TARGET_OTP = 1,
2134 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
2137 /* Section types for IWM_NVM_ACCESS_CMD */
2139 IWM_NVM_SECTION_TYPE_SW = 1,
2140 IWM_NVM_SECTION_TYPE_REGULATORY = 3,
2141 IWM_NVM_SECTION_TYPE_CALIBRATION = 4,
2142 IWM_NVM_SECTION_TYPE_PRODUCTION = 5,
2143 IWM_NVM_SECTION_TYPE_REGULATORY_SDP = 8,
2144 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
2145 IWM_NVM_SECTION_TYPE_PHY_SKU = 12,
2146 IWM_NVM_MAX_NUM_SECTIONS = 13,
2150 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2151 * @op_code: 0 - read, 1 - write
2152 * @target: IWM_NVM_ACCESS_TARGET_*
2153 * @type: IWM_NVM_SECTION_TYPE_*
2154 * @offset: offset in bytes into the section
2155 * @length: in bytes, to read/write
2156 * @data: if write operation, the data to write. On read its empty
2158 struct iwm_nvm_access_cmd {
2165 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2167 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */
2170 * struct iwm_fw_paging_cmd - paging layout
2172 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f)
2174 * Send to FW the paging layout in the driver.
2176 * @flags: various flags for the command
2177 * @block_size: the block size in powers of 2
2178 * @block_num: number of blocks specified in the command.
2179 * @device_phy_addr: virtual addresses from device side
2181 struct iwm_fw_paging_cmd {
2183 uint32_t block_size;
2185 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS];
2186 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */
2191 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload
2194 enum iwm_fw_item_id {
2195 IWM_FW_ITEM_ID_PAGING = 3,
2199 * struct iwm_fw_get_item_cmd - get an item from the fw
2201 struct iwm_fw_get_item_cmd {
2203 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */
2206 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2207 * @offset: offset in bytes into the section
2208 * @length: in bytes, either how much was written or read
2209 * @type: IWM_NVM_SECTION_TYPE_*
2210 * @status: 0 for success, fail otherwise
2211 * @data: if read operation, the data returned. Empty on write.
2213 struct iwm_nvm_access_resp {
2219 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2223 /* alive response is_valid values */
2224 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2225 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2227 /* alive response ver_type values */
2230 IWM_FW_TYPE_PROT = 1,
2232 IWM_FW_TYPE_WOWLAN = 3,
2233 IWM_FW_TYPE_TIMING = 4,
2234 IWM_FW_TYPE_WIPAN = 5
2237 /* alive response ver_subtype values */
2239 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2240 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2241 IWM_FW_SUBTYPE_REDUCED = 2,
2242 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2243 IWM_FW_SUBTYPE_WOWLAN = 4,
2244 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2245 IWM_FW_SUBTYPE_WIPAN = 6,
2246 IWM_FW_SUBTYPE_INITIALIZE = 9
2249 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2250 #define IWM_ALIVE_STATUS_OK 0xCAFE
2252 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2254 struct iwm_lmac_alive {
2255 uint32_t ucode_major;
2256 uint32_t ucode_minor;
2257 uint8_t ver_subtype;
2262 uint32_t error_event_table_ptr; /* SRAM address for error log */
2263 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2264 uint32_t cpu_register_ptr;
2265 uint32_t dbgm_config_ptr;
2266 uint32_t alive_counter_ptr;
2267 uint32_t scd_base_ptr; /* SRAM address for SCD */
2268 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2269 uint32_t st_fwrd_size;
2270 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */
2272 struct iwm_umac_alive {
2273 uint32_t umac_major; /* UMAC version: major */
2274 uint32_t umac_minor; /* UMAC version: minor */
2275 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2276 uint32_t dbg_print_buff_addr;
2277 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */
2279 struct iwm_alive_resp_v3 {
2282 struct iwm_lmac_alive lmac_data;
2283 struct iwm_umac_alive umac_data;
2284 } __packed; /* ALIVE_RES_API_S_VER_3 */
2286 struct iwm_alive_resp {
2289 struct iwm_lmac_alive lmac_data[2];
2290 struct iwm_umac_alive umac_data;
2291 } __packed; /* ALIVE_RES_API_S_VER_4 */
2293 /* Error response/notification */
2295 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2296 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2297 IWM_FW_ERR_SERVICE = 0x2,
2298 IWM_FW_ERR_ARC_MEMORY = 0x3,
2299 IWM_FW_ERR_ARC_CODE = 0x4,
2300 IWM_FW_ERR_WATCH_DOG = 0x5,
2301 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2302 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2303 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2304 IWM_FW_ERR_UNEXPECTED = 0xFE,
2305 IWM_FW_ERR_FATAL = 0xFF
2309 * struct iwm_error_resp - FW error indication
2310 * ( IWM_REPLY_ERROR = 0x2 )
2311 * @error_type: one of IWM_FW_ERR_*
2312 * @cmd_id: the command ID for which the error occurred
2313 * @bad_cmd_seq_num: sequence number of the erroneous command
2314 * @error_service: which service created the error, applicable only if
2315 * error_type = 2, otherwise 0
2316 * @timestamp: TSF in usecs.
2318 struct iwm_error_resp {
2319 uint32_t error_type;
2322 uint16_t bad_cmd_seq_num;
2323 uint32_t error_service;
2328 /* Common PHY, MAC and Bindings definitions */
2330 #define IWM_MAX_MACS_IN_BINDING (3)
2331 #define IWM_MAX_BINDINGS (4)
2332 #define IWM_AUX_BINDING_INDEX (3)
2333 #define IWM_MAX_PHYS (4)
2335 /* Used to extract ID and color from the context dword */
2336 #define IWM_FW_CTXT_ID_POS (0)
2337 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2338 #define IWM_FW_CTXT_COLOR_POS (8)
2339 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2340 #define IWM_FW_CTXT_INVALID (0xffffffff)
2342 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2343 (_color << IWM_FW_CTXT_COLOR_POS))
2345 /* Possible actions on PHYs, MACs and Bindings */
2347 IWM_FW_CTXT_ACTION_STUB = 0,
2348 IWM_FW_CTXT_ACTION_ADD,
2349 IWM_FW_CTXT_ACTION_MODIFY,
2350 IWM_FW_CTXT_ACTION_REMOVE,
2351 IWM_FW_CTXT_ACTION_NUM
2352 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2356 /* Time Event types, according to MAC type */
2357 enum iwm_time_event_type {
2358 /* BSS Station Events */
2359 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2360 IWM_TE_BSS_STA_ASSOC,
2361 IWM_TE_BSS_EAP_DHCP_PROT,
2362 IWM_TE_BSS_QUIET_PERIOD,
2364 /* P2P Device Events */
2365 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2366 IWM_TE_P2P_DEVICE_LISTEN,
2367 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2368 IWM_TE_P2P_DEVICE_FULL_SCAN,
2370 /* P2P Client Events */
2371 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2372 IWM_TE_P2P_CLIENT_ASSOC,
2373 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2376 IWM_TE_P2P_GO_ASSOC_PROT,
2377 IWM_TE_P2P_GO_REPETITIVE_NOA,
2378 IWM_TE_P2P_GO_CT_WINDOW,
2380 /* WiDi Sync Events */
2381 IWM_TE_WIDI_TX_SYNC,
2384 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2388 /* Time event - defines for command API v1 */
2391 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2392 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2393 * the first fragment is scheduled.
2394 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2395 * the first 2 fragments are scheduled.
2396 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2397 * number of fragments are valid.
2399 * Other than the constant defined above, specifying a fragmentation value 'x'
2400 * means that the event can be fragmented but only the first 'x' will be
2404 IWM_TE_V1_FRAG_NONE = 0,
2405 IWM_TE_V1_FRAG_SINGLE = 1,
2406 IWM_TE_V1_FRAG_DUAL = 2,
2407 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2410 /* If a Time Event can be fragmented, this is the max number of fragments */
2411 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2412 /* Repeat the time event endlessly (until removed) */
2413 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2414 /* If a Time Event has bounded repetitions, this is the maximal value */
2415 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2417 /* Time Event dependencies: none, on another TE, or in a specific time */
2419 IWM_TE_V1_INDEPENDENT = 0,
2420 IWM_TE_V1_DEP_OTHER = (1 << 0),
2421 IWM_TE_V1_DEP_TSF = (1 << 1),
2422 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2423 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2426 * @IWM_TE_V1_NOTIF_NONE: no notifications
2427 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2428 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2429 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2430 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2431 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2432 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2433 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2434 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2436 * Supported Time event notifications configuration.
2437 * A notification (both event and fragment) includes a status indicating weather
2438 * the FW was able to schedule the event or not. For fragment start/end
2439 * notification the status is always success. There is no start/end fragment
2440 * notification for monolithic events.
2443 IWM_TE_V1_NOTIF_NONE = 0,
2444 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2445 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2446 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2447 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2448 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2449 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2450 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2451 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2452 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2453 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2455 /* Time event - defines for command API */
2458 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2459 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2460 * the first fragment is scheduled.
2461 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2462 * the first 2 fragments are scheduled.
2463 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2464 * number of fragments are valid.
2466 * Other than the constant defined above, specifying a fragmentation value 'x'
2467 * means that the event can be fragmented but only the first 'x' will be
2471 IWM_TE_V2_FRAG_NONE = 0,
2472 IWM_TE_V2_FRAG_SINGLE = 1,
2473 IWM_TE_V2_FRAG_DUAL = 2,
2474 IWM_TE_V2_FRAG_MAX = 0xfe,
2475 IWM_TE_V2_FRAG_ENDLESS = 0xff
2478 /* Repeat the time event endlessly (until removed) */
2479 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2480 /* If a Time Event has bounded repetitions, this is the maximal value */
2481 #define IWM_TE_V2_REPEAT_MAX 0xfe
2483 #define IWM_TE_V2_PLACEMENT_POS 12
2484 #define IWM_TE_V2_ABSENCE_POS 15
2486 /* Time event policy values
2487 * A notification (both event and fragment) includes a status indicating weather
2488 * the FW was able to schedule the event or not. For fragment start/end
2489 * notification the status is always success. There is no start/end fragment
2490 * notification for monolithic events.
2492 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2493 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2494 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2495 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2496 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2497 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2498 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2499 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2500 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2501 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2502 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2503 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2504 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2507 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2509 /* notifications (event start/stop, fragment start/stop) */
2510 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2511 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2512 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2513 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2515 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2516 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2517 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2518 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2520 IWM_TE_V2_NOTIF_MSK = 0xff,
2522 /* placement characteristics */
2523 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2524 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2525 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2527 /* are we present or absent during the Time Event. */
2528 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2532 * struct iwm_time_event_cmd_api - configuring Time Events
2533 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2534 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2535 * ( IWM_TIME_EVENT_CMD = 0x29 )
2536 * @id_and_color: ID and color of the relevant MAC
2537 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2538 * @id: this field has two meanings, depending on the action:
2539 * If the action is ADD, then it means the type of event to add.
2540 * For all other actions it is the unique event ID assigned when the
2541 * event was added by the FW.
2542 * @apply_time: When to start the Time Event (in GP2)
2543 * @max_delay: maximum delay to event's start (apply time), in TU
2544 * @depends_on: the unique ID of the event we depend on (if any)
2545 * @interval: interval between repetitions, in TU
2546 * @duration: duration of event in TU
2547 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2548 * @max_frags: maximal number of fragments the Time Event can be divided to
2549 * @policy: defines whether uCode shall notify the host or other uCode modules
2550 * on event and/or fragment start and/or end
2551 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2552 * IWM_TE_EVENT_SOCIOPATHIC
2553 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2555 struct iwm_time_event_cmd {
2556 /* COMMON_INDEX_HDR_API_S_VER_1 */
2557 uint32_t id_and_color;
2560 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2561 uint32_t apply_time;
2563 uint32_t depends_on;
2569 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2572 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2573 * @status: bit 0 indicates success, all others specify errors
2574 * @id: the Time Event type
2575 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2576 * @id_and_color: ID and color of the relevant MAC
2578 struct iwm_time_event_resp {
2582 uint32_t id_and_color;
2583 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2586 * struct iwm_time_event_notif - notifications of time event start/stop
2587 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2588 * @timestamp: action timestamp in GP2
2589 * @session_id: session's unique id
2590 * @unique_id: unique id of the Time Event itself
2591 * @id_and_color: ID and color of the relevant MAC
2592 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2593 * @status: true if scheduled, false otherwise (not executed)
2595 struct iwm_time_event_notif {
2597 uint32_t session_id;
2599 uint32_t id_and_color;
2602 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2605 /* Bindings and Time Quota */
2608 * struct iwm_binding_cmd - configuring bindings
2609 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2610 * @id_and_color: ID and color of the relevant Binding
2611 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2612 * @macs: array of MAC id and colors which belong to the binding
2613 * @phy: PHY id and color which belongs to the binding
2615 struct iwm_binding_cmd {
2616 /* COMMON_INDEX_HDR_API_S_VER_1 */
2617 uint32_t id_and_color;
2619 /* IWM_BINDING_DATA_API_S_VER_1 */
2620 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2622 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2624 /* The maximal number of fragments in the FW's schedule session */
2625 #define IWM_MAX_QUOTA 128
2628 * struct iwm_time_quota_data - configuration of time quota per binding
2629 * @id_and_color: ID and color of the relevant Binding
2630 * @quota: absolute time quota in TU. The scheduler will try to divide the
2631 * remainig quota (after Time Events) according to this quota.
2632 * @max_duration: max uninterrupted context duration in TU
2634 struct iwm_time_quota_data {
2635 uint32_t id_and_color;
2637 uint32_t max_duration;
2638 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2641 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2642 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2643 * @quotas: allocations per binding
2645 struct iwm_time_quota_cmd {
2646 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2647 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2652 /* Supported bands */
2653 #define IWM_PHY_BAND_5 (0)
2654 #define IWM_PHY_BAND_24 (1)
2656 /* Supported channel width, vary if there is VHT support */
2657 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2658 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2659 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2660 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2663 * Control channel position:
2664 * For legacy set bit means upper channel, otherwise lower.
2665 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2666 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2669 * 40Mhz |_______|_______|
2670 * 80Mhz |_______|_______|_______|_______|
2671 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2672 * code 011 010 001 000 | 100 101 110 111
2674 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2675 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2676 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2677 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2678 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2679 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2680 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2681 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2684 * @band: IWM_PHY_BAND_*
2685 * @channel: channel number
2686 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2687 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2689 struct iwm_fw_channel_info {
2696 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2697 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2698 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2699 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2700 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2701 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2702 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2703 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2704 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2705 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2706 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2707 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2708 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2709 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2710 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2711 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2712 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2713 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2714 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2715 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2716 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2718 /* TODO: fix the value, make it depend on firmware at runtime? */
2719 #define IWM_NUM_PHY_CTX 3
2721 /* TODO: complete missing documentation */
2723 * struct iwm_phy_context_cmd - config of the PHY context
2724 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2725 * @id_and_color: ID and color of the relevant Binding
2726 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2727 * @apply_time: 0 means immediate apply and context switch.
2728 * other value means apply new params after X usecs
2729 * @tx_param_color: ???
2731 * @txchain_info: ???
2732 * @rxchain_info: ???
2733 * @acquisition_data: ???
2734 * @dsp_cfg_flags: set to 0
2736 struct iwm_phy_context_cmd {
2737 /* COMMON_INDEX_HDR_API_S_VER_1 */
2738 uint32_t id_and_color;
2740 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2741 uint32_t apply_time;
2742 uint32_t tx_param_color;
2743 struct iwm_fw_channel_info ci;
2744 uint32_t txchain_info;
2745 uint32_t rxchain_info;
2746 uint32_t acquisition_data;
2747 uint32_t dsp_cfg_flags;
2748 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2750 #define IWM_RX_INFO_PHY_CNT 8
2751 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2752 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2753 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2754 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2755 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2756 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2757 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2759 #define IWM_RX_INFO_AGC_IDX 1
2760 #define IWM_RX_INFO_RSSI_AB_IDX 2
2761 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2762 #define IWM_OFDM_AGC_A_POS 0
2763 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2764 #define IWM_OFDM_AGC_B_POS 7
2765 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2766 #define IWM_OFDM_AGC_CODE_POS 20
2767 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2768 #define IWM_OFDM_RSSI_A_POS 0
2769 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2770 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2771 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2772 #define IWM_OFDM_RSSI_B_POS 16
2773 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2774 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2777 * struct iwm_rx_phy_info - phy info
2778 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2779 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2780 * @cfg_phy_cnt: configurable DSP phy data byte count
2781 * @stat_id: configurable DSP phy data set ID
2783 * @system_timestamp: GP2 at on air rise
2784 * @timestamp: TSF at on air rise
2785 * @beacon_time_stamp: beacon at on-air rise
2786 * @phy_flags: general phy flags: band, modulation, ...
2787 * @channel: channel number
2788 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2789 * @rate_n_flags: IWM_RATE_MCS_*
2790 * @byte_count: frame's byte-count
2791 * @frame_time: frame's time on the air, based on byte count and frame rate
2793 * @mac_active_msk: what MACs were active when the frame was received
2795 * Before each Rx, the device sends this data. It contains PHY information
2796 * about the reception of the packet.
2798 struct iwm_rx_phy_info {
2799 uint8_t non_cfg_phy_cnt;
2800 uint8_t cfg_phy_cnt;
2803 uint32_t system_timestamp;
2805 uint32_t beacon_time_stamp;
2807 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2809 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2813 uint32_t byte_count;
2814 uint16_t mac_active_msk;
2815 uint16_t frame_time;
2818 struct iwm_rx_mpdu_res_start {
2819 uint16_t byte_count;
2824 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2825 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2826 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2827 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2828 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2829 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2830 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2831 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2832 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2833 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2835 enum iwm_rx_phy_flags {
2836 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2837 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2838 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2839 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2840 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2841 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2842 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2843 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2844 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2845 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2849 * enum iwm_rx_status - written by fw for each Rx packet
2850 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2851 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2852 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2853 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2854 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2855 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2856 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2858 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2859 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2860 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2861 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2862 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2863 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2864 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2865 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2866 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2867 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2868 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2869 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2870 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2871 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2872 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2873 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2874 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2875 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2876 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2877 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2878 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2880 enum iwm_rx_status {
2881 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2882 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2883 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2884 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2885 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2886 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2887 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2888 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2889 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2890 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2891 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2892 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2893 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2894 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2895 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2896 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2897 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2898 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2899 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2900 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2901 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2902 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2903 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2904 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2905 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2906 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2907 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2910 enum iwm_rx_mpdu_mac_flags1 {
2911 IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK = 0x03,
2912 IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0,
2913 IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3,
2916 enum iwm_rx_mpdu_mac_flags2 {
2917 IWM_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f,
2918 IWM_RX_MPDU_MFLG2_PAD = 0x20,
2919 IWM_RX_MPDU_MFLG2_AMSDU = 0x40,
2922 enum iwm_rx_mpdu_phy_info {
2923 IWM_RX_MPDU_PHY_AMPDU = (1 << 5),
2924 IWM_RX_MPDU_PHY_AMPDU_TOGGLE = (1 << 6),
2925 IWM_RX_MPDU_PHY_SHORT_PREAMBLE = (1 << 7),
2926 IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY = (1 << 7),
2927 IWM_RX_MPDU_PHY_TSF_OVERLOAD = (1 << 8),
2930 struct iwm_rx_mpdu_desc_v1 {
2936 uint32_t filter_match;
2939 uint32_t rate_n_flags;
2943 uint8_t mac_context;
2944 uint32_t gp2_on_air_rise;
2946 uint64_t tsf_on_air_rise;
2954 struct iwm_rx_mpdu_desc {
2960 uint8_t mac_phy_idx;
2963 uint16_t l3l4_flags;
2967 uint8_t hash_filter;
2968 uint8_t sta_id_flags;
2969 uint32_t reorder_data;
2970 struct iwm_rx_mpdu_desc_v1 v1;
2974 * struct iwm_radio_version_notif - information on the radio version
2975 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2980 struct iwm_radio_version_notif {
2981 uint32_t radio_flavor;
2982 uint32_t radio_step;
2983 uint32_t radio_dash;
2984 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2986 enum iwm_card_state_flags {
2987 IWM_CARD_ENABLED = 0x00,
2988 IWM_HW_CARD_DISABLED = 0x01,
2989 IWM_SW_CARD_DISABLED = 0x02,
2990 IWM_CT_KILL_CARD_DISABLED = 0x04,
2991 IWM_HALT_CARD_DISABLED = 0x08,
2992 IWM_CARD_DISABLED_MSK = 0x0f,
2993 IWM_CARD_IS_RX_ON = 0x10,
2997 * struct iwm_radio_version_notif - information on the radio version
2998 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2999 * @flags: %iwm_card_state_flags
3001 struct iwm_card_state_notif {
3003 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
3006 * struct iwm_missed_beacons_notif - information on missed beacons
3007 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
3008 * @mac_id: interface ID
3009 * @consec_missed_beacons_since_last_rx: number of consecutive missed
3010 * beacons since last RX.
3011 * @consec_missed_beacons: number of consecutive missed beacons
3012 * @num_expected_beacons:
3013 * @num_recvd_beacons:
3015 struct iwm_missed_beacons_notif {
3017 uint32_t consec_missed_beacons_since_last_rx;
3018 uint32_t consec_missed_beacons;
3019 uint32_t num_expected_beacons;
3020 uint32_t num_recvd_beacons;
3021 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
3024 * struct iwm_mfuart_load_notif - mfuart image version & status
3025 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
3026 * @installed_ver: installed image version
3027 * @external_ver: external image version
3028 * @status: MFUART loading status
3029 * @duration: MFUART loading time
3031 struct iwm_mfuart_load_notif {
3032 uint32_t installed_ver;
3033 uint32_t external_ver;
3036 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
3039 * struct iwm_set_calib_default_cmd - set default value for calibration.
3040 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
3041 * @calib_index: the calibration to set value for
3043 * @data: the value to set for the calibration result
3045 struct iwm_set_calib_default_cmd {
3046 uint16_t calib_index;
3049 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
3051 #define IWM_MAX_PORT_ID_NUM 2
3052 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
3055 * struct iwm_mcast_filter_cmd - configure multicast filter.
3056 * @filter_own: Set 1 to filter out multicast packets sent by station itself
3057 * @port_id: Multicast MAC addresses array specifier. This is a strange way
3058 * to identify network interface adopted in host-device IF.
3059 * It is used by FW as index in array of addresses. This array has
3060 * IWM_MAX_PORT_ID_NUM members.
3061 * @count: Number of MAC addresses in the array
3062 * @pass_all: Set 1 to pass all multicast packets.
3063 * @bssid: current association BSSID.
3064 * @addr_list: Place holder for array of MAC addresses.
3065 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
3067 struct iwm_mcast_filter_cmd {
3073 uint8_t reserved[2];
3074 uint8_t addr_list[0];
3075 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
3078 * The first MAC indices (starting from 0)
3079 * are available to the driver, AUX follows
3081 #define IWM_MAC_INDEX_AUX 4
3082 #define IWM_MAC_INDEX_MIN_DRIVER 0
3083 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3084 #define IWM_NUM_MAC_INDEX (IWM_MAC_INDEX_AUX + 1)
3086 /***********************************
3088 ***********************************/
3089 struct iwm_statistics_dbg {
3090 uint32_t burst_check;
3091 uint32_t burst_count;
3092 uint32_t wait_for_silence_timeout_cnt;
3093 uint32_t reserved[3];
3094 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
3096 struct iwm_statistics_div {
3100 uint32_t probe_time;
3103 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
3105 struct iwm_statistics_rx_non_phy {
3106 uint32_t bogus_cts; /* CTS received when not expecting CTS */
3107 uint32_t bogus_ack; /* ACK received when not expecting ACK */
3108 uint32_t non_bssid_frames; /* number of frames with BSSID that
3109 * doesn't belong to the STA BSSID */
3110 uint32_t filtered_frames; /* count frames that were dumped in the
3111 * filtering process */
3112 uint32_t non_channel_beacons; /* beacons with our bss id but not on
3113 * our serving channel */
3114 uint32_t channel_beacons; /* beacons with our bss id and in our
3115 * serving channel */
3116 uint32_t num_missed_bcon; /* number of missed beacons */
3117 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
3118 * ADC was in saturation */
3119 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
3121 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
3122 uint32_t interference_data_flag; /* flag for interference data
3123 * availability. 1 when data is
3125 uint32_t channel_load; /* counts RX Enable time in uSec */
3126 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
3127 * and CCK) counter */
3128 uint32_t beacon_rssi_a;
3129 uint32_t beacon_rssi_b;
3130 uint32_t beacon_rssi_c;
3131 uint32_t beacon_energy_a;
3132 uint32_t beacon_energy_b;
3133 uint32_t beacon_energy_c;
3134 uint32_t num_bt_kills;
3136 uint32_t directed_data_mpdu;
3137 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
3139 struct iwm_statistics_rx_phy {
3144 uint32_t overrun_err;
3145 uint32_t early_overrun_err;
3146 uint32_t crc32_good;
3147 uint32_t false_alarm_cnt;
3148 uint32_t fina_sync_err_cnt;
3149 uint32_t sfd_timeout;
3150 uint32_t fina_timeout;
3151 uint32_t unresponded_rts;
3152 uint32_t rxe_frame_limit_overrun;
3153 uint32_t sent_ack_cnt;
3154 uint32_t sent_cts_cnt;
3155 uint32_t sent_ba_rsp_cnt;
3156 uint32_t dsp_self_kill;
3157 uint32_t mh_format_err;
3158 uint32_t re_acq_main_rssi_sum;
3160 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
3162 struct iwm_statistics_rx_ht_phy {
3164 uint32_t overrun_err;
3165 uint32_t early_overrun_err;
3166 uint32_t crc32_good;
3168 uint32_t mh_format_err;
3169 uint32_t agg_crc32_good;
3170 uint32_t agg_mpdu_cnt;
3172 uint32_t unsupport_mcs;
3173 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3175 struct iwm_statistics_tx_non_phy {
3176 uint32_t preamble_cnt;
3177 uint32_t rx_detected_cnt;
3178 uint32_t bt_prio_defer_cnt;
3179 uint32_t bt_prio_kill_cnt;
3180 uint32_t few_bytes_cnt;
3181 uint32_t cts_timeout;
3182 uint32_t ack_timeout;
3183 uint32_t expected_ack_cnt;
3184 uint32_t actual_ack_cnt;
3185 uint32_t dump_msdu_cnt;
3186 uint32_t burst_abort_next_frame_mismatch_cnt;
3187 uint32_t burst_abort_missing_next_frame_cnt;
3188 uint32_t cts_timeout_collision;
3189 uint32_t ack_or_ba_timeout_collision;
3190 } __packed; /* IWM_STATISTICS_TX_NON_PHY_API_S_VER_3 */
3192 #define IWM_MAX_CHAINS 3
3194 struct iwm_statistics_tx_non_phy_agg {
3195 uint32_t ba_timeout;
3196 uint32_t ba_reschedule_frames;
3197 uint32_t scd_query_agg_frame_cnt;
3198 uint32_t scd_query_no_agg;
3199 uint32_t scd_query_agg;
3200 uint32_t scd_query_mismatch;
3201 uint32_t frame_not_ready;
3203 uint32_t bt_prio_kill;
3204 uint32_t rx_ba_rsp_cnt;
3205 int8_t txpower[IWM_MAX_CHAINS];
3208 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3210 struct iwm_statistics_tx_channel_width {
3211 uint32_t ext_cca_narrow_ch20[1];
3212 uint32_t ext_cca_narrow_ch40[2];
3213 uint32_t ext_cca_narrow_ch80[3];
3214 uint32_t ext_cca_narrow_ch160[4];
3215 uint32_t last_tx_ch_width_indx;
3216 uint32_t rx_detected_per_ch_width[4];
3217 uint32_t success_per_ch_width[4];
3218 uint32_t fail_per_ch_width[4];
3219 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3221 struct iwm_statistics_tx {
3222 struct iwm_statistics_tx_non_phy general;
3223 struct iwm_statistics_tx_non_phy_agg agg;
3224 struct iwm_statistics_tx_channel_width channel_width;
3225 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3228 struct iwm_statistics_bt_activity {
3229 uint32_t hi_priority_tx_req_cnt;
3230 uint32_t hi_priority_tx_denied_cnt;
3231 uint32_t lo_priority_tx_req_cnt;
3232 uint32_t lo_priority_tx_denied_cnt;
3233 uint32_t hi_priority_rx_req_cnt;
3234 uint32_t hi_priority_rx_denied_cnt;
3235 uint32_t lo_priority_rx_req_cnt;
3236 uint32_t lo_priority_rx_denied_cnt;
3237 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3239 struct iwm_statistics_general_v8 {
3240 uint32_t radio_temperature;
3241 uint32_t radio_voltage;
3242 struct iwm_statistics_dbg dbg;
3243 uint32_t sleep_time;
3245 uint32_t slots_idle;
3246 uint32_t ttl_timestamp;
3247 struct iwm_statistics_div slow_div;
3248 uint32_t rx_enable_counter;
3250 * num_of_sos_states:
3251 * count the number of times we have to re-tune
3252 * in order to get out of bad PHY status
3254 uint32_t num_of_sos_states;
3255 uint32_t beacon_filtered;
3256 uint32_t missed_beacons;
3257 uint8_t beacon_filter_average_energy;
3258 uint8_t beacon_filter_reason;
3259 uint8_t beacon_filter_current_energy;
3260 uint8_t beacon_filter_reserved;
3261 uint32_t beacon_filter_delta_time;
3262 struct iwm_statistics_bt_activity bt_activity;
3264 uint64_t on_time_rf;
3265 uint64_t on_time_scan;
3267 uint32_t beacon_counter[IWM_NUM_MAC_INDEX];
3268 uint8_t beacon_average_energy[IWM_NUM_MAC_INDEX];
3269 uint8_t reserved[4 - (IWM_NUM_MAC_INDEX % 4)];
3270 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_8 */
3272 struct iwm_statistics_rx {
3273 struct iwm_statistics_rx_phy ofdm;
3274 struct iwm_statistics_rx_phy cck;
3275 struct iwm_statistics_rx_non_phy general;
3276 struct iwm_statistics_rx_ht_phy ofdm_ht;
3277 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3280 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3282 * By default, uCode issues this notification after receiving a beacon
3283 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3284 * IWM_STATISTICS_CMD (0x9c), below.
3287 struct iwm_notif_statistics_v10 {
3289 struct iwm_statistics_rx rx;
3290 struct iwm_statistics_tx tx;
3291 struct iwm_statistics_general_v8 general;
3292 } __packed; /* IWM_STATISTICS_NTFY_API_S_VER_10 */
3294 #define IWM_STATISTICS_FLG_CLEAR 0x1
3295 #define IWM_STATISTICS_FLG_DISABLE_NOTIF 0x2
3297 struct iwm_statistics_cmd {
3299 } __packed; /* IWM_STATISTICS_CMD_API_S_VER_1 */
3301 /***********************************
3303 ***********************************/
3304 /* Smart Fifo state */
3306 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3310 IWM_SF_HW_NUM_STATES
3313 /* Smart Fifo possible scenario */
3314 enum iwm_sf_scenario {
3315 IWM_SF_SCENARIO_SINGLE_UNICAST,
3316 IWM_SF_SCENARIO_AGG_UNICAST,
3317 IWM_SF_SCENARIO_MULTICAST,
3318 IWM_SF_SCENARIO_BA_RESP,
3319 IWM_SF_SCENARIO_TX_RESP,
3323 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3324 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3326 /* smart FIFO default values */
3327 #define IWM_SF_W_MARK_SISO 4096
3328 #define IWM_SF_W_MARK_MIMO2 8192
3329 #define IWM_SF_W_MARK_MIMO3 6144
3330 #define IWM_SF_W_MARK_LEGACY 4096
3331 #define IWM_SF_W_MARK_SCAN 4096
3333 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3334 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3335 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3336 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3337 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3338 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3339 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3340 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3341 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3342 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3343 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3345 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3346 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3347 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3348 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3349 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3350 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3351 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3352 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3353 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3354 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3355 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3357 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3359 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3362 * Smart Fifo configuration command.
3363 * @state: smart fifo state, types listed in iwm_sf_state.
3364 * @watermark: Minimum allowed available free space in RXF for transient state.
3365 * @long_delay_timeouts: aging and idle timer values for each scenario
3366 * in long delay state.
3367 * @full_on_timeouts: timer values for each scenario in full on state.
3369 struct iwm_sf_cfg_cmd {
3371 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3372 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3373 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3374 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3381 * BEGIN mvm/fw-api-mac.h
3393 * enum iwm_mac_protection_flags - MAC context flags
3394 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3395 * this will require CCK RTS/CTS2self.
3396 * RTS/CTS will protect full burst time.
3397 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3398 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3399 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3401 enum iwm_mac_protection_flags {
3402 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3403 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3404 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3405 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3408 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3409 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3412 * enum iwm_mac_types - Supported MAC types
3413 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3414 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3415 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3416 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3417 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3418 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3419 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3420 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3421 * @IWM_FW_MAC_TYPE_GO: P2P GO
3422 * @IWM_FW_MAC_TYPE_TEST: ?
3423 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3425 enum iwm_mac_types {
3426 IWM_FW_MAC_TYPE_FIRST = 1,
3427 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3428 IWM_FW_MAC_TYPE_LISTENER,
3429 IWM_FW_MAC_TYPE_PIBSS,
3430 IWM_FW_MAC_TYPE_IBSS,
3431 IWM_FW_MAC_TYPE_BSS_STA,
3432 IWM_FW_MAC_TYPE_P2P_DEVICE,
3433 IWM_FW_MAC_TYPE_P2P_STA,
3435 IWM_FW_MAC_TYPE_TEST,
3436 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3437 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3440 * enum iwm_tsf_id - TSF hw timer ID
3441 * @IWM_TSF_ID_A: use TSF A
3442 * @IWM_TSF_ID_B: use TSF B
3443 * @IWM_TSF_ID_C: use TSF C
3444 * @IWM_TSF_ID_D: use TSF D
3445 * @IWM_NUM_TSF_IDS: number of TSF timers available
3452 IWM_NUM_TSF_IDS = 4,
3453 }; /* IWM_TSF_ID_API_E_VER_1 */
3456 * struct iwm_mac_data_ap - configuration data for AP MAC context
3457 * @beacon_time: beacon transmit time in system time
3458 * @beacon_tsf: beacon transmit time in TSF
3459 * @bi: beacon interval in TU
3460 * @bi_reciprocal: 2^32 / bi
3461 * @dtim_interval: dtim transmit time in TU
3462 * @dtim_reciprocal: 2^32 / dtim_interval
3463 * @mcast_qid: queue ID for multicast traffic
3464 * @beacon_template: beacon template ID
3466 struct iwm_mac_data_ap {
3467 uint32_t beacon_time;
3468 uint64_t beacon_tsf;
3470 uint32_t bi_reciprocal;
3471 uint32_t dtim_interval;
3472 uint32_t dtim_reciprocal;
3474 uint32_t beacon_template;
3475 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3478 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3479 * @beacon_time: beacon transmit time in system time
3480 * @beacon_tsf: beacon transmit time in TSF
3481 * @bi: beacon interval in TU
3482 * @bi_reciprocal: 2^32 / bi
3483 * @beacon_template: beacon template ID
3485 struct iwm_mac_data_ibss {
3486 uint32_t beacon_time;
3487 uint64_t beacon_tsf;
3489 uint32_t bi_reciprocal;
3490 uint32_t beacon_template;
3491 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3494 * struct iwm_mac_data_sta - configuration data for station MAC context
3495 * @is_assoc: 1 for associated state, 0 otherwise
3496 * @dtim_time: DTIM arrival time in system time
3497 * @dtim_tsf: DTIM arrival time in TSF
3498 * @bi: beacon interval in TU, applicable only when associated
3499 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3500 * @dtim_interval: DTIM interval in TU, applicable only when associated
3501 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3502 * @listen_interval: in beacon intervals, applicable only when associated
3503 * @assoc_id: unique ID assigned by the AP during association
3505 struct iwm_mac_data_sta {
3510 uint32_t bi_reciprocal;
3511 uint32_t dtim_interval;
3512 uint32_t dtim_reciprocal;
3513 uint32_t listen_interval;
3515 uint32_t assoc_beacon_arrive_time;
3516 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3519 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3520 * @ap: iwm_mac_data_ap struct with most config data
3521 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3522 * 0 indicates that there is no CT window.
3523 * @opp_ps_enabled: indicate that opportunistic PS allowed
3525 struct iwm_mac_data_go {
3526 struct iwm_mac_data_ap ap;
3528 uint32_t opp_ps_enabled;
3529 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3532 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3533 * @sta: iwm_mac_data_sta struct with most config data
3534 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3535 * 0 indicates that there is no CT window.
3537 struct iwm_mac_data_p2p_sta {
3538 struct iwm_mac_data_sta sta;
3540 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3543 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3544 * @stats_interval: interval in TU between statistics notifications to host.
3546 struct iwm_mac_data_pibss {
3547 uint32_t stats_interval;
3548 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3551 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3553 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3554 * other channels as well. This should be to true only in case that the
3555 * device is discoverable and there is an active GO. Note that setting this
3556 * field when not needed, will increase the number of interrupts and have
3557 * effect on the platform power, as this setting opens the Rx filters on
3560 struct iwm_mac_data_p2p_dev {
3561 uint32_t is_disc_extended;
3562 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3565 * enum iwm_mac_filter_flags - MAC context filter flags
3566 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3567 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3568 * control frames to the host
3569 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3570 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3571 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3572 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3573 * (in station mode when associated)
3574 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3575 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3576 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3578 enum iwm_mac_filter_flags {
3579 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3580 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3581 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3582 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3583 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3584 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3585 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3586 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3587 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3591 * enum iwm_mac_qos_flags - QoS flags
3592 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3593 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3594 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3597 enum iwm_mac_qos_flags {
3598 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3599 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3600 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3604 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3605 * @cw_min: Contention window, start value in numbers of slots.
3606 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3607 * @cw_max: Contention window, max value in numbers of slots.
3608 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3609 * @aifsn: Number of slots in Arbitration Interframe Space (before
3610 * performing random backoff timing prior to Tx). Device default 1.
3611 * @fifos_mask: FIFOs used by this MAC for this AC
3612 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3614 * One instance of this config struct for each of 4 EDCA access categories
3615 * in struct iwm_qosparam_cmd.
3617 * Device will automatically increase contention window by (2*CW) + 1 for each
3618 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3619 * value, to cap the CW value.
3627 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3630 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3631 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3632 * @id_and_color: ID and color of the MAC
3633 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3634 * @mac_type: one of IWM_FW_MAC_TYPE_*
3635 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3636 * @node_addr: MAC address
3637 * @bssid_addr: BSSID
3638 * @cck_rates: basic rates available for CCK
3639 * @ofdm_rates: basic rates available for OFDM
3640 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3641 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3642 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3643 * @filter_flags: combination of IWM_MAC_FILTER_*
3644 * @qos_flags: from IWM_MAC_QOS_FLG_*
3645 * @ac: one iwm_mac_qos configuration for each AC
3646 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3648 struct iwm_mac_ctx_cmd {
3649 /* COMMON_INDEX_HDR_API_S_VER_1 */
3650 uint32_t id_and_color;
3652 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3655 uint8_t node_addr[6];
3656 uint16_t reserved_for_node_addr;
3657 uint8_t bssid_addr[6];
3658 uint16_t reserved_for_bssid_addr;
3660 uint32_t ofdm_rates;
3661 uint32_t protection_flags;
3662 uint32_t cck_short_preamble;
3663 uint32_t short_slot;
3664 uint32_t filter_flags;
3665 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3667 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3668 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3670 struct iwm_mac_data_ap ap;
3671 struct iwm_mac_data_go go;
3672 struct iwm_mac_data_sta sta;
3673 struct iwm_mac_data_p2p_sta p2p_sta;
3674 struct iwm_mac_data_p2p_dev p2p_dev;
3675 struct iwm_mac_data_pibss pibss;
3676 struct iwm_mac_data_ibss ibss;
3678 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3680 static inline uint32_t iwm_reciprocal(uint32_t v)
3684 return 0xFFFFFFFF / v;
3687 #define IWM_NONQOS_SEQ_GET 0x1
3688 #define IWM_NONQOS_SEQ_SET 0x2
3689 struct iwm_nonqos_seq_query_cmd {
3690 uint32_t get_set_flag;
3691 uint32_t mac_id_n_color;
3694 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3697 * END mvm/fw-api-mac.h
3701 * BEGIN mvm/fw-api-power.h
3704 /* Power Management Commands, Responses, Notifications */
3707 * enum iwm_ltr_config_flags - masks for LTR config command flags
3708 * @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status
3709 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow
3711 * @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR
3713 * @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from
3715 * @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register
3716 * @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register
3717 * @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD
3719 enum iwm_ltr_config_flags {
3720 IWM_LTR_CFG_FLAG_FEATURE_ENABLE = (1 << 0),
3721 IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS = (1 << 1),
3722 IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH = (1 << 2),
3723 IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 = (1 << 3),
3724 IWM_LTR_CFG_FLAG_SW_SET_SHORT = (1 << 4),
3725 IWM_LTR_CFG_FLAG_SW_SET_LONG = (1 << 5),
3726 IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD = (1 << 6),
3730 * struct iwm_ltr_config_cmd_v1 - configures the LTR
3731 * @flags: See %enum iwm_ltr_config_flags
3733 struct iwm_ltr_config_cmd_v1 {
3735 uint32_t static_long;
3736 uint32_t static_short;
3737 } __packed; /* LTR_CAPABLE_API_S_VER_1 */
3739 #define IWM_LTR_VALID_STATES_NUM 4
3742 * struct iwm_ltr_config_cmd - configures the LTR
3743 * @flags: See %enum iwm_ltr_config_flags
3747 * @ltr_short_idle_timeout:
3749 struct iwm_ltr_config_cmd {
3751 uint32_t static_long;
3752 uint32_t static_short;
3753 uint32_t ltr_cfg_values[IWM_LTR_VALID_STATES_NUM];
3754 uint32_t ltr_short_idle_timeout;
3755 } __packed; /* LTR_CAPABLE_API_S_VER_2 */
3757 /* Radio LP RX Energy Threshold measured in dBm */
3758 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3759 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3760 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3763 * enum iwm_scan_flags - masks for power table command flags
3764 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3765 * receiver and transmitter. '0' - does not allow.
3766 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3767 * '1' Driver enables PM (use rest of parameters)
3768 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3769 * '1' PM could sleep over DTIM till listen Interval.
3770 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3771 * access categories are both delivery and trigger enabled.
3772 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3773 * PBW Snoozing enabled
3774 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3775 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3776 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3777 * detection enablement
3779 enum iwm_power_flags {
3780 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3781 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3782 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3783 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3784 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3785 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3786 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3787 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3790 #define IWM_POWER_VEC_SIZE 5
3793 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3794 * is used also with a new power API for device wide power settings.
3795 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3797 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3798 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3799 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3800 * set regardless of power scheme or current power state.
3801 * FW use this value also when PM is disabled.
3802 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3803 * PSM transition - legacy PM
3804 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3805 * PSM transition - legacy PM
3806 * @sleep_interval: not in use
3807 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3808 * is set. For example, if it is required to skip over
3809 * one DTIM, this value need to be set to 2 (DTIM periods).
3810 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3813 struct iwm_powertable_cmd {
3814 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3816 uint8_t keep_alive_seconds;
3817 uint8_t debug_flags;
3818 uint32_t rx_data_timeout;
3819 uint32_t tx_data_timeout;
3820 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3821 uint32_t skip_dtim_periods;
3822 uint32_t lprx_rssi_threshold;
3826 * enum iwm_device_power_flags - masks for device power command flags
3827 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3828 * receiver and transmitter. '0' - does not allow.
3830 enum iwm_device_power_flags {
3831 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3835 * struct iwm_device_power_cmd - device wide power command.
3836 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3838 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3840 struct iwm_device_power_cmd {
3841 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3847 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3848 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3849 * @id_and_color: MAC contex identifier
3850 * @flags: Power table command flags from POWER_FLAGS_*
3851 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3852 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3853 * set regardless of power scheme or current power state.
3854 * FW use this value also when PM is disabled.
3855 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3856 * PSM transition - legacy PM
3857 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3858 * PSM transition - legacy PM
3859 * @sleep_interval: not in use
3860 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3861 * is set. For example, if it is required to skip over
3862 * one DTIM, this value need to be set to 2 (DTIM periods).
3863 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3864 * PSM transition - uAPSD
3865 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3866 * PSM transition - uAPSD
3867 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3869 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3870 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3871 * from the AP [msec]
3872 * @snooze_window: A window of time in which PBW snoozing insures that all
3873 * packets received. It is also the minimum time from last
3874 * received unicast RX packet, before client stops snoozing
3877 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3878 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3879 * each corresponding AC.
3880 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3881 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3883 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3884 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3885 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3886 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3887 * @limited_ps_threshold:
3889 struct iwm_mac_power_cmd {
3890 /* CONTEXT_DESC_API_T_VER_1 */
3891 uint32_t id_and_color;
3893 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3895 uint16_t keep_alive_seconds;
3896 uint32_t rx_data_timeout;
3897 uint32_t tx_data_timeout;
3898 uint32_t rx_data_timeout_uapsd;
3899 uint32_t tx_data_timeout_uapsd;
3900 uint8_t lprx_rssi_threshold;
3901 uint8_t skip_dtim_periods;
3902 uint16_t snooze_interval;
3903 uint16_t snooze_window;
3904 uint8_t snooze_step;
3906 uint8_t uapsd_ac_flags;
3907 uint8_t uapsd_max_sp;
3908 uint8_t heavy_tx_thld_packets;
3909 uint8_t heavy_rx_thld_packets;
3910 uint8_t heavy_tx_thld_percentage;
3911 uint8_t heavy_rx_thld_percentage;
3912 uint8_t limited_ps_threshold;
3917 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3918 * associated AP is identified as improperly implementing uAPSD protocol.
3919 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3920 * @sta_id: index of station in uCode's station table - associated AP ID in
3923 struct iwm_uapsd_misbehaving_ap_notif {
3926 uint8_t reserved[3];
3930 * struct iwm_beacon_filter_cmd
3931 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3932 * @id_and_color: MAC contex identifier
3933 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3934 * to driver if delta in Energy values calculated for this and last
3935 * passed beacon is greater than this threshold. Zero value means that
3936 * the Energy change is ignored for beacon filtering, and beacon will
3937 * not be forced to be sent to driver regardless of this delta. Typical
3939 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3940 * Send beacon to driver if delta in Energy values calculated for this
3941 * and last passed beacon is greater than this threshold. Zero value
3942 * means that the Energy change is ignored for beacon filtering while in
3943 * Roaming state, typical energy delta 1dB.
3944 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3945 * calculated for current beacon is less than the threshold, use
3946 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3947 * Threshold. Typical energy threshold is -72dBm.
3948 * @bf_temp_threshold: This threshold determines the type of temperature
3949 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3950 * If the current temperature is above this threshold - Fast filter
3951 * will be used, If the current temperature is below this threshold -
3952 * Slow filter will be used.
3953 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3954 * calculated for this and the last passed beacon is greater than this
3955 * threshold. Zero value means that the temperature change is ignored for
3956 * beacon filtering; beacons will not be forced to be sent to driver
3957 * regardless of whether its temperature has been changed.
3958 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3959 * calculated for this and the last passed beacon is greater than this
3960 * threshold. Zero value means that the temperature change is ignored for
3961 * beacon filtering; beacons will not be forced to be sent to driver
3962 * regardless of whether its temperature has been changed.
3963 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3964 * @bf_filter_escape_timer: Send beacons to the driver if no beacons were passed
3965 * for a specific period of time. Units: Beacons.
3966 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3967 * for a longer period of time then this escape-timeout. Units: Beacons.
3968 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3970 struct iwm_beacon_filter_cmd {
3971 uint32_t bf_energy_delta;
3972 uint32_t bf_roaming_energy_delta;
3973 uint32_t bf_roaming_state;
3974 uint32_t bf_temp_threshold;
3975 uint32_t bf_temp_fast_filter;
3976 uint32_t bf_temp_slow_filter;
3977 uint32_t bf_enable_beacon_filter;
3978 uint32_t bf_debug_flag;
3979 uint32_t bf_escape_timer;
3980 uint32_t ba_escape_timer;
3981 uint32_t ba_enable_beacon_abort;
3984 /* Beacon filtering and beacon abort */
3985 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3986 #define IWM_BF_ENERGY_DELTA_MAX 255
3987 #define IWM_BF_ENERGY_DELTA_MIN 0
3989 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3990 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3991 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3993 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3994 #define IWM_BF_ROAMING_STATE_MAX 255
3995 #define IWM_BF_ROAMING_STATE_MIN 0
3997 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3998 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3999 #define IWM_BF_TEMP_THRESHOLD_MIN 0
4001 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
4002 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
4003 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
4005 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
4006 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
4007 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
4009 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
4011 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
4013 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
4014 #define IWM_BF_ESCAPE_TIMER_MAX 1024
4015 #define IWM_BF_ESCAPE_TIMER_MIN 0
4017 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
4018 #define IWM_BA_ESCAPE_TIMER_D3 9
4019 #define IWM_BA_ESCAPE_TIMER_MAX 1024
4020 #define IWM_BA_ESCAPE_TIMER_MIN 0
4022 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
4024 #define IWM_BF_CMD_CONFIG_DEFAULTS \
4025 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
4026 .bf_roaming_energy_delta = \
4027 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
4028 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
4029 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
4030 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
4031 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
4032 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
4033 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
4034 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
4037 * END mvm/fw-api-power.h
4041 * BEGIN mvm/fw-api-rs.h
4045 * These serve as indexes into
4046 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
4047 * TODO: avoid overlap between legacy and HT rates
4050 IWM_RATE_1M_INDEX = 0,
4051 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
4055 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
4057 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
4058 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
4059 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
4060 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
4063 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
4065 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
4067 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
4069 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
4071 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
4073 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
4074 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
4076 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
4077 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
4078 IWM_RATE_MCS_8_INDEX,
4079 IWM_RATE_MCS_9_INDEX,
4080 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
4081 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
4082 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
4085 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
4087 /* fw API values for legacy bit rates, both OFDM and CCK */
4089 IWM_RATE_6M_PLCP = 13,
4090 IWM_RATE_9M_PLCP = 15,
4091 IWM_RATE_12M_PLCP = 5,
4092 IWM_RATE_18M_PLCP = 7,
4093 IWM_RATE_24M_PLCP = 9,
4094 IWM_RATE_36M_PLCP = 11,
4095 IWM_RATE_48M_PLCP = 1,
4096 IWM_RATE_54M_PLCP = 3,
4097 IWM_RATE_1M_PLCP = 10,
4098 IWM_RATE_2M_PLCP = 20,
4099 IWM_RATE_5M_PLCP = 55,
4100 IWM_RATE_11M_PLCP = 110,
4101 IWM_RATE_INVM_PLCP = -1,
4105 * rate_n_flags bit fields
4107 * The 32-bit value has different layouts in the low 8 bites depending on the
4108 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
4109 * for CCK and OFDM).
4111 * High-throughput (HT) rate format
4112 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
4113 * Very High-throughput (VHT) rate format
4114 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
4115 * Legacy OFDM rate format for bits 7:0
4116 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
4117 * Legacy CCK rate format for bits 7:0:
4118 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
4121 /* Bit 8: (1) HT format, (0) legacy or VHT format */
4122 #define IWM_RATE_MCS_HT_POS 8
4123 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
4125 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
4126 #define IWM_RATE_MCS_CCK_POS 9
4127 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
4129 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
4130 #define IWM_RATE_MCS_VHT_POS 26
4131 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
4135 * High-throughput (HT) rate format for bits 7:0
4137 * 2-0: MCS rate base
4146 * 4-3: 0) Single stream (SISO)
4147 * 1) Dual stream (MIMO)
4148 * 2) Triple stream (MIMO)
4149 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
4150 * (bits 7-6 are zero)
4152 * Together the low 5 bits work out to the MCS index because we don't
4153 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
4154 * streams and 16-23 have three streams. We could also support MCS 32
4155 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
4157 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
4158 #define IWM_RATE_HT_MCS_NSS_POS 3
4159 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
4161 /* Bit 10: (1) Use Green Field preamble */
4162 #define IWM_RATE_HT_MCS_GF_POS 10
4163 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
4165 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
4168 * Very High-throughput (VHT) rate format for bits 7:0
4170 * 3-0: VHT MCS (0-9)
4171 * 5-4: number of streams - 1:
4172 * 0) Single stream (SISO)
4173 * 1) Dual stream (MIMO)
4174 * 2) Triple stream (MIMO)
4177 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
4178 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
4179 #define IWM_RATE_VHT_MCS_NSS_POS 4
4180 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
4183 * Legacy OFDM rate format for bits 7:0
4195 * Legacy CCK rate format for bits 7:0:
4196 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
4204 #define IWM_RATE_LEGACY_RATE_MSK 0xff
4208 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
4209 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
4211 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
4212 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4213 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4214 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4215 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4216 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4218 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
4219 #define IWM_RATE_MCS_SGI_POS 13
4220 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
4222 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4223 #define IWM_RATE_MCS_ANT_POS 14
4224 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
4225 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
4226 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
4227 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
4228 IWM_RATE_MCS_ANT_B_MSK)
4229 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
4230 IWM_RATE_MCS_ANT_C_MSK)
4231 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
4232 #define IWM_RATE_MCS_ANT_NUM 3
4234 /* Bit 17-18: (0) SS, (1) SS*2 */
4235 #define IWM_RATE_MCS_STBC_POS 17
4236 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4238 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4239 #define IWM_RATE_MCS_BF_POS 19
4240 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4242 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
4243 #define IWM_RATE_MCS_ZLF_POS 20
4244 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4246 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4247 #define IWM_RATE_MCS_DUP_POS 24
4248 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
4250 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
4251 #define IWM_RATE_MCS_LDPC_POS 27
4252 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
4255 /* Link Quality definitions */
4257 /* # entries in rate scale table to support Tx retries */
4258 #define IWM_LQ_MAX_RETRY_NUM 16
4260 /* Link quality command flags bit fields */
4262 /* Bit 0: (0) Don't use RTS (1) Use RTS */
4263 #define IWM_LQ_FLAG_USE_RTS_POS 0
4264 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4266 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4267 #define IWM_LQ_FLAG_COLOR_POS 1
4268 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4270 /* Bit 4-5: Tx RTS BW Signalling
4271 * (0) No RTS BW signalling
4272 * (1) Static BW signalling
4273 * (2) Dynamic BW signalling
4275 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4276 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4277 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4278 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4280 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4281 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4283 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4284 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4286 /* Single Stream Tx Parameters (lq_cmd->ss_params)
4287 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be
4288 * used for single stream Tx.
4291 /* Bit 0-1: Max STBC streams allowed. Can be 0-3.
4292 * (0) - No STBC allowed
4293 * (1) - 2x1 STBC allowed (HT/VHT)
4294 * (2) - 4x2 STBC allowed (HT/VHT)
4295 * (3) - 3x2 STBC allowed (HT only)
4296 * All our chips are at most 2 antennas so only (1) is valid for now.
4298 #define IWM_LQ_SS_STBC_ALLOWED_POS 0
4299 #define IWM_LQ_SS_STBC_ALLOWED_MSK (3 << IWM_LQ_SS_STBC_ALLOWED_MSK)
4301 /* 2x1 STBC is allowed */
4302 #define IWM_LQ_SS_STBC_1SS_ALLOWED (1 << IWM_LQ_SS_STBC_ALLOWED_POS)
4304 /* Bit 2: Beamformer (VHT only) is allowed */
4305 #define IWM_LQ_SS_BFER_ALLOWED_POS 2
4306 #define IWM_LQ_SS_BFER_ALLOWED (1 << IWM_LQ_SS_BFER_ALLOWED_POS)
4308 /* Bit 3: Force BFER or STBC for testing
4310 * If BFER is allowed then force the ucode to choose BFER else
4311 * If STBC is allowed then force the ucode to choose STBC over SISO
4313 #define IWM_LQ_SS_FORCE_POS 3
4314 #define IWM_LQ_SS_FORCE (1 << IWM_LQ_SS_FORCE_POS)
4316 /* Bit 31: ss_params field is valid. Used for FW backward compatibility
4317 * with other drivers which don't support the ss_params API yet
4319 #define IWM_LQ_SS_PARAMS_VALID_POS 31
4320 #define IWM_LQ_SS_PARAMS_VALID (1 << IWM_LQ_SS_PARAMS_VALID_POS)
4323 * struct iwm_lq_cmd - link quality command
4324 * @sta_id: station to update
4325 * @control: not used
4326 * @flags: combination of IWM_LQ_FLAG_*
4327 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4329 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4330 * Should be ANT_[ABC]
4331 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4332 * @initial_rate_index: first index from rs_table per AC category
4333 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4334 * value of 100 is one usec. Range is 100 to 8000
4335 * @agg_disable_start_th: try-count threshold for starting aggregation.
4336 * If a frame has higher try-count, it should not be selected for
4337 * starting an aggregation sequence.
4338 * @agg_frame_cnt_limit: max frame count in an aggregation.
4340 * 1: no aggregation (one frame per aggregation)
4341 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4342 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4343 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4344 * @ss_params: single stream features. declare whether STBC or BFER are allowed.
4348 uint8_t reduced_tpc;
4350 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4353 uint8_t single_stream_ant_msk;
4354 uint8_t dual_stream_ant_msk;
4355 uint8_t initial_rate_index[IWM_AC_NUM];
4356 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4357 uint16_t agg_time_limit;
4358 uint8_t agg_disable_start_th;
4359 uint8_t agg_frame_cnt_limit;
4361 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4363 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4366 * END mvm/fw-api-rs.h
4370 * BEGIN mvm/fw-api-tx.h
4374 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4375 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4376 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4377 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4378 * Otherwise, use rate_n_flags from the TX command
4379 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4380 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4381 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4382 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4383 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4384 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4385 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4386 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4387 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4388 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4389 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4390 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4391 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4392 * Should be set for beacons and probe responses
4393 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4394 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4395 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4396 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4397 * Should be set for 26/30 length MAC headers
4398 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4399 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4400 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4401 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4402 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4403 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4404 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4407 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4408 IWM_TX_CMD_FLG_ACK = (1 << 3),
4409 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4410 IWM_TX_CMD_FLG_BA = (1 << 5),
4411 IWM_TX_CMD_FLG_BAR = (1 << 6),
4412 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4413 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4414 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4415 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4416 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4417 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4418 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4419 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4420 IWM_TX_CMD_FLG_TSF = (1 << 16),
4421 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4422 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4423 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4424 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4425 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4426 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4427 IWM_TX_CMD_FLG_DUR = (1 << 25),
4428 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4429 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4430 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4431 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4432 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4435 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4436 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4437 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4438 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4440 enum iwm_tx_pm_timeouts {
4441 IWM_PM_FRAME_NONE = 0,
4442 IWM_PM_FRAME_MGMT = 2,
4443 IWM_PM_FRAME_ASSOC = 3,
4447 * TX command security control
4449 #define IWM_TX_CMD_SEC_WEP 0x01
4450 #define IWM_TX_CMD_SEC_CCM 0x02
4451 #define IWM_TX_CMD_SEC_TKIP 0x03
4452 #define IWM_TX_CMD_SEC_EXT 0x04
4453 #define IWM_TX_CMD_SEC_MSK 0x07
4454 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4455 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4456 #define IWM_TX_CMD_SEC_KEY128 0x08
4459 * TX command Frame life time in us - to be written in pm_frame_timeout
4461 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4462 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4463 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4464 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4467 * TID for non QoS frames - to be written in tid_tspec
4469 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4472 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4474 #define IWM_DEFAULT_TX_RETRY 15
4475 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4476 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
4477 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4478 #define IWM_LOW_RETRY_LIMIT 7
4481 * enum iwm_tx_offload_assist_flags_pos - set %iwm_tx_cmd offload_assist values
4482 * @IWM_TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words)
4483 * from mac header end. For normal case it is 4 words for SNAP.
4484 * note: tx_cmd, mac header and pad are not counted in the offset.
4485 * This is used to help the offload in case there is tunneling such as
4486 * IPv6 in IPv4, in such case the ip header offset should point to the
4487 * inner ip header and IPv4 checksum of the external header should be
4488 * calculated by driver.
4489 * @IWM_TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum
4490 * @IWM_TX_CMD_OFFLD_L3_EN: enable IP header checksum
4491 * @IWM_TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV
4492 * field. Doesn't include the pad.
4493 * @IWM_TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for
4495 * @IWM_TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU
4497 enum iwm_tx_offload_assist_flags_pos {
4498 IWM_TX_CMD_OFFLD_IP_HDR = 0,
4499 IWM_TX_CMD_OFFLD_L4_EN = 6,
4500 IWM_TX_CMD_OFFLD_L3_EN = 7,
4501 IWM_TX_CMD_OFFLD_MH_SIZE = 8,
4502 IWM_TX_CMD_OFFLD_PAD = 13,
4503 IWM_TX_CMD_OFFLD_AMSDU = 14,
4506 #define IWM_TX_CMD_OFFLD_MH_MASK 0x1f
4507 #define IWM_TX_CMD_OFFLD_IP_HDR_MASK 0x3f
4509 /* TODO: complete documentation for try_cnt and btkill_cnt */
4511 * struct iwm_tx_cmd - TX command struct to FW
4512 * ( IWM_TX_CMD = 0x1c )
4513 * @len: in bytes of the payload, see below for details
4514 * @offload_assist: TX offload configuration
4515 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4516 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4517 * cleared. Combination of IWM_RATE_MCS_*
4518 * @sta_id: index of destination station in FW station table
4519 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4520 * @initial_rate_index: index into the rate table for initial TX attempt.
4521 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4522 * @key: security key
4523 * @reserved3: reserved
4524 * @life_time: frame life time (usecs??)
4525 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4526 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4527 * @dram_msb_ptr: upper bits of the scratch physical address
4528 * @rts_retry_limit: max attempts for RTS
4529 * @data_retry_limit: max attempts to send the data packet
4530 * @tid_spec: TID/tspec
4531 * @pm_frame_timeout: PM TX frame timeout
4532 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4533 * specified by HCCA protocol
4535 * The byte count (both len and next_frame_len) includes MAC header
4536 * (24/26/30/32 bytes)
4537 * + 2 bytes pad if 26/30 header size
4538 * + 8 byte IV for CCM or TKIP (not used for WEP)
4540 * + 8-byte MIC (not used for CCM/WEP)
4541 * It does not include post-MAC padding, i.e.,
4542 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4543 * Range of len: 14-2342 bytes.
4545 * After the struct fields the MAC header is placed, plus any padding,
4546 * and then the actial payload.
4550 uint16_t offload_assist;
4556 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4557 uint32_t rate_n_flags;
4560 uint8_t initial_rate_index;
4565 uint32_t dram_lsb_ptr;
4566 uint8_t dram_msb_ptr;
4567 uint8_t rts_retry_limit;
4568 uint8_t data_retry_limit;
4570 uint16_t pm_frame_timeout;
4573 struct ieee80211_frame hdr[0];
4574 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4577 * TX response related data
4581 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4582 * @IWM_TX_STATUS_SUCCESS:
4583 * @IWM_TX_STATUS_DIRECT_DONE:
4584 * @IWM_TX_STATUS_POSTPONE_DELAY:
4585 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4586 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4587 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4588 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4589 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4590 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4591 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4592 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4593 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4594 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4595 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4596 * @IWM_TX_STATUS_FAIL_DEST_PS:
4597 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4598 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4599 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4600 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4601 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4602 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4603 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4604 * @IWM_TX_STATUS_FAIL_FW_DROP:
4605 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4607 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4609 * @IWM_TX_MODE_NO_BURST:
4610 * @IWM_TX_MODE_IN_BURST_SEQ:
4611 * @IWM_TX_MODE_FIRST_IN_BURST:
4612 * @IWM_TX_QUEUE_NUM_MSK:
4614 * Valid only if frame_count =1
4615 * TODO: complete documentation
4617 enum iwm_tx_status {
4618 IWM_TX_STATUS_MSK = 0x000000ff,
4619 IWM_TX_STATUS_SUCCESS = 0x01,
4620 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4622 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4623 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4624 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4625 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4626 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4628 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4629 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4630 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4631 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4632 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4633 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4634 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4635 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4636 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4637 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4638 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4639 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4640 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4641 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4642 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4643 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4644 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4645 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4646 IWM_TX_MODE_MSK = 0x00000f00,
4647 IWM_TX_MODE_NO_BURST = 0x00000000,
4648 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4649 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4650 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4651 IWM_TX_NARROW_BW_MSK = 0x00060000,
4652 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4653 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4654 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4658 * enum iwm_tx_agg_status - TX aggregation status
4659 * @IWM_AGG_TX_STATE_STATUS_MSK:
4660 * @IWM_AGG_TX_STATE_TRANSMITTED:
4661 * @IWM_AGG_TX_STATE_UNDERRUN:
4662 * @IWM_AGG_TX_STATE_BT_PRIO:
4663 * @IWM_AGG_TX_STATE_FEW_BYTES:
4664 * @IWM_AGG_TX_STATE_ABORT:
4665 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4666 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4667 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4668 * @IWM_AGG_TX_STATE_SCD_QUERY:
4669 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4670 * @IWM_AGG_TX_STATE_RESPONSE:
4671 * @IWM_AGG_TX_STATE_DUMP_TX:
4672 * @IWM_AGG_TX_STATE_DELAY_TX:
4673 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4674 * occur if tx failed for this frame when it was a member of a previous
4675 * aggregation block). If rate scaling is used, retry count indicates the
4676 * rate table entry used for all frames in the new agg.
4677 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4680 * TODO: complete documentation
4682 enum iwm_tx_agg_status {
4683 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4684 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4685 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4686 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4687 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4688 IWM_AGG_TX_STATE_ABORT = 0x008,
4689 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4690 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4691 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4692 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4693 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4694 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4695 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4696 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4697 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4698 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4701 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4702 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4703 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4706 * The mask below describes a status where we are absolutely sure that the MPDU
4707 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4708 * written the bytes to the TXE, but we know nothing about what the DSP did.
4710 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4711 IWM_AGG_TX_STATE_ABORT | \
4712 IWM_AGG_TX_STATE_SCD_QUERY)
4715 * IWM_REPLY_TX = 0x1c (response)
4717 * This response may be in one of two slightly different formats, indicated
4718 * by the frame_count field:
4720 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4721 * frame. Multiple attempts, at various bit rates, may have been made for
4724 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4725 * frames that used block-acknowledge. All frames were transmitted at
4726 * same rate. Rate scaling may have been used if first frame in this new
4727 * agg block failed in previous agg block(s).
4729 * Note that, for aggregation, ACK (block-ack) status is not delivered
4730 * here; block-ack has not been received by the time the device records
4732 * This status relates to reasons the tx might have been blocked or aborted
4733 * within the device, rather than whether it was received successfully by
4734 * the destination station.
4738 * struct iwm_agg_tx_status - per packet TX aggregation status
4739 * @status: enum iwm_tx_agg_status
4740 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4742 struct iwm_agg_tx_status {
4748 * definitions for initial rate index field
4749 * bits [3:0] initial rate index
4750 * bits [6:4] rate table color, used for the initial rate
4751 * bit-7 invalid rate indication
4753 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4754 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4755 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4757 #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4758 #define IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4761 * struct iwm_tx_resp - notifies that fw is TXing a packet
4762 * ( IWM_REPLY_TX = 0x1c )
4763 * @frame_count: 1 no aggregation, >1 aggregation
4764 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4765 * @failure_rts: num of failures due to unsuccessful RTS
4766 * @failure_frame: num failures due to no ACK (unused for agg)
4767 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4768 * Tx of all the batch. IWM_RATE_MCS_*
4769 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4770 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4772 * @pa_status: tx power info
4773 * @pa_integ_res_a: tx power info
4774 * @pa_integ_res_b: tx power info
4775 * @pa_integ_res_c: tx power info
4776 * @measurement_req_id: tx power info
4777 * @tfd_info: TFD information set by the FH
4778 * @seq_ctl: sequence control from the Tx cmd
4779 * @byte_cnt: byte count from the Tx cmd
4780 * @tlc_info: TLC rate info
4781 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4782 * @frame_ctrl: frame control
4783 * @status: for non-agg: frame status IWM_TX_STATUS_*
4784 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4785 * follow this one, up to frame_count.
4787 * After the array of statuses comes the SSN of the SCD. Look at
4788 * %iwm_get_scd_ssn for more details.
4790 struct iwm_tx_resp {
4791 uint8_t frame_count;
4792 uint8_t bt_kill_count;
4793 uint8_t failure_rts;
4794 uint8_t failure_frame;
4795 uint32_t initial_rate;
4796 uint16_t wireless_media_time;
4799 uint8_t pa_integ_res_a[3];
4800 uint8_t pa_integ_res_b[3];
4801 uint8_t pa_integ_res_c[3];
4802 uint16_t measurement_req_id;
4803 uint8_t reduced_tpc;
4811 uint16_t frame_ctrl;
4813 struct iwm_agg_tx_status status;
4814 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4817 * struct iwm_ba_notif - notifies about reception of BA
4818 * ( IWM_BA_NOTIF = 0xc5 )
4819 * @sta_addr_lo32: lower 32 bits of the MAC address
4820 * @sta_addr_hi16: upper 16 bits of the MAC address
4821 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4822 * @tid: tid of the session
4824 * @bitmap: the bitmap of the BA notification as seen in the air
4825 * @scd_flow: the tx queue this BA relates to
4826 * @scd_ssn: the index of the last contiguously sent packet
4827 * @txed: number of Txed frames in this batch
4828 * @txed_2_done: number of Acked frames in this batch
4830 struct iwm_ba_notif {
4831 uint32_t sta_addr_lo32;
4832 uint16_t sta_addr_hi16;
4842 uint8_t txed_2_done;
4847 * struct iwm_mac_beacon_cmd - beacon template command
4848 * @tx: the tx commands associated with the beacon frame
4849 * @template_id: currently equal to the mac context id of the coresponding
4851 * @tim_idx: the offset of the tim IE in the beacon
4852 * @tim_size: the length of the tim IE
4853 * @frame: the template of the beacon frame
4855 struct iwm_mac_beacon_cmd {
4856 struct iwm_tx_cmd tx;
4857 uint32_t template_id;
4860 struct ieee80211_frame frame[0];
4863 struct iwm_beacon_notif {
4864 struct iwm_tx_resp beacon_notify_hdr;
4866 uint32_t ibss_mgr_status;
4870 * enum iwm_dump_control - dump (flush) control flags
4871 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4872 * and the TFD queues are empty.
4874 enum iwm_dump_control {
4875 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4879 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4880 * @queues_ctl: bitmap of queues to flush
4881 * @flush_ctl: control flags
4882 * @reserved: reserved
4884 struct iwm_tx_path_flush_cmd {
4885 uint32_t queues_ctl;
4888 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4891 * iwm_get_scd_ssn - returns the SSN of the SCD
4892 * @tx_resp: the Tx response from the fw (agg or non-agg)
4894 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4895 * it can't know that everything will go well until the end of the AMPDU, it
4896 * can't know in advance the number of MPDUs that will be sent in the current
4897 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4898 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4899 * of the batch. This is why the SSN of the SCD is written at the end of the
4900 * whole struct at a variable offset. This function knows how to cope with the
4901 * variable offset and returns the SSN of the SCD.
4903 static inline uint32_t iwm_get_scd_ssn(struct iwm_tx_resp *tx_resp)
4905 return le32_to_cpup((uint32_t *)&tx_resp->status +
4906 tx_resp->frame_count) & 0xfff;
4910 * END mvm/fw-api-tx.h
4914 * BEGIN mvm/fw-api-scan.h
4918 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4920 * @sta_id: station id
4922 * @scd_queue: scheduler queue to confiug
4923 * @enable: 1 queue enable, 0 queue disable
4924 * @aggregate: 1 aggregated queue, 0 otherwise
4925 * @tx_fifo: %enum iwm_tx_fifo
4926 * @window: BA window size
4927 * @ssn: SSN for the BA agreement
4929 struct iwm_scd_txq_cfg_cmd {
4940 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4943 * struct iwm_scd_txq_cfg_rsp
4944 * @token: taken from the command
4945 * @sta_id: station id from the command
4946 * @tid: tid from the command
4947 * @scd_queue: scd_queue from the command
4949 struct iwm_scd_txq_cfg_rsp {
4954 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4957 /* Scan Commands, Responses, Notifications */
4959 /* Masks for iwm_scan_channel.type flags */
4960 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4961 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1)
4963 /* Max number of IEs for direct SSID scans in a command */
4964 #define IWM_PROBE_OPTION_MAX 20
4967 * struct iwm_ssid_ie - directed scan network information element
4969 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4970 * selected by "type" bit field in struct iwm_scan_channel;
4971 * each channel may select different ssids from among the 20 entries.
4972 * SSID IEs get transmitted in reverse order of entry.
4974 struct iwm_ssid_ie {
4977 uint8_t ssid[IEEE80211_NWID_LEN];
4978 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4981 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4982 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4983 #define IWM_SCAN_MAX_PROFILES 11
4984 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4986 /* Default watchdog (in MS) for scheduled scan iteration */
4987 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4989 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4990 #define IWM_CAN_ABORT_STATUS 1
4992 #define IWM_FULL_SCAN_MULTIPLIER 5
4993 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4994 #define IWM_MAX_SCHED_SCAN_PLANS 2
4997 * iwm_scan_schedule_lmac - schedule of scan offload
4998 * @delay: delay between iterations, in seconds.
4999 * @iterations: num of scan iterations
5000 * @full_scan_mul: number of partial scans before each full scan
5002 struct iwm_scan_schedule_lmac {
5005 uint8_t full_scan_mul;
5006 } __packed; /* SCAN_SCHEDULE_API_S */
5009 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
5010 * @tx_flags: combination of TX_CMD_FLG_*
5011 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
5012 * cleared. Combination of RATE_MCS_*
5013 * @sta_id: index of destination station in FW station table
5014 * @reserved: for alignment and future use
5016 struct iwm_scan_req_tx_cmd {
5018 uint32_t rate_n_flags;
5020 uint8_t reserved[3];
5023 enum iwm_scan_channel_flags_lmac {
5024 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
5025 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
5029 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
5030 * @flags: bits 1-20: directed scan to i'th ssid
5031 * other bits &enum iwm_scan_channel_flags_lmac
5032 * @channel_number: channel number 1-13 etc
5033 * @iter_count: scan iteration on this channel
5034 * @iter_interval: interval in seconds between iterations on one channel
5036 struct iwm_scan_channel_cfg_lmac {
5038 uint16_t channel_num;
5039 uint16_t iter_count;
5040 uint32_t iter_interval;
5044 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
5045 * @offset: offset in the data block
5046 * @len: length of the segment
5048 struct iwm_scan_probe_segment {
5053 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
5054 * @mac_header: first (and common) part of the probe
5055 * @band_data: band specific data
5056 * @common_data: last (and common) part of the probe
5057 * @buf: raw data block
5059 struct iwm_scan_probe_req {
5060 struct iwm_scan_probe_segment mac_header;
5061 struct iwm_scan_probe_segment band_data[2];
5062 struct iwm_scan_probe_segment common_data;
5063 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
5066 enum iwm_scan_channel_flags {
5067 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
5068 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
5069 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
5072 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
5073 * @flags: enum iwm_scan_channel_flags
5074 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
5076 * 1 - EBS is disabled.
5077 * 2 - every second scan will be full scan(and so on).
5079 struct iwm_scan_channel_opt {
5081 uint16_t non_ebs_ratio;
5085 * iwm_lmac_scan_flags
5086 * @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
5087 * without filtering.
5088 * @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
5089 * @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
5090 * @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
5091 * @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
5092 * @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
5093 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
5094 * and DS parameter set IEs into probe requests.
5095 * @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
5097 * @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
5099 enum iwm_lmac_scan_flags {
5100 IWM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
5101 IWM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
5102 IWM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
5103 IWM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
5104 IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
5105 IWM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
5106 IWM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
5107 IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
5108 IWM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
5111 enum iwm_scan_priority {
5112 IWM_SCAN_PRIORITY_LOW,
5113 IWM_SCAN_PRIORITY_MEDIUM,
5114 IWM_SCAN_PRIORITY_HIGH,
5118 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
5119 * @reserved1: for alignment and future use
5120 * @channel_num: num of channels to scan
5121 * @active-dwell: dwell time for active channels
5122 * @passive-dwell: dwell time for passive channels
5123 * @fragmented-dwell: dwell time for fragmented passive scan
5124 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
5125 * @reserved2: for alignment and future use
5126 * @rx_chain_selct: PHY_RX_CHAIN_* flags
5127 * @scan_flags: &enum iwm_lmac_scan_flags
5128 * @max_out_time: max time (in TU) to be out of associated channel
5129 * @suspend_time: pause scan this long (TUs) when returning to service channel
5130 * @flags: RXON flags
5131 * @filter_flags: RXON filter
5132 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
5133 * @direct_scan: list of SSIDs for directed active scan
5134 * @scan_prio: enum iwm_scan_priority
5135 * @iter_num: number of scan iterations
5136 * @delay: delay in seconds before first iteration
5137 * @schedule: two scheduling plans. The first one is finite, the second one can
5139 * @channel_opt: channel optimization options, for full and partial scan
5140 * @data: channel configuration and probe request packet.
5142 struct iwm_scan_req_lmac {
5143 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
5146 uint8_t active_dwell;
5147 uint8_t passive_dwell;
5148 uint8_t fragmented_dwell;
5149 uint8_t extended_dwell;
5151 uint16_t rx_chain_select;
5152 uint32_t scan_flags;
5153 uint32_t max_out_time;
5154 uint32_t suspend_time;
5155 /* RX_ON_FLAGS_API_S_VER_1 */
5157 uint32_t filter_flags;
5158 struct iwm_scan_req_tx_cmd tx_cmd[2];
5159 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5161 /* SCAN_REQ_PERIODIC_PARAMS_API_S */
5164 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
5165 struct iwm_scan_channel_opt channel_opt[2];
5170 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
5171 * @last_schedule_line: last schedule line executed (fast or regular)
5172 * @last_schedule_iteration: last scan iteration executed before scan abort
5173 * @status: enum iwm_scan_offload_complete_status
5174 * @ebs_status: EBS success status &enum iwm_scan_ebs_status
5175 * @time_after_last_iter; time in seconds elapsed after last iteration
5177 struct iwm_periodic_scan_complete {
5178 uint8_t last_schedule_line;
5179 uint8_t last_schedule_iteration;
5182 uint32_t time_after_last_iter;
5187 * struct iwm_scan_results_notif - scan results for one channel -
5188 * SCAN_RESULT_NTF_API_S_VER_3
5189 * @channel: which channel the results are from
5190 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
5191 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
5192 * @num_probe_not_sent: # of request that weren't sent due to not enough time
5193 * @duration: duration spent in channel, in usecs
5195 struct iwm_scan_results_notif {
5198 uint8_t probe_status;
5199 uint8_t num_probe_not_sent;
5203 enum iwm_scan_framework_client {
5204 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
5205 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
5206 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
5210 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
5211 * @ssid: MAC address to filter out
5212 * @reported_rssi: AP rssi reported to the host
5213 * @client_bitmap: clients ignore this entry - enum scan_framework_client
5215 struct iwm_scan_offload_blacklist {
5216 uint8_t ssid[IEEE80211_ADDR_LEN];
5217 uint8_t reported_rssi;
5218 uint8_t client_bitmap;
5221 enum iwm_scan_offload_network_type {
5222 IWM_NETWORK_TYPE_BSS = 1,
5223 IWM_NETWORK_TYPE_IBSS = 2,
5224 IWM_NETWORK_TYPE_ANY = 3,
5227 enum iwm_scan_offload_band_selection {
5228 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
5229 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
5230 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
5234 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
5235 * @ssid_index: index to ssid list in fixed part
5236 * @unicast_cipher: encryption olgorithm to match - bitmap
5237 * @aut_alg: authentication olgorithm to match - bitmap
5238 * @network_type: enum iwm_scan_offload_network_type
5239 * @band_selection: enum iwm_scan_offload_band_selection
5240 * @client_bitmap: clients waiting for match - enum scan_framework_client
5242 struct iwm_scan_offload_profile {
5244 uint8_t unicast_cipher;
5246 uint8_t network_type;
5247 uint8_t band_selection;
5248 uint8_t client_bitmap;
5249 uint8_t reserved[2];
5253 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
5254 * @blaclist: AP list to filter off from scan results
5255 * @profiles: profiles to search for match
5256 * @blacklist_len: length of blacklist
5257 * @num_profiles: num of profiles in the list
5258 * @match_notify: clients waiting for match found notification
5259 * @pass_match: clients waiting for the results
5260 * @active_clients: active clients bitmap - enum scan_framework_client
5261 * @any_beacon_notify: clients waiting for match notification without match
5263 struct iwm_scan_offload_profile_cfg {
5264 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
5265 uint8_t blacklist_len;
5266 uint8_t num_profiles;
5267 uint8_t match_notify;
5269 uint8_t active_clients;
5270 uint8_t any_beacon_notify;
5271 uint8_t reserved[2];
5274 enum iwm_scan_offload_complete_status {
5275 IWM_SCAN_OFFLOAD_COMPLETED = 1,
5276 IWM_SCAN_OFFLOAD_ABORTED = 2,
5279 enum iwm_scan_ebs_status {
5280 IWM_SCAN_EBS_SUCCESS,
5281 IWM_SCAN_EBS_FAILED,
5282 IWM_SCAN_EBS_CHAN_NOT_FOUND,
5283 IWM_SCAN_EBS_INACTIVE,
5287 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5288 * SCAN_COMPLETE_NTF_API_S_VER_3
5289 * @scanned_channels: number of channels scanned (and number of valid results)
5290 * @status: one of SCAN_COMP_STATUS_*
5291 * @bt_status: BT on/off status
5292 * @last_channel: last channel that was scanned
5293 * @tsf_low: TSF timer (lower half) in usecs
5294 * @tsf_high: TSF timer (higher half) in usecs
5295 * @results: an array of scan results, only "scanned_channels" of them are valid
5297 struct iwm_lmac_scan_complete_notif {
5298 uint8_t scanned_channels;
5301 uint8_t last_channel;
5304 struct iwm_scan_results_notif results[];
5309 * END mvm/fw-api-scan.h
5313 * BEGIN mvm/fw-api-sta.h
5318 /* The maximum of either of these cannot exceed 8, because we use an
5319 * 8-bit mask (see IWM_SCAN_MASK).
5321 #define IWM_MAX_UMAC_SCANS 8
5322 #define IWM_MAX_LMAC_SCANS 1
5324 enum iwm_scan_config_flags {
5325 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5326 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5327 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5328 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5329 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5330 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5331 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5332 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5333 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5334 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5335 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5336 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5337 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5338 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5339 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5340 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5341 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5342 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5344 /* Bits 26-31 are for num of channels in channel_array */
5345 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5348 enum iwm_scan_config_rates {
5349 /* OFDM basic rates */
5350 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5351 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5352 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5353 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5354 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5355 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5356 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5357 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5358 /* CCK basic rates */
5359 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5360 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5361 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5362 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5364 /* Bits 16-27 are for supported rates */
5365 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5368 enum iwm_channel_flags {
5369 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5370 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5371 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5372 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5376 * struct iwm_scan_config
5377 * @flags: enum scan_config_flags
5378 * @tx_chains: valid_tx antenna - ANT_* definitions
5379 * @rx_chains: valid_rx antenna - ANT_* definitions
5380 * @legacy_rates: default legacy rates - enum scan_config_rates
5381 * @out_of_channel_time: default max out of serving channel time
5382 * @suspend_time: default max suspend time
5383 * @dwell_active: default dwell time for active scan
5384 * @dwell_passive: default dwell time for passive scan
5385 * @dwell_fragmented: default dwell time for fragmented scan
5386 * @dwell_extended: default dwell time for channels 1, 6 and 11
5387 * @mac_addr: default mac address to be used in probes
5388 * @bcast_sta_id: the index of the station in the fw
5389 * @channel_flags: default channel flags - enum iwm_channel_flags
5390 * scan_config_channel_flag
5391 * @channel_array: default supported channels
5393 struct iwm_scan_config {
5397 uint32_t legacy_rates;
5398 uint32_t out_of_channel_time;
5399 uint32_t suspend_time;
5400 uint8_t dwell_active;
5401 uint8_t dwell_passive;
5402 uint8_t dwell_fragmented;
5403 uint8_t dwell_extended;
5404 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5405 uint8_t bcast_sta_id;
5406 uint8_t channel_flags;
5407 uint8_t channel_array[];
5408 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5411 * iwm_umac_scan_flags
5412 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5413 * can be preempted by other scan requests with higher priority.
5414 * The low priority scan will be resumed when the higher proirity scan is
5416 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5419 enum iwm_umac_scan_flags {
5420 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5421 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5424 enum iwm_umac_scan_uid_offsets {
5425 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5426 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5429 enum iwm_umac_scan_general_flags {
5430 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5431 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5432 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5433 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5434 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5435 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5436 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5437 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5438 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5439 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5440 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5444 * struct iwm_scan_channel_cfg_umac
5445 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5446 * @channel_num: channel number 1-13 etc.
5447 * @iter_count: repetition count for the channel.
5448 * @iter_interval: interval between two scan iterations on one channel.
5450 struct iwm_scan_channel_cfg_umac {
5452 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5454 uint8_t channel_num;
5456 uint16_t iter_interval;
5457 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5460 * struct iwm_scan_umac_schedule
5461 * @interval: interval in seconds between scan iterations
5462 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5463 * @reserved: for alignment and future use
5465 struct iwm_scan_umac_schedule {
5469 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5472 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5473 * parameters following channels configuration array.
5474 * @schedule: two scheduling plans.
5475 * @delay: delay in TUs before starting the first scan iteration
5476 * @reserved: for future use and alignment
5477 * @preq: probe request with IEs blocks
5478 * @direct_scan: list of SSIDs for directed active scan
5480 struct iwm_scan_req_umac_tail {
5481 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5482 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5485 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5486 struct iwm_scan_probe_req preq;
5487 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5491 * struct iwm_scan_uma_chan_param
5492 * @flags: channel flags &enum iwm_scan_channel_flags
5493 * @count: num of channels in scan request
5494 * @reserved: for future use and alignment
5496 struct iwm_scan_umac_chan_param {
5503 * struct iwm_scan_req_umac
5504 * @flags: &enum iwm_umac_scan_flags
5505 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5506 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5507 * @general_flags: &enum iwm_umac_scan_general_flags
5508 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
5509 * @extended_dwell: dwell time for channels 1, 6 and 11
5510 * @active_dwell: dwell time for active scan per LMAC
5511 * @passive_dwell: dwell time for passive scan per LMAC
5512 * @fragmented_dwell: dwell time for fragmented passive scan
5513 * @adwell_default_n_aps: for adaptive dwell the default number of APs
5515 * @adwell_default_n_aps_social: for adaptive dwell the default
5516 * number of APs per social (1,6,11) channel
5517 * @general_flags2: &enum iwl_umac_scan_general_flags2
5518 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added
5519 * to total scan time
5520 * @max_out_time: max out of serving channel time, per LMAC - for CDB there
5522 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs
5523 * @scan_priority: scan internal prioritization &enum iwl_scan_priority
5524 * @num_of_fragments: Number of fragments needed for full coverage per band.
5525 * Relevant only for fragmented scan.
5526 * @channel: &struct iwl_scan_umac_chan_param
5527 * @reserved: for future use and alignment
5528 * @reserved3: for future use and alignment
5529 * @data: &struct iwm_scan_channel_cfg_umac and
5530 * &struct iwm_scan_req_umac_tail
5532 struct iwm_scan_req_umac {
5535 uint32_t ooc_priority;
5536 uint16_t general_flags;
5538 uint8_t scan_start_mac_id;
5541 uint8_t extended_dwell;
5542 uint8_t active_dwell;
5543 uint8_t passive_dwell;
5544 uint8_t fragmented_dwell;
5545 uint32_t max_out_time;
5546 uint32_t suspend_time;
5547 uint32_t scan_priority;
5548 struct iwm_scan_umac_chan_param channel;
5552 uint8_t active_dwell;
5553 uint8_t passive_dwell;
5554 uint8_t fragmented_dwell;
5555 uint8_t adwell_default_n_aps;
5556 uint8_t adwell_default_n_aps_social;
5558 uint16_t adwell_max_budget;
5559 uint32_t max_out_time[2];
5560 uint32_t suspend_time[2];
5561 uint32_t scan_priority;
5562 struct iwm_scan_umac_chan_param channel;
5568 #define IWM_SCAN_REQ_UMAC_SIZE_V7 48
5569 #define IWM_SCAN_REQ_UMAC_SIZE_V1 36
5572 * struct iwm_umac_scan_abort
5573 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5576 struct iwm_umac_scan_abort {
5579 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5582 * struct iwm_umac_scan_complete
5583 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5584 * @last_schedule: last scheduling line
5585 * @last_iter: last scan iteration number
5586 * @scan status: &enum iwm_scan_offload_complete_status
5587 * @ebs_status: &enum iwm_scan_ebs_status
5588 * @time_from_last_iter: time elapsed from last iteration
5589 * @reserved: for future use
5591 struct iwm_umac_scan_complete {
5593 uint8_t last_schedule;
5597 uint32_t time_from_last_iter;
5599 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5601 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5603 * struct iwm_scan_offload_profile_match - match information
5604 * @bssid: matched bssid
5605 * @channel: channel where the match occurred
5607 * @matching_feature:
5608 * @matching_channels: bitmap of channels that matched, referencing
5609 * the channels passed in tue scan offload request
5611 struct iwm_scan_offload_profile_match {
5612 uint8_t bssid[IEEE80211_ADDR_LEN];
5616 uint8_t matching_feature;
5617 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5618 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5621 * struct iwm_scan_offload_profiles_query - match results query response
5622 * @matched_profiles: bitmap of matched profiles, referencing the
5623 * matches passed in the scan offload request
5624 * @last_scan_age: age of the last offloaded scan
5625 * @n_scans_done: number of offloaded scans done
5626 * @gp2_d0u: GP2 when D0U occurred
5627 * @gp2_invoked: GP2 when scan offload was invoked
5628 * @resume_while_scanning: not used
5629 * @self_recovery: obsolete
5630 * @reserved: reserved
5631 * @matches: array of match information, one for each match
5633 struct iwm_scan_offload_profiles_query {
5634 uint32_t matched_profiles;
5635 uint32_t last_scan_age;
5636 uint32_t n_scans_done;
5638 uint32_t gp2_invoked;
5639 uint8_t resume_while_scanning;
5640 uint8_t self_recovery;
5642 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5643 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5646 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5647 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5648 * @scanned_channels: number of channels scanned and number of valid elements in
5650 * @status: one of SCAN_COMP_STATUS_*
5651 * @bt_status: BT on/off status
5652 * @last_channel: last channel that was scanned
5653 * @tsf_low: TSF timer (lower half) in usecs
5654 * @tsf_high: TSF timer (higher half) in usecs
5655 * @results: array of scan results, only "scanned_channels" of them are valid
5657 struct iwm_umac_scan_iter_complete_notif {
5659 uint8_t scanned_channels;
5662 uint8_t last_channel;
5665 struct iwm_scan_results_notif results[];
5666 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5668 /* Please keep this enum *SORTED* by hex value.
5669 * Needed for binary search, otherwise a warning will be triggered.
5671 enum iwm_scan_subcmd_ids {
5672 IWM_GSCAN_START_CMD = 0x0,
5673 IWM_GSCAN_STOP_CMD = 0x1,
5674 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5675 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5676 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5677 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5678 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5679 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5680 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5686 * enum iwm_sta_flags - flags for the ADD_STA host command
5687 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5688 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5689 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5690 * @IWM_STA_FLG_PS: set if STA is in Power Save
5691 * @IWM_STA_FLG_INVALID: set if STA is invalid
5692 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5693 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5694 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5695 * @IWM_STA_FLG_PAN: STA is for PAN interface
5696 * @IWM_STA_FLG_CLASS_AUTH:
5697 * @IWM_STA_FLG_CLASS_ASSOC:
5698 * @IWM_STA_FLG_CLASS_MIMO_PROT:
5699 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5700 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5701 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5702 * initialised by driver and can be updated by fw upon reception of
5703 * action frames that can change the channel width. When cleared the fw
5704 * will send all the frames in 20MHz even when FAT channel is requested.
5705 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5706 * driver and can be updated by fw upon reception of action frames.
5707 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5709 enum iwm_sta_flags {
5710 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5711 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
5713 IWM_STA_FLG_DISABLE_TX = (1 << 4),
5715 IWM_STA_FLG_PS = (1 << 8),
5716 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5717 IWM_STA_FLG_PAN = (1 << 13),
5718 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5719 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5720 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
5722 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5723 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5724 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5725 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5726 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5727 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5728 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5729 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5730 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5731 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5733 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5734 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5735 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5736 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5737 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5738 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5740 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5741 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5742 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5743 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5744 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
5746 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5747 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5748 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5749 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5753 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
5754 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5755 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5756 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5757 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5758 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5759 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5760 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5761 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5762 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5763 * station info array (1 - n 1X mode)
5764 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5765 * @IWM_STA_KEY_NOT_VALID: key is invalid
5766 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5767 * @IWM_STA_KEY_MULTICAST: set for multical key
5768 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5770 enum iwm_sta_key_flag {
5771 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5772 IWM_STA_KEY_FLG_WEP = (1 << 0),
5773 IWM_STA_KEY_FLG_CCM = (2 << 0),
5774 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5775 IWM_STA_KEY_FLG_EXT = (4 << 0),
5776 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5777 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5778 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
5780 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5781 IWM_STA_KEY_FLG_KEYID_POS = 8,
5782 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5783 IWM_STA_KEY_NOT_VALID = (1 << 11),
5784 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5785 IWM_STA_KEY_MULTICAST = (1 << 14),
5786 IWM_STA_KEY_MFP = (1 << 15),
5790 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5791 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5792 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5793 * @IWM_STA_MODIFY_TX_RATE: unused
5794 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5795 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5796 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5797 * @IWM_STA_MODIFY_PROT_TH:
5798 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5800 enum iwm_sta_modify_flag {
5801 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5802 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5803 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5804 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5805 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5806 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5807 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5808 IWM_STA_MODIFY_QUEUES = (1 << 7),
5811 #define IWM_STA_MODE_MODIFY 1
5814 * enum iwm_sta_sleep_flag - type of sleep of the station
5815 * @IWM_STA_SLEEP_STATE_AWAKE:
5816 * @IWM_STA_SLEEP_STATE_PS_POLL:
5817 * @IWM_STA_SLEEP_STATE_UAPSD:
5818 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5819 * (last) released frame
5821 enum iwm_sta_sleep_flag {
5822 IWM_STA_SLEEP_STATE_AWAKE = 0,
5823 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5824 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5825 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5828 /* STA ID and color bits definitions */
5829 #define IWM_STA_ID_SEED (0x0f)
5830 #define IWM_STA_ID_POS (0)
5831 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5833 #define IWM_STA_COLOR_SEED (0x7)
5834 #define IWM_STA_COLOR_POS (4)
5835 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5837 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5838 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5839 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5840 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5842 #define IWM_STA_KEY_MAX_NUM (16)
5843 #define IWM_STA_KEY_IDX_INVALID (0xff)
5844 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5845 #define IWM_MAX_GLOBAL_KEYS (4)
5846 #define IWM_STA_KEY_LEN_WEP40 (5)
5847 #define IWM_STA_KEY_LEN_WEP104 (13)
5850 * struct iwm_keyinfo - key information
5851 * @key_flags: type %iwm_sta_key_flag
5852 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5853 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5854 * @key_offset: key offset in the fw's key table
5855 * @key: 16-byte unicast decryption key
5856 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5857 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5858 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5860 struct iwm_keyinfo {
5862 uint8_t tkip_rx_tsc_byte2;
5864 uint16_t tkip_rx_ttak[5];
5868 uint64_t tx_secur_seq_cnt;
5869 uint64_t hw_tkip_mic_rx_key;
5870 uint64_t hw_tkip_mic_tx_key;
5873 #define IWM_ADD_STA_STATUS_MASK 0xFF
5874 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5875 #define IWM_ADD_STA_BAID_MASK 0x7F00
5876 #define IWM_ADD_STA_BAID_SHIFT 8
5879 * struct iwl_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
5880 * ( REPLY_ADD_STA = 0x18 )
5881 * @add_modify: see &enum iwl_sta_mode
5882 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
5883 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5884 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
5885 * @mac_id_n_color: the Mac context this station belongs to,
5886 * see &enum iwl_ctxt_id_and_color
5887 * @addr: station's MAC address
5888 * @reserved2: reserved
5889 * @sta_id: index of station in uCode's station table
5890 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
5891 * alone. 1 - modify, 0 - don't change.
5892 * @reserved3: reserved
5893 * @station_flags: look at &enum iwl_sta_flags
5894 * @station_flags_msk: what of %station_flags have changed,
5895 * also &enum iwl_sta_flags
5896 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5897 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
5898 * add_immediate_ba_ssn.
5899 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5900 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
5901 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5902 * add_immediate_ba_tid.
5903 * @sleep_tx_count: number of packets to transmit to station even though it is
5904 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5905 * keeps track of STA sleep state.
5906 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag.
5907 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5909 * @beamform_flags: beam forming controls
5910 * @tfd_queue_msk: tfd queues used by this station
5912 * The device contains an internal table of per-station information, with info
5913 * on security keys, aggregation parameters, and Tx rates for initial Tx
5914 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD).
5916 * ADD_STA sets up the table entry for one station, either creating a new
5917 * entry, or modifying a pre-existing one.
5919 struct iwm_add_sta_cmd_v7 {
5922 uint16_t tid_disable_tx;
5923 uint32_t mac_id_n_color;
5924 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5927 uint8_t modify_mask;
5929 uint32_t station_flags;
5930 uint32_t station_flags_msk;
5931 uint8_t add_immediate_ba_tid;
5932 uint8_t remove_immediate_ba_tid;
5933 uint16_t add_immediate_ba_ssn;
5934 uint16_t sleep_tx_count;
5935 uint16_t sleep_state_flags;
5937 uint16_t beamform_flags;
5938 uint32_t tfd_queue_msk;
5939 } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5942 * enum iwm_sta_type - FW station types
5943 * ( REPLY_ADD_STA = 0x18 )
5944 * @IWM_STA_LINK: Link station - normal RX and TX traffic.
5945 * @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons
5946 * and probe responses.
5947 * @IWM_STA_MULTICAST: multicast traffic,
5948 * @IWM_STA_TDLS_LINK: TDLS link station
5949 * @IWM_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on).
5953 IWM_STA_GENERAL_PURPOSE,
5956 IWM_STA_AUX_ACTIVITY,
5960 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table.
5961 * ( REPLY_ADD_STA = 0x18 )
5962 * @add_modify: see &enum iwm_sta_mode
5963 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
5964 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5965 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
5966 * @mac_id_n_color: the Mac context this station belongs to,
5967 * see &enum iwl_ctxt_id_and_color
5968 * @addr: station's MAC address
5969 * @reserved2: reserved
5970 * @sta_id: index of station in uCode's station table
5971 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
5972 * alone. 1 - modify, 0 - don't change.
5973 * @reserved3: reserved
5974 * @station_flags: look at &enum iwm_sta_flags
5975 * @station_flags_msk: what of %station_flags have changed,
5976 * also &enum iwm_sta_flags
5977 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5978 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
5979 * add_immediate_ba_ssn.
5980 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5981 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
5982 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5983 * add_immediate_ba_tid.
5984 * @sleep_tx_count: number of packets to transmit to station even though it is
5985 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5986 * keeps track of STA sleep state.
5987 * @station_type: type of this station. See &enum iwl_sta_type.
5988 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag.
5989 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5991 * @beamform_flags: beam forming controls
5992 * @tfd_queue_msk: tfd queues used by this station.
5993 * Obselete for new TX API (9 and above).
5994 * @rx_ba_window: aggregation window size
5995 * @sp_length: the size of the SP in actual number of frames
5996 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver
5999 * The device contains an internal table of per-station information, with info
6000 * on security keys, aggregation parameters, and Tx rates for initial Tx
6001 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD).
6003 * ADD_STA sets up the table entry for one station, either creating a new
6004 * entry, or modifying a pre-existing one.
6006 struct iwm_add_sta_cmd {
6009 uint16_t tid_disable_tx;
6010 uint32_t mac_id_n_color;
6011 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
6014 uint8_t modify_mask;
6016 uint32_t station_flags;
6017 uint32_t station_flags_msk;
6018 uint8_t add_immediate_ba_tid;
6019 uint8_t remove_immediate_ba_tid;
6020 uint16_t add_immediate_ba_ssn;
6021 uint16_t sleep_tx_count;
6022 uint8_t sleep_state_flags;
6023 uint8_t station_type;
6025 uint16_t beamform_flags;
6026 uint32_t tfd_queue_msk;
6027 uint16_t rx_ba_window;
6030 } __packed; /* ADD_STA_CMD_API_S_VER_10 */
6033 * struct iwm_add_sta_key_cmd - add/modify sta key
6034 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
6035 * @sta_id: index of station in uCode's station table
6036 * @key_offset: key offset in key storage
6037 * @key_flags: type %iwm_sta_key_flag
6038 * @key: key material data
6039 * @key2: key material data
6040 * @rx_secur_seq_cnt: RX security sequence counter for the key
6041 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
6042 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
6044 struct iwm_add_sta_key_cmd {
6050 uint8_t rx_secur_seq_cnt[16];
6051 uint8_t tkip_rx_tsc_byte2;
6053 uint16_t tkip_rx_ttak[5];
6054 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
6057 * enum iwm_add_sta_rsp_status - status in the response to ADD_STA command
6058 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
6059 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
6060 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
6061 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
6062 * that doesn't exist.
6064 enum iwm_add_sta_rsp_status {
6065 IWM_ADD_STA_SUCCESS = 0x1,
6066 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
6067 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
6068 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
6072 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table
6073 * ( IWM_REMOVE_STA = 0x19 )
6074 * @sta_id: the station id of the station to be removed
6076 struct iwm_rm_sta_cmd {
6078 uint8_t reserved[3];
6079 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
6082 * struct iwm_mgmt_mcast_key_cmd
6083 * ( IWM_MGMT_MCAST_KEY = 0x1f )
6084 * @ctrl_flags: %iwm_sta_key_flag
6086 * @K1: IGTK master key
6088 * @sta_id: station ID that support IGTK
6090 * @receive_seq_cnt: initial RSC/PN needed for replay check
6092 struct iwm_mgmt_mcast_key_cmd {
6093 uint32_t ctrl_flags;
6099 uint64_t receive_seq_cnt;
6100 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
6102 struct iwm_wep_key {
6107 uint8_t reserved2[3];
6111 struct iwm_wep_key_cmd {
6112 uint32_t mac_id_n_color;
6114 uint8_t decryption_type;
6117 struct iwm_wep_key wep_key[0];
6118 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
6121 * END mvm/fw-api-sta.h
6128 enum iwm_bt_coex_mode {
6129 IWM_BT_COEX_DISABLE = 0x0,
6130 IWM_BT_COEX_NW = 0x1,
6131 IWM_BT_COEX_BT = 0x2,
6132 IWM_BT_COEX_WIFI = 0x3,
6133 }; /* BT_COEX_MODES_E */
6135 enum iwm_bt_coex_enabled_modules {
6136 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
6137 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
6138 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
6139 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
6140 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
6141 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
6144 * struct iwm_bt_coex_cmd - bt coex configuration command
6145 * @mode: enum %iwm_bt_coex_mode
6146 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
6148 * The structure is used for the BT_COEX command.
6150 struct iwm_bt_coex_cmd {
6152 uint32_t enabled_modules;
6153 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
6157 * Location Aware Regulatory (LAR) API - MCC updates
6161 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
6162 * regulatory profile according to the given MCC (Mobile Country Code).
6163 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
6164 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
6165 * MCC in the cmd response will be the relevant MCC in the NVM.
6166 * @mcc: given mobile country code
6167 * @source_id: the source from where we got the MCC, see iwm_mcc_source
6168 * @reserved: reserved for alignment
6170 struct iwm_mcc_update_cmd_v1 {
6174 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
6177 * struct iwm_mcc_update_cmd - Request the device to update geographic
6178 * regulatory profile according to the given MCC (Mobile Country Code).
6179 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
6180 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
6181 * MCC in the cmd response will be the relevant MCC in the NVM.
6182 * @mcc: given mobile country code
6183 * @source_id: the source from where we got the MCC, see iwm_mcc_source
6184 * @reserved: reserved for alignment
6185 * @key: integrity key for MCC API OEM testing
6186 * @reserved2: reserved
6188 struct iwm_mcc_update_cmd {
6193 uint32_t reserved2[5];
6194 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
6197 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
6198 * Contains the new channel control profile map, if changed, and the new MCC
6199 * (mobile country code).
6200 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
6201 * @status: see &enum iwm_mcc_update_status
6202 * @mcc: the new applied MCC
6203 * @cap: capabilities for all channels which matches the MCC
6204 * @source_id: the MCC source, see iwm_mcc_source
6205 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6206 * channels, depending on platform)
6207 * @channels: channel control data map, DWORD for each channel. Only the first
6210 struct iwm_mcc_update_resp_v1 {
6215 uint32_t n_channels;
6216 uint32_t channels[0];
6217 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
6220 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
6221 * Contains the new channel control profile map, if changed, and the new MCC
6222 * (mobile country code).
6223 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
6224 * @status: see &enum iwm_mcc_update_status
6225 * @mcc: the new applied MCC
6226 * @cap: capabilities for all channels which matches the MCC
6227 * @source_id: the MCC source, see iwm_mcc_source
6228 * @time: time elapsed from the MCC test start (in 30 seconds TU)
6229 * @reserved: reserved.
6230 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
6231 * channels, depending on platform)
6232 * @channels: channel control data map, DWORD for each channel. Only the first
6235 struct iwm_mcc_update_resp {
6242 uint32_t n_channels;
6243 uint32_t channels[0];
6244 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
6247 * struct iwm_mcc_chub_notif - chub notifies of mcc change
6248 * (MCC_CHUB_UPDATE_CMD = 0xc9)
6249 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
6250 * the cellular and connectivity cores that gets updates of the mcc, and
6251 * notifies the ucode directly of any mcc change.
6252 * The ucode requests the driver to request the device to update geographic
6253 * regulatory profile according to the given MCC (Mobile Country Code).
6254 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
6255 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
6256 * MCC in the cmd response will be the relevant MCC in the NVM.
6257 * @mcc: given mobile country code
6258 * @source_id: identity of the change originator, see iwm_mcc_source
6259 * @reserved1: reserved for alignment
6261 struct iwm_mcc_chub_notif {
6265 } __packed; /* LAR_MCC_NOTIFY_S */
6267 enum iwm_mcc_update_status {
6268 IWM_MCC_RESP_NEW_CHAN_PROFILE,
6269 IWM_MCC_RESP_SAME_CHAN_PROFILE,
6270 IWM_MCC_RESP_INVALID,
6271 IWM_MCC_RESP_NVM_DISABLED,
6272 IWM_MCC_RESP_ILLEGAL,
6273 IWM_MCC_RESP_LOW_PRIORITY,
6274 IWM_MCC_RESP_TEST_MODE_ACTIVE,
6275 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
6276 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
6279 enum iwm_mcc_source {
6280 IWM_MCC_SOURCE_OLD_FW = 0,
6281 IWM_MCC_SOURCE_ME = 1,
6282 IWM_MCC_SOURCE_BIOS = 2,
6283 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
6284 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
6285 IWM_MCC_SOURCE_WIFI = 5,
6286 IWM_MCC_SOURCE_RESERVED = 6,
6287 IWM_MCC_SOURCE_DEFAULT = 7,
6288 IWM_MCC_SOURCE_UNINITIALIZED = 8,
6289 IWM_MCC_SOURCE_MCC_API = 9,
6290 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
6291 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
6295 * struct iwm_dts_measurement_notif_v1 - measurements notification
6297 * @temp: the measured temperature
6298 * @voltage: the measured voltage
6300 struct iwm_dts_measurement_notif_v1 {
6303 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/
6306 * struct iwm_dts_measurement_notif_v2 - measurements notification
6308 * @temp: the measured temperature
6309 * @voltage: the measured voltage
6310 * @threshold_idx: the trip index that was crossed
6312 struct iwm_dts_measurement_notif_v2 {
6315 int32_t threshold_idx;
6316 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */
6319 * Some cherry-picked definitions
6322 #define IWM_FRAME_LIMIT 64
6325 * These functions retrieve specific information from the id field in
6326 * the iwm_host_cmd struct which contains the command id, the group id,
6327 * and the version of the command and vice versa.
6329 static inline uint8_t
6330 iwm_cmd_opcode(uint32_t cmdid)
6332 return cmdid & 0xff;
6335 static inline uint8_t
6336 iwm_cmd_groupid(uint32_t cmdid)
6338 return ((cmdid & 0xff00) >> 8);
6341 static inline uint8_t
6342 iwm_cmd_version(uint32_t cmdid)
6344 return ((cmdid & 0xff0000) >> 16);
6347 static inline uint32_t
6348 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
6350 return opcode + (groupid << 8) + (version << 16);
6353 /* make uint16_t wide id out of uint8_t group and opcode */
6354 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
6356 /* due to the conversion, this group is special */
6357 #define IWM_ALWAYS_LONG_GROUP 1
6359 struct iwm_cmd_header {
6366 struct iwm_cmd_header_wide {
6377 * enum iwm_power_scheme
6378 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode
6379 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default)
6380 * @IWM_POWER_LEVEL_LP - Low Power
6382 enum iwm_power_scheme {
6383 IWM_POWER_SCHEME_CAM = 1,
6384 IWM_POWER_SCHEME_BPS,
6388 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
6389 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6390 #define IWM_CMD_FAILED_MSK 0x40
6393 * struct iwm_device_cmd
6395 * For allocation of the command and tx queues, this establishes the overall
6396 * size of the largest command we send to uCode, except for commands that
6397 * aren't fully copied and use other TFD space.
6399 struct iwm_device_cmd {
6402 struct iwm_cmd_header hdr;
6403 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
6406 struct iwm_cmd_header_wide hdr_wide;
6407 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
6408 sizeof(struct iwm_cmd_header_wide) +
6409 sizeof(struct iwm_cmd_header)];
6414 struct iwm_rx_packet {
6416 * The first 4 bytes of the RX frame header contain both the RX frame
6417 * size and some flags.
6419 * 31: flag flush RB request
6420 * 30: flag ignore TC (terminal counter) request
6421 * 29: flag fast IRQ request
6423 * 13-00: RX frame size
6425 uint32_t len_n_flags;
6426 struct iwm_cmd_header hdr;
6430 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6431 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000
6432 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40
6434 static inline uint32_t
6435 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6438 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6441 static inline uint32_t
6442 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
6445 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6449 #define IWM_MIN_DBM -100
6450 #define IWM_MAX_DBM -33 /* realistic guess */
6452 #define IWM_READ(sc, reg) \
6453 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6455 #define IWM_WRITE(sc, reg, val) \
6456 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6458 #define IWM_WRITE_1(sc, reg, val) \
6459 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6461 #define IWM_SETBITS(sc, reg, mask) \
6462 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
6464 #define IWM_CLRBITS(sc, reg, mask) \
6465 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
6467 #define IWM_BARRIER_WRITE(sc) \
6468 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6469 BUS_SPACE_BARRIER_WRITE)
6471 #define IWM_BARRIER_READ_WRITE(sc) \
6472 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6473 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
6475 #endif /* __IF_IWM_REG_H__ */