1 /* $OpenBSD: if_iwmreg.h,v 1.3 2015/02/23 10:25:20 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
77 * CSR (control and status registers)
79 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * whenever platform supplies power to device, even when device is in
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
84 * Use iwl_write32() and iwl_read32() family to access these registers;
85 * these provide simple PCI bus access, without waking up the MAC.
86 * Do not use iwl_write_direct32() family for these registers;
87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
91 * NOTE: Device does need to be awake in order to read this memory
92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101 #define IWM_CSR_GP_CNTRL (0x024)
103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
104 #define IWM_CSR_INT_PERIODIC_REG (0x005)
107 * Hardware revision info
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
114 #define IWM_CSR_HW_REV (0x028)
117 * EEPROM and OTP (one-time-programmable) memory reads
119 * NOTE: Device must be awake, initialized via apm_ops.init(),
122 #define IWM_CSR_EEPROM_REG (0x02c)
123 #define IWM_CSR_EEPROM_GP (0x030)
124 #define IWM_CSR_OTP_GP_REG (0x034)
126 #define IWM_CSR_GIO_REG (0x03C)
127 #define IWM_CSR_GP_UCODE_REG (0x048)
128 #define IWM_CSR_GP_DRIVER_REG (0x050)
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
132 * SET/CLR registers set/clear bit(s) if "1" is written.
134 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
139 #define IWM_CSR_LED_REG (0x094)
140 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
141 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
144 /* GIO Chicken Bits (PCI Express bus link power management) */
145 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
147 /* Analog phase-lock-loop configuration */
148 #define IWM_CSR_ANA_PLL_CFG (0x20c)
151 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
152 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
153 * See also IWM_CSR_HW_REV register.
155 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
156 * 1-0: "Dash" (-) value, as in C-1, etc.
158 #define IWM_CSR_HW_REV_WA_REG (0x22C)
160 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
161 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
163 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
166 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
168 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
171 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
184 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
186 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
187 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
189 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
190 * acknowledged (reset) by host writing "1" to flagged bits. */
191 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
192 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
193 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
194 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
195 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
196 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
197 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
198 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
199 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
200 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
201 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
203 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
204 IWM_CSR_INT_BIT_HW_ERR | \
205 IWM_CSR_INT_BIT_FH_TX | \
206 IWM_CSR_INT_BIT_SW_ERR | \
207 IWM_CSR_INT_BIT_RF_KILL | \
208 IWM_CSR_INT_BIT_SW_RX | \
209 IWM_CSR_INT_BIT_WAKEUP | \
210 IWM_CSR_INT_BIT_ALIVE | \
211 IWM_CSR_INT_BIT_RX_PERIODIC)
213 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
214 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
215 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
216 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
217 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
218 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
219 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
221 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
222 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL0)
225 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
226 IWM_CSR_FH_INT_BIT_TX_CHNL0)
229 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
230 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
231 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
234 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
235 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
236 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
237 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
238 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
239 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
242 * GP (general purpose) CONTROL REGISTER
245 * Indicates state of (platform's) hardware RF-Kill switch
246 * 26-24: POWER_SAVE_TYPE
247 * Indicates current power-saving mode:
248 * 000 -- No power saving
249 * 001 -- MAC power-down
250 * 010 -- PHY (radio) power-down
253 * Indicates current system configuration, reflecting pins on chip
254 * as forced high/low by device circuit board.
256 * Indicates MAC is entering a power-saving sleep power-down.
257 * Not a good time to access device-internal resources.
259 * Host sets this to request and maintain MAC wakeup, to allow host
260 * access to device-internal resources. Host must wait for
261 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
264 * Host sets this to put device into fully operational D0 power mode.
265 * Host resets this after SW_RESET to put device into low power mode.
267 * Indicates MAC (ucode processor, etc.) is powered up and can run.
268 * Internal resources are accessible.
269 * NOTE: This does not indicate that the processor is actually running.
270 * NOTE: This does not indicate that device has completed
271 * init or post-power-down restore of internal SRAM memory.
272 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
273 * SRAM is restored and uCode is in normal operation mode.
274 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
275 * do not need to save/restore it.
276 * NOTE: After device reset, this bit remains "0" until host sets
279 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
280 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
281 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
282 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
284 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
286 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
287 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
288 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
292 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
293 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
295 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
296 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
297 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
298 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
299 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
300 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
301 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
302 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
303 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
304 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
305 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
306 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
307 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
308 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
309 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
310 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
311 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
314 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
315 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
316 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
317 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
320 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
321 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
322 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
323 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
324 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
325 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
327 /* One-time-programmable memory general purpose reg */
328 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
329 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
330 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
331 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
334 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
335 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
336 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
337 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
338 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
342 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
345 * UCODE-DRIVER GP (general purpose) mailbox register 1
346 * Host driver and uCode write and/or read this register to communicate with
350 * Host sets this to request permanent halt of uCode, same as
351 * sending CARD_STATE command with "halt" bit set.
353 * Host sets this to request exit from CT_KILL state, i.e. host thinks
354 * device temperature is low enough to continue normal operation.
356 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
357 * to release uCode to clear all Tx and command queues, enter
358 * unassociated mode, and power down.
359 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
361 * Host sets this when issuing CARD_STATE command to request
364 * uCode sets this when preparing a power-saving power-down.
365 * uCode resets this when power-up is complete and SRAM is sane.
366 * NOTE: device saves internal SRAM data to host when powering down,
367 * and must restore this data after powering back up.
368 * MAC_SLEEP is the best indication that restore is complete.
369 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
370 * do not need to save/restore it.
372 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
373 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
374 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
375 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
376 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
379 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
380 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
381 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
382 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
383 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
384 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
386 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
388 /* GIO Chicken Bits (PCI Express bus link power management) */
389 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
390 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
393 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
394 #define IWM_CSR_LED_REG_TURN_ON (0x60)
395 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
398 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
401 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
404 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
405 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
407 /* SECURE boot registers */
408 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
409 enum iwm_secure_boot_config_reg {
410 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
411 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
414 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
415 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
416 enum iwm_secure_boot_status_reg {
417 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
418 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
419 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
420 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
421 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
424 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR (0x100)
425 enum iwm_secure_load_status_reg {
426 IWM_CSR_CPU_STATUS_LOADING_STARTED = 0x00000001,
427 IWM_CSR_CPU_STATUS_LOADING_COMPLETED = 0x00000002,
428 IWM_CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
429 IWM_CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
432 #define IWM_CSR_SECURE_INSPECTOR_CODE_ADDR (0x100)
433 #define IWM_CSR_SECURE_INSPECTOR_DATA_ADDR (0x100)
435 #define IWM_CSR_SECURE_TIME_OUT (100)
437 #define IWM_FH_TCSR_0_REG0 (0x1D00)
440 * HBUS (Host-side Bus)
442 * HBUS registers are mapped directly into PCI bus space, but are used
443 * to indirectly access device's internal memory or registers that
444 * may be powered-down.
446 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
447 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
448 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
449 * internal resources.
451 * Do not use iwl_write32()/iwl_read32() family to access these registers;
452 * these provide only simple PCI bus access, without waking up the MAC.
454 #define IWM_HBUS_BASE (0x400)
457 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
458 * structures, error log, event log, verifying uCode load).
459 * First write to address register, then read from or write to data register
460 * to complete the job. Once the address register is set up, accesses to
461 * data registers auto-increment the address by one dword.
462 * Bit usage for address registers (read or write):
463 * 0-31: memory address within device
465 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
466 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
467 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
468 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
470 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
471 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
472 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
475 * Registers for accessing device's internal peripheral registers
476 * (e.g. SCD, BSM, etc.). First write to address register,
477 * then read from or write to data register to complete the job.
478 * Bit usage for address registers (read or write):
479 * 0-15: register address (offset) within device
480 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
482 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
483 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
484 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
485 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
487 /* Used to enable DBGM */
488 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
491 * Per-Tx-queue write pointer (index, really!)
492 * Indicates index to next TFD that driver will fill (1 past latest filled).
494 * 0-7: queue write index
495 * 11-8: queue selector
497 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
499 /**********************************************************
501 **********************************************************/
503 * host interrupt timeout value
504 * used with setting interrupt coalescing timer
505 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
507 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
509 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
510 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
511 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
512 #define IWM_HOST_INT_OPER_MODE (1 << 31)
514 /*****************************************************************************
515 * 7000/3000 series SHR DTS addresses *
516 *****************************************************************************/
518 /* Diode Results Register Structure: */
519 enum iwm_dtd_diode_reg {
520 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
521 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
522 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
523 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
524 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
525 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
526 /* Those are the masks INSIDE the flags bit-field: */
527 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
528 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
529 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
530 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
542 * enum iwm_ucode_tlv_flag - ucode API flags
543 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
544 * was a separate TLV but moved here to save space.
545 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
546 * treats good CRC threshold as a boolean
547 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
548 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
549 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
550 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
551 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
552 * offload profile config command.
553 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
554 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
555 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
556 * (rather than two) IPv6 addresses
557 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
558 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
559 * from the probe request template.
560 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
561 * connection when going back to D0
562 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
563 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
564 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
565 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
566 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
567 * containing CAM (Continuous Active Mode) indication.
568 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
569 * single bound interface).
570 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
572 enum iwm_ucode_tlv_flag {
573 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
574 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
575 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
576 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
577 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
578 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
579 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
580 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
581 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
582 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
583 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
584 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
585 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
586 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
587 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
588 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
589 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
590 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
591 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
592 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
593 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
594 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
597 /* The default calibrate table size if not specified by firmware file */
598 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
599 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
600 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
602 /* The default max probe length if not specified by the firmware file */
603 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
606 * enumeration of ucode section.
607 * This enumeration is used directly for older firmware (before 16.0).
608 * For new firmware, there can be up to 4 sections (see below) but the
609 * first one packaged into the firmware file is the DATA section and
610 * some debugging code accesses that.
613 IWM_UCODE_SECTION_DATA,
614 IWM_UCODE_SECTION_INST,
617 * For 16.0 uCode and above, there is no differentiation between sections,
618 * just an offset to the HW address.
620 #define IWM_UCODE_SECTION_MAX 6
621 #define IWM_UCODE_FIRST_SECTION_OF_SECOND_CPU (IWM_UCODE_SECTION_MAX/2)
623 /* uCode version contains 4 values: Major/Minor/API/Serial */
624 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
625 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
626 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
627 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
630 * Calibration control struct.
631 * Sent as part of the phy configuration command.
632 * @flow_trigger: bitmap for which calibrations to perform according to
634 * @event_trigger: bitmap for which calibrations to perform according to
637 struct iwm_tlv_calib_ctrl {
638 uint32_t flow_trigger;
639 uint32_t event_trigger;
642 enum iwm_fw_phy_cfg {
643 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
644 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
645 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
646 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
647 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
648 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
649 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
650 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
651 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
652 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
655 #define IWM_UCODE_MAX_CS 1
658 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
659 * @cipher: a cipher suite selector
660 * @flags: cipher scheme flags (currently reserved for a future use)
661 * @hdr_len: a size of MPDU security header
662 * @pn_len: a size of PN
663 * @pn_off: an offset of pn from the beginning of the security header
664 * @key_idx_off: an offset of key index byte in the security header
665 * @key_idx_mask: a bit mask of key_idx bits
666 * @key_idx_shift: bit shift needed to get key_idx
667 * @mic_len: mic length in bytes
668 * @hw_cipher: a HW cipher index used in host commands
670 struct iwm_fw_cipher_scheme {
677 uint8_t key_idx_mask;
678 uint8_t key_idx_shift;
684 * struct iwm_fw_cscheme_list - a cipher scheme list
685 * @size: a number of entries
686 * @cs: cipher scheme entries
688 struct iwm_fw_cscheme_list {
690 struct iwm_fw_cipher_scheme cs[];
698 * BEGIN iwl-fw-file.h
701 /* v1/v2 uCode file layout */
702 struct iwm_ucode_header {
703 uint32_t ver; /* major/minor/API/serial */
706 uint32_t inst_size; /* bytes of runtime code */
707 uint32_t data_size; /* bytes of runtime data */
708 uint32_t init_size; /* bytes of init code */
709 uint32_t init_data_size; /* bytes of init data */
710 uint32_t boot_size; /* bytes of bootstrap code */
711 uint8_t data[0]; /* in same order as sizes */
714 uint32_t build; /* build number */
715 uint32_t inst_size; /* bytes of runtime code */
716 uint32_t data_size; /* bytes of runtime data */
717 uint32_t init_size; /* bytes of init code */
718 uint32_t init_data_size; /* bytes of init data */
719 uint32_t boot_size; /* bytes of bootstrap code */
720 uint8_t data[0]; /* in same order as sizes */
726 * new TLV uCode file layout
728 * The new TLV file format contains TLVs, that each specify
729 * some piece of data.
732 enum iwm_ucode_tlv_type {
733 IWM_UCODE_TLV_INVALID = 0, /* unused */
734 IWM_UCODE_TLV_INST = 1,
735 IWM_UCODE_TLV_DATA = 2,
736 IWM_UCODE_TLV_INIT = 3,
737 IWM_UCODE_TLV_INIT_DATA = 4,
738 IWM_UCODE_TLV_BOOT = 5,
739 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
740 IWM_UCODE_TLV_PAN = 7,
741 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
742 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
743 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
744 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
745 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
746 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
747 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
748 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
749 IWM_UCODE_TLV_WOWLAN_INST = 16,
750 IWM_UCODE_TLV_WOWLAN_DATA = 17,
751 IWM_UCODE_TLV_FLAGS = 18,
752 IWM_UCODE_TLV_SEC_RT = 19,
753 IWM_UCODE_TLV_SEC_INIT = 20,
754 IWM_UCODE_TLV_SEC_WOWLAN = 21,
755 IWM_UCODE_TLV_DEF_CALIB = 22,
756 IWM_UCODE_TLV_PHY_SKU = 23,
757 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
758 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
759 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
760 IWM_UCODE_TLV_NUM_OF_CPU = 27,
761 IWM_UCODE_TLV_CSCHEME = 28,
764 * Following two are not in our base tag, but allow
765 * handling ucode version 9.
767 IWM_UCODE_TLV_API_CHANGES_SET = 29,
768 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30
771 struct iwm_ucode_tlv {
772 uint32_t type; /* see above */
773 uint32_t length; /* not including type/length fields */
777 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
779 struct iwm_tlv_ucode_header {
781 * The TLV style ucode header is distinguished from
782 * the v1/v2 style header by first four bytes being
783 * zero, as such is an invalid combination of
784 * major/minor/API/serial versions.
788 uint8_t human_readable[64];
789 uint32_t ver; /* major/minor/API/serial */
793 * The data contained herein has a TLV layout,
794 * see above for the TLV header and types.
795 * Note that each TLV is padded to a length
796 * that is a multiple of 4 for alignment.
810 * Registers in this file are internal, not PCI bus memory mapped.
811 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
813 #define IWM_PRPH_BASE (0x00000)
814 #define IWM_PRPH_END (0xFFFFF)
816 /* APMG (power management) constants */
817 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
818 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
819 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
820 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
821 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
822 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
823 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
824 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
825 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
826 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
827 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
829 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
830 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
831 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
833 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
834 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
835 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
836 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
837 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
838 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
839 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
841 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
843 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
845 /* Device system time */
846 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
848 /* Device NMI register */
849 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
851 /*****************************************************************************
852 * 7000/3000 series SHR DTS addresses *
853 *****************************************************************************/
855 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
856 #define IWM_DTSC_CFG_MODE (0x00a10604)
857 #define IWM_DTSC_VREF_AVG (0x00a10648)
858 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
859 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
860 #define IWM_DTSC_PTAT_AVG (0x00a10650)
866 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
867 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
868 * host DRAM. It steers each frame's Tx command (which contains the frame
869 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
870 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
871 * but one DMA channel may take input from several queues.
873 * Tx DMA FIFOs have dedicated purposes.
875 * For 5000 series and up, they are used differently
876 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
878 * 0 -- EDCA BK (background) frames, lowest priority
879 * 1 -- EDCA BE (best effort) frames, normal priority
880 * 2 -- EDCA VI (video) frames, higher priority
881 * 3 -- EDCA VO (voice) and management frames, highest priority
887 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
888 * In addition, driver can map the remaining queues to Tx DMA/FIFO
889 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
891 * The driver sets up each queue to work in one of two modes:
893 * 1) Scheduler-Ack, in which the scheduler automatically supports a
894 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
895 * contains TFDs for a unique combination of Recipient Address (RA)
896 * and Traffic Identifier (TID), that is, traffic of a given
897 * Quality-Of-Service (QOS) priority, destined for a single station.
899 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
900 * each frame within the BA window, including whether it's been transmitted,
901 * and whether it's been acknowledged by the receiving station. The device
902 * automatically processes block-acks received from the receiving STA,
903 * and reschedules un-acked frames to be retransmitted (successful
904 * Tx completion may end up being out-of-order).
906 * The driver must maintain the queue's Byte Count table in host DRAM
908 * This mode does not support fragmentation.
910 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
911 * The device may automatically retry Tx, but will retry only one frame
912 * at a time, until receiving ACK from receiving station, or reaching
913 * retry limit and giving up.
915 * The command queue (#4/#9) must use this mode!
916 * This mode does not require use of the Byte Count table in host DRAM.
918 * Driver controls scheduler operation via 3 means:
919 * 1) Scheduler registers
920 * 2) Shared scheduler data base in internal SRAM
921 * 3) Shared data in host DRAM
925 * When loading, driver should allocate memory for:
926 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
927 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
928 * (1024 bytes for each queue).
930 * After receiving "Alive" response from uCode, driver must initialize
931 * the scheduler (especially for queue #4/#9, the command queue, otherwise
932 * the driver can't issue commands!):
934 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
937 * Max Tx window size is the max number of contiguous TFDs that the scheduler
938 * can keep track of at one time when creating block-ack chains of frames.
939 * Note that "64" matches the number of ack bits in a block-ack packet.
941 #define IWM_SCD_WIN_SIZE 64
942 #define IWM_SCD_FRAME_LIMIT 64
944 #define IWM_SCD_TXFIFO_POS_TID (0)
945 #define IWM_SCD_TXFIFO_POS_RA (4)
946 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
949 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
950 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
951 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
952 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
953 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
955 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
956 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
957 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
958 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
959 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
960 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
961 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
962 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
965 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
966 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
969 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
970 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
972 /* Translation Data */
973 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
974 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
976 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
977 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
979 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
980 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
982 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
983 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
985 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
987 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
988 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
989 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
990 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
991 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
992 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
993 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
994 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
995 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
997 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1000 return IWM_SCD_BASE + 0x18 + chnl * 4;
1001 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1004 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1007 return IWM_SCD_BASE + 0x68 + chnl * 4;
1008 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1011 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1014 return IWM_SCD_BASE + 0x10c + chnl * 4;
1015 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1018 /*********************** END TX SCHEDULER *************************************/
1020 /* Oscillator clock */
1021 #define IWM_OSC_CLK (0xa04068)
1022 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1032 /****************************/
1033 /* Flow Handler Definitions */
1034 /****************************/
1037 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1038 * Addresses are offsets from device's PCI hardware base address.
1040 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1041 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1044 * Keep-Warm (KW) buffer base address.
1046 * Driver must allocate a 4KByte buffer that is for keeping the
1047 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1048 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1049 * from going into a power-savings mode that would cause higher DRAM latency,
1050 * and possible data over/under-runs, before all Tx/Rx is complete.
1052 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1053 * of the buffer, which must be 4K aligned. Once this is set up, the device
1054 * automatically invokes keep-warm accesses when normal accesses might not
1055 * be sufficient to maintain fast DRAM response.
1058 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1060 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1064 * TFD Circular Buffers Base (CBBC) addresses
1066 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1067 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1068 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1069 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1070 * aligned (address bits 0-7 must be 0).
1071 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1072 * for them are in different places.
1074 * Bit fields in each pointer register:
1075 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1077 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1078 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1079 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1080 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1081 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1082 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1084 /* Find TFD CB base pointer for given queue */
1085 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1088 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1090 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1091 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1096 * Rx SRAM Control and Status Registers (RSCSR)
1098 * These registers provide handshake between driver and device for the Rx queue
1099 * (this queue handles *all* command responses, notifications, Rx data, etc.
1100 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1101 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1102 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1103 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1104 * mapping between RBDs and RBs.
1106 * Driver must allocate host DRAM memory for the following, and set the
1107 * physical address of each into device registers:
1109 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1110 * entries (although any power of 2, up to 4096, is selectable by driver).
1111 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1112 * (typically 4K, although 8K or 16K are also selectable by driver).
1113 * Driver sets up RB size and number of RBDs in the CB via Rx config
1114 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1116 * Bit fields within one RBD:
1117 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1119 * Driver sets physical address [35:8] of base of RBD circular buffer
1120 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1122 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1123 * (RBs) have been filled, via a "write pointer", actually the index of
1124 * the RB's corresponding RBD within the circular buffer. Driver sets
1125 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1127 * Bit fields in lower dword of Rx status buffer (upper dword not used
1129 * 31-12: Not used by driver
1130 * 11- 0: Index of last filled Rx buffer descriptor
1131 * (device writes, driver reads this value)
1133 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1134 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1135 * and update the device's "write" index register,
1136 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1138 * This "write" index corresponds to the *next* RBD that the driver will make
1139 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1140 * the circular buffer. This value should initially be 0 (before preparing any
1141 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1142 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1143 * "read" index has advanced past 1! See below).
1144 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1146 * As the device fills RBs (referenced from contiguous RBDs within the circular
1147 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1148 * to tell the driver the index of the latest filled RBD. The driver must
1149 * read this "read" index from DRAM after receiving an Rx interrupt from device
1151 * The driver must also internally keep track of a third index, which is the
1152 * next RBD to process. When receiving an Rx interrupt, driver should process
1153 * all filled but unprocessed RBs up to, but not including, the RB
1154 * corresponding to the "read" index. For example, if "read" index becomes "1",
1155 * driver may process the RB pointed to by RBD 0. Depending on volume of
1156 * traffic, there may be many RBs to process.
1158 * If read index == write index, device thinks there is no room to put new data.
1159 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1160 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1161 * and "read" indexes; that is, make sure that there are no more than 254
1162 * buffers waiting to be filled.
1164 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1165 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1166 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1169 * Physical base address of 8-byte Rx Status buffer.
1171 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1173 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1176 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1178 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1180 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1183 * Rx write pointer (index, really!).
1185 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1186 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1188 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1189 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1191 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1192 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1195 * Rx Config/Status Registers (RCSR)
1196 * Rx Config Reg for channel 0 (only channel used)
1198 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1199 * normal operation (see bit fields).
1201 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1202 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1203 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1206 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1207 * '10' operate normally
1209 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1210 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1212 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1213 * '10' 12K, '11' 16K.
1215 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1216 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1217 * typical value 0x10 (about 1/2 msec)
1220 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1221 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1222 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1224 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1225 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1226 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1228 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1229 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1230 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1231 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1232 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1233 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1235 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1236 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1237 #define IWM_RX_RB_TIMEOUT (0x11)
1239 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1240 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1241 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1243 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1244 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1245 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1246 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1248 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1249 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1250 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1253 * Rx Shared Status Registers (RSSR)
1255 * After stopping Rx DMA channel (writing 0 to
1256 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1257 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1260 * 24: 1 = Channel 0 is idle
1262 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1263 * contain default values that should not be altered by the driver.
1265 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1266 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1268 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1269 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1270 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1271 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1273 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1275 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1277 /* TFDB Area - TFDs buffer table */
1278 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1279 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1280 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1281 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1282 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1285 * Transmit DMA Channel Control/Status Registers (TCSR)
1287 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1288 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1289 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1291 * To use a Tx DMA channel, driver must initialize its
1292 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1294 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1295 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1297 * All other bits should be 0.
1300 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1301 * '10' operate normally
1302 * 29- 4: Reserved, set to "0"
1303 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1304 * 2- 0: Reserved, set to "0"
1306 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1307 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1309 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1310 #define IWM_FH_TCSR_CHNL_NUM (8)
1312 /* TCSR: tx_config register values */
1313 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1314 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1315 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1316 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1317 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1318 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1320 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1321 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1323 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1324 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1326 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1327 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1328 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1330 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1331 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1332 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1334 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1335 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1336 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1338 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1339 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1340 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1342 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1343 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1346 * Tx Shared Status Registers (TSSR)
1348 * After stopping Tx DMA channel (writing 0 to
1349 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1350 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1351 * (channel's buffers empty | no pending requests).
1354 * 31-24: 1 = Channel buffers empty (channel 7:0)
1355 * 23-16: 1 = No pending requests (channel 7:0)
1357 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1358 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1360 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1363 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1364 * 31: Indicates an address error when accessed to internal memory
1365 * uCode/driver must write "1" in order to clear this flag
1366 * 30: Indicates that Host did not send the expected number of dwords to FH
1367 * uCode/driver must write "1" in order to clear this flag
1368 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1369 * command was received from the scheduler while the TRB was already full
1370 * with previous command
1371 * uCode/driver must write "1" in order to clear this flag
1372 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1373 * bit is set, it indicates that the FH has received a full indication
1374 * from the RTC TxFIFO and the current value of the TxCredit counter was
1375 * not equal to zero. This mean that the credit mechanism was not
1376 * synchronized to the TxFIFO status
1377 * uCode/driver must write "1" in order to clear this flag
1379 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1380 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1382 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1384 /* Tx service channels */
1385 #define IWM_FH_SRVC_CHNL (9)
1386 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1387 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1388 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1389 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1391 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1392 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1395 /* Instruct FH to increment the retry count of a packet when
1396 * it is brought from the memory to TX-FIFO
1398 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1400 #define IWM_RX_QUEUE_SIZE 256
1401 #define IWM_RX_QUEUE_MASK 255
1402 #define IWM_RX_QUEUE_SIZE_LOG 8
1405 * RX related structures and functions
1407 #define IWM_RX_FREE_BUFFERS 64
1408 #define IWM_RX_LOW_WATERMARK 8
1411 * struct iwm_rb_status - reseve buffer status
1412 * host memory mapped FH registers
1413 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1414 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1415 * @finished_rb_num [0:11] - Indicates the index of the current RB
1416 * in which the last frame was written to
1417 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1418 * which was transferred
1420 struct iwm_rb_status {
1421 uint16_t closed_rb_num;
1422 uint16_t closed_fr_num;
1423 uint16_t finished_rb_num;
1424 uint16_t finished_fr_nam;
1429 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1430 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1431 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1432 IWM_TFD_QUEUE_SIZE_BC_DUP)
1433 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1434 #define IWM_NUM_OF_TBS 20
1436 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1438 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1441 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1443 * This structure contains dma address and length of transmission address
1445 * @lo: low [31:0] portion of the dma address of TX buffer
1446 * every even is unaligned on 16 bit boundary
1447 * @hi_n_len 0-3 [35:32] portion of dma
1448 * 4-15 length of the tx buffer
1458 * Transmit Frame Descriptor (TFD)
1460 * @ __reserved1[3] reserved
1461 * @ num_tbs 0-4 number of active tbs
1463 * 6-7 padding (not used)
1464 * @ tbs[20] transmit frame buffer descriptors
1467 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1468 * Both driver and device share these circular buffers, each of which must be
1469 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1471 * Driver must indicate the physical address of the base of each
1472 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1474 * Each TFD contains pointer/size information for up to 20 data buffers
1475 * in host DRAM. These buffers collectively contain the (one) frame described
1476 * by the TFD. Each buffer must be a single contiguous block of memory within
1477 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1478 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1479 * Tx frame, up to 8 KBytes in size.
1481 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1484 uint8_t __reserved1[3];
1486 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1490 /* Keep Warm Size */
1491 #define IWM_KW_SIZE 0x1000 /* 4k */
1493 /* Fixed (non-configurable) rx data from phy */
1496 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1497 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1498 * @tfd_offset 0-12 - tx command byte count
1499 * 12-16 - station index
1501 struct iwm_agn_scd_bc_tbl {
1502 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1510 * BEGIN mvm/fw-api.h
1513 /* maximal number of Tx queues in any platform */
1514 #define IWM_MVM_MAX_QUEUES 20
1516 /* Tx queue numbers */
1518 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1519 IWM_MVM_CMD_QUEUE = 9,
1522 enum iwm_mvm_tx_fifo {
1523 IWM_MVM_TX_FIFO_BK = 0,
1527 IWM_MVM_TX_FIFO_MCAST = 5,
1528 IWM_MVM_TX_FIFO_CMD = 7,
1531 #define IWM_MVM_STATION_COUNT 16
1535 IWM_MVM_ALIVE = 0x1,
1536 IWM_REPLY_ERROR = 0x2,
1538 IWM_INIT_COMPLETE_NOTIF = 0x4,
1540 /* PHY context commands */
1541 IWM_PHY_CONTEXT_CMD = 0x8,
1545 IWM_ADD_STA_KEY = 0x17,
1547 IWM_REMOVE_STA = 0x19,
1551 IWM_TXPATH_FLUSH = 0x1e,
1552 IWM_MGMT_MCAST_KEY = 0x1f,
1557 /* MAC and Binding commands */
1558 IWM_MAC_CONTEXT_CMD = 0x28,
1559 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1560 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1561 IWM_BINDING_CONTEXT_CMD = 0x2b,
1562 IWM_TIME_QUOTA_CMD = 0x2c,
1563 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1568 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1569 IWM_CALIBRATION_CFG_CMD = 0x65,
1570 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1571 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1572 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1575 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1576 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1577 IWM_SCAN_OFFLOAD_COMPLETE = 0x6D,
1578 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6E,
1579 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1580 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1583 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1584 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1585 /* IWM_PHY_DB_CMD = 0x6c, */
1587 /* Power - legacy power table command */
1588 IWM_POWER_TABLE_CMD = 0x77,
1589 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1591 /* Thermal Throttling*/
1592 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1595 IWM_SCAN_REQUEST_CMD = 0x80,
1596 IWM_SCAN_ABORT_CMD = 0x81,
1597 IWM_SCAN_START_NOTIFICATION = 0x82,
1598 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1599 IWM_SCAN_COMPLETE_NOTIFICATION = 0x84,
1602 IWM_NVM_ACCESS_CMD = 0x88,
1604 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1606 IWM_BEACON_NOTIFICATION = 0x90,
1607 IWM_BEACON_TEMPLATE_CMD = 0x91,
1608 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1609 IWM_BT_CONFIG = 0x9b,
1610 IWM_STATISTICS_NOTIFICATION = 0x9d,
1611 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1613 /* RF-KILL commands and notifications */
1614 IWM_CARD_STATE_CMD = 0xa0,
1615 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1617 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1619 /* Power - new power table command */
1620 IWM_MAC_PM_POWER_TABLE = 0xa9,
1622 IWM_REPLY_RX_PHY_CMD = 0xc0,
1623 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1624 IWM_BA_NOTIF = 0xc5,
1627 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1628 IWM_BT_COEX_PROT_ENV = 0xcd,
1629 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1630 IWM_BT_COEX_CI = 0x5d,
1632 IWM_REPLY_SF_CFG_CMD = 0xd1,
1633 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1635 IWM_REPLY_DEBUG_CMD = 0xf0,
1636 IWM_DEBUG_LOG_MSG = 0xf7,
1638 IWM_MCAST_FILTER_CMD = 0xd0,
1640 /* D3 commands/notifications */
1641 IWM_D3_CONFIG_CMD = 0xd3,
1642 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1643 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1644 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1646 /* for WoWLAN in particular */
1647 IWM_WOWLAN_PATTERNS = 0xe0,
1648 IWM_WOWLAN_CONFIGURATION = 0xe1,
1649 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1650 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1651 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1652 IWM_WOWLAN_GET_STATUSES = 0xe5,
1653 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1655 /* and for NetDetect */
1656 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1657 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1658 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1659 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1660 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1662 IWM_REPLY_MAX = 0xff,
1666 * struct iwm_cmd_response - generic response struct for most commands
1667 * @status: status of the command asked, changes for each one
1669 struct iwm_cmd_response {
1674 * struct iwm_tx_ant_cfg_cmd
1675 * @valid: valid antenna configuration
1677 struct iwm_tx_ant_cfg_cmd {
1682 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1683 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1684 * @flags: (reserved for future implementation)
1685 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1686 * @pwr_restriction: TX power restriction in dBms.
1688 struct iwm_reduce_tx_power_cmd {
1690 uint8_t mac_context_id;
1691 uint16_t pwr_restriction;
1692 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1695 * Calibration control struct.
1696 * Sent as part of the phy configuration command.
1697 * @flow_trigger: bitmap for which calibrations to perform according to
1699 * @event_trigger: bitmap for which calibrations to perform according to
1702 struct iwm_calib_ctrl {
1703 uint32_t flow_trigger;
1704 uint32_t event_trigger;
1707 /* This enum defines the bitmap of various calibrations to enable in both
1708 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1710 enum iwm_calib_cfg {
1711 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1712 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1713 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1714 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1715 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1716 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1717 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1718 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1719 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1720 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1721 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1722 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1723 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1724 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1725 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1726 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1727 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1728 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1729 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1733 * Phy configuration command.
1735 struct iwm_phy_cfg_cmd {
1737 struct iwm_calib_ctrl calib_control;
1740 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1741 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1742 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1743 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1744 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1745 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1746 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1747 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1748 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1749 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1755 enum iwm_phy_db_section_type {
1757 IWM_PHY_DB_CALIB_NCH,
1759 IWM_PHY_DB_CALIB_CHG_PAPD,
1760 IWM_PHY_DB_CALIB_CHG_TXP,
1764 #define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */
1767 * phy db - configure operational ucode
1769 struct iwm_phy_db_cmd {
1775 /* for parsing of tx power channel group data that comes from the firmware */
1776 struct iwm_phy_db_chg_txp {
1778 uint16_t max_channel_idx;
1782 * phy db - Receive phy db chunk after calibrations
1784 struct iwm_calib_res_notif_phy_db {
1791 /* Target of the IWM_NVM_ACCESS_CMD */
1793 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1794 IWM_NVM_ACCESS_TARGET_OTP = 1,
1795 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1798 /* Section types for IWM_NVM_ACCESS_CMD */
1800 IWM_NVM_SECTION_TYPE_HW = 0,
1801 IWM_NVM_SECTION_TYPE_SW,
1802 IWM_NVM_SECTION_TYPE_PAPD,
1803 IWM_NVM_SECTION_TYPE_BT,
1804 IWM_NVM_SECTION_TYPE_CALIBRATION,
1805 IWM_NVM_SECTION_TYPE_PRODUCTION,
1806 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB,
1807 IWM_NVM_NUM_OF_SECTIONS,
1811 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1812 * @op_code: 0 - read, 1 - write
1813 * @target: IWM_NVM_ACCESS_TARGET_*
1814 * @type: IWM_NVM_SECTION_TYPE_*
1815 * @offset: offset in bytes into the section
1816 * @length: in bytes, to read/write
1817 * @data: if write operation, the data to write. On read its empty
1819 struct iwm_nvm_access_cmd {
1826 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
1829 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
1830 * @offset: offset in bytes into the section
1831 * @length: in bytes, either how much was written or read
1832 * @type: IWM_NVM_SECTION_TYPE_*
1833 * @status: 0 for success, fail otherwise
1834 * @data: if read operation, the data returned. Empty on write.
1836 struct iwm_nvm_access_resp {
1842 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
1844 /* IWM_MVM_ALIVE 0x1 */
1846 /* alive response is_valid values */
1847 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
1848 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
1850 /* alive response ver_type values */
1853 IWM_FW_TYPE_PROT = 1,
1855 IWM_FW_TYPE_WOWLAN = 3,
1856 IWM_FW_TYPE_TIMING = 4,
1857 IWM_FW_TYPE_WIPAN = 5
1860 /* alive response ver_subtype values */
1862 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
1863 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
1864 IWM_FW_SUBTYPE_REDUCED = 2,
1865 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
1866 IWM_FW_SUBTYPE_WOWLAN = 4,
1867 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
1868 IWM_FW_SUBTYPE_WIPAN = 6,
1869 IWM_FW_SUBTYPE_INITIALIZE = 9
1872 #define IWM_ALIVE_STATUS_ERR 0xDEAD
1873 #define IWM_ALIVE_STATUS_OK 0xCAFE
1875 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
1877 struct iwm_mvm_alive_resp {
1880 uint8_t ucode_minor;
1881 uint8_t ucode_major;
1885 uint8_t ver_subtype;
1891 uint32_t error_event_table_ptr; /* SRAM address for error log */
1892 uint32_t log_event_table_ptr; /* SRAM address for event log */
1893 uint32_t cpu_register_ptr;
1894 uint32_t dbgm_config_ptr;
1895 uint32_t alive_counter_ptr;
1896 uint32_t scd_base_ptr; /* SRAM address for SCD */
1897 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
1899 /* Error response/notification */
1901 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
1902 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
1903 IWM_FW_ERR_SERVICE = 0x2,
1904 IWM_FW_ERR_ARC_MEMORY = 0x3,
1905 IWM_FW_ERR_ARC_CODE = 0x4,
1906 IWM_FW_ERR_WATCH_DOG = 0x5,
1907 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
1908 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
1909 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
1910 IWM_FW_ERR_UNEXPECTED = 0xFE,
1911 IWM_FW_ERR_FATAL = 0xFF
1915 * struct iwm_error_resp - FW error indication
1916 * ( IWM_REPLY_ERROR = 0x2 )
1917 * @error_type: one of IWM_FW_ERR_*
1918 * @cmd_id: the command ID for which the error occurred
1919 * @bad_cmd_seq_num: sequence number of the erroneous command
1920 * @error_service: which service created the error, applicable only if
1921 * error_type = 2, otherwise 0
1922 * @timestamp: TSF in usecs.
1924 struct iwm_error_resp {
1925 uint32_t error_type;
1928 uint16_t bad_cmd_seq_num;
1929 uint32_t error_service;
1934 /* Common PHY, MAC and Bindings definitions */
1936 #define IWM_MAX_MACS_IN_BINDING (3)
1937 #define IWM_MAX_BINDINGS (4)
1938 #define IWM_AUX_BINDING_INDEX (3)
1939 #define IWM_MAX_PHYS (4)
1941 /* Used to extract ID and color from the context dword */
1942 #define IWM_FW_CTXT_ID_POS (0)
1943 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
1944 #define IWM_FW_CTXT_COLOR_POS (8)
1945 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
1946 #define IWM_FW_CTXT_INVALID (0xffffffff)
1948 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
1949 (_color << IWM_FW_CTXT_COLOR_POS))
1951 /* Possible actions on PHYs, MACs and Bindings */
1953 IWM_FW_CTXT_ACTION_STUB = 0,
1954 IWM_FW_CTXT_ACTION_ADD,
1955 IWM_FW_CTXT_ACTION_MODIFY,
1956 IWM_FW_CTXT_ACTION_REMOVE,
1957 IWM_FW_CTXT_ACTION_NUM
1958 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
1962 /* Time Event types, according to MAC type */
1963 enum iwm_time_event_type {
1964 /* BSS Station Events */
1965 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
1966 IWM_TE_BSS_STA_ASSOC,
1967 IWM_TE_BSS_EAP_DHCP_PROT,
1968 IWM_TE_BSS_QUIET_PERIOD,
1970 /* P2P Device Events */
1971 IWM_TE_P2P_DEVICE_DISCOVERABLE,
1972 IWM_TE_P2P_DEVICE_LISTEN,
1973 IWM_TE_P2P_DEVICE_ACTION_SCAN,
1974 IWM_TE_P2P_DEVICE_FULL_SCAN,
1976 /* P2P Client Events */
1977 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
1978 IWM_TE_P2P_CLIENT_ASSOC,
1979 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
1982 IWM_TE_P2P_GO_ASSOC_PROT,
1983 IWM_TE_P2P_GO_REPETITIVE_NOA,
1984 IWM_TE_P2P_GO_CT_WINDOW,
1986 /* WiDi Sync Events */
1987 IWM_TE_WIDI_TX_SYNC,
1990 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
1994 /* Time event - defines for command API v1 */
1997 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
1998 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
1999 * the first fragment is scheduled.
2000 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2001 * the first 2 fragments are scheduled.
2002 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2003 * number of fragments are valid.
2005 * Other than the constant defined above, specifying a fragmentation value 'x'
2006 * means that the event can be fragmented but only the first 'x' will be
2010 IWM_TE_V1_FRAG_NONE = 0,
2011 IWM_TE_V1_FRAG_SINGLE = 1,
2012 IWM_TE_V1_FRAG_DUAL = 2,
2013 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2016 /* If a Time Event can be fragmented, this is the max number of fragments */
2017 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2018 /* Repeat the time event endlessly (until removed) */
2019 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2020 /* If a Time Event has bounded repetitions, this is the maximal value */
2021 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2023 /* Time Event dependencies: none, on another TE, or in a specific time */
2025 IWM_TE_V1_INDEPENDENT = 0,
2026 IWM_TE_V1_DEP_OTHER = (1 << 0),
2027 IWM_TE_V1_DEP_TSF = (1 << 1),
2028 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2029 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2032 * @IWM_TE_V1_NOTIF_NONE: no notifications
2033 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2034 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2035 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2036 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2037 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2038 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2039 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2040 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2042 * Supported Time event notifications configuration.
2043 * A notification (both event and fragment) includes a status indicating weather
2044 * the FW was able to schedule the event or not. For fragment start/end
2045 * notification the status is always success. There is no start/end fragment
2046 * notification for monolithic events.
2049 IWM_TE_V1_NOTIF_NONE = 0,
2050 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2051 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2052 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2053 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2054 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2055 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2056 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2057 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2058 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2062 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2063 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2064 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2065 * ( IWM_TIME_EVENT_CMD = 0x29 )
2066 * @id_and_color: ID and color of the relevant MAC
2067 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2068 * @id: this field has two meanings, depending on the action:
2069 * If the action is ADD, then it means the type of event to add.
2070 * For all other actions it is the unique event ID assigned when the
2071 * event was added by the FW.
2072 * @apply_time: When to start the Time Event (in GP2)
2073 * @max_delay: maximum delay to event's start (apply time), in TU
2074 * @depends_on: the unique ID of the event we depend on (if any)
2075 * @interval: interval between repetitions, in TU
2076 * @interval_reciprocal: 2^32 / interval
2077 * @duration: duration of event in TU
2078 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2079 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2080 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2081 * @is_present: 0 or 1, are we present or absent during the Time Event
2082 * @max_frags: maximal number of fragments the Time Event can be divided to
2083 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2085 struct iwm_time_event_cmd_v1 {
2086 /* COMMON_INDEX_HDR_API_S_VER_1 */
2087 uint32_t id_and_color;
2090 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2091 uint32_t apply_time;
2093 uint32_t dep_policy;
2094 uint32_t depends_on;
2095 uint32_t is_present;
2098 uint32_t interval_reciprocal;
2102 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2105 /* Time event - defines for command API v2 */
2108 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2109 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2110 * the first fragment is scheduled.
2111 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2112 * the first 2 fragments are scheduled.
2113 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2114 * number of fragments are valid.
2116 * Other than the constant defined above, specifying a fragmentation value 'x'
2117 * means that the event can be fragmented but only the first 'x' will be
2121 IWM_TE_V2_FRAG_NONE = 0,
2122 IWM_TE_V2_FRAG_SINGLE = 1,
2123 IWM_TE_V2_FRAG_DUAL = 2,
2124 IWM_TE_V2_FRAG_MAX = 0xfe,
2125 IWM_TE_V2_FRAG_ENDLESS = 0xff
2128 /* Repeat the time event endlessly (until removed) */
2129 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2130 /* If a Time Event has bounded repetitions, this is the maximal value */
2131 #define IWM_TE_V2_REPEAT_MAX 0xfe
2133 #define IWM_TE_V2_PLACEMENT_POS 12
2134 #define IWM_TE_V2_ABSENCE_POS 15
2136 /* Time event policy values (for time event cmd api v2)
2137 * A notification (both event and fragment) includes a status indicating weather
2138 * the FW was able to schedule the event or not. For fragment start/end
2139 * notification the status is always success. There is no start/end fragment
2140 * notification for monolithic events.
2142 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2143 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2144 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2145 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2146 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2147 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2148 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2149 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2150 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2151 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2152 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2153 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2154 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2157 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2159 /* notifications (event start/stop, fragment start/stop) */
2160 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2161 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2162 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2163 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2165 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2166 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2167 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2168 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2170 IWM_TE_V2_NOTIF_MSK = 0xff,
2172 /* placement characteristics */
2173 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2174 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2175 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2177 /* are we present or absent during the Time Event. */
2178 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2182 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2183 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2184 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2185 * ( IWM_TIME_EVENT_CMD = 0x29 )
2186 * @id_and_color: ID and color of the relevant MAC
2187 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2188 * @id: this field has two meanings, depending on the action:
2189 * If the action is ADD, then it means the type of event to add.
2190 * For all other actions it is the unique event ID assigned when the
2191 * event was added by the FW.
2192 * @apply_time: When to start the Time Event (in GP2)
2193 * @max_delay: maximum delay to event's start (apply time), in TU
2194 * @depends_on: the unique ID of the event we depend on (if any)
2195 * @interval: interval between repetitions, in TU
2196 * @duration: duration of event in TU
2197 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2198 * @max_frags: maximal number of fragments the Time Event can be divided to
2199 * @policy: defines whether uCode shall notify the host or other uCode modules
2200 * on event and/or fragment start and/or end
2201 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2202 * IWM_TE_EVENT_SOCIOPATHIC
2203 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2205 struct iwm_time_event_cmd_v2 {
2206 /* COMMON_INDEX_HDR_API_S_VER_1 */
2207 uint32_t id_and_color;
2210 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2211 uint32_t apply_time;
2213 uint32_t depends_on;
2219 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2222 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2223 * @status: bit 0 indicates success, all others specify errors
2224 * @id: the Time Event type
2225 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2226 * @id_and_color: ID and color of the relevant MAC
2228 struct iwm_time_event_resp {
2232 uint32_t id_and_color;
2233 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2236 * struct iwm_time_event_notif - notifications of time event start/stop
2237 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2238 * @timestamp: action timestamp in GP2
2239 * @session_id: session's unique id
2240 * @unique_id: unique id of the Time Event itself
2241 * @id_and_color: ID and color of the relevant MAC
2242 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2243 * @status: true if scheduled, false otherwise (not executed)
2245 struct iwm_time_event_notif {
2247 uint32_t session_id;
2249 uint32_t id_and_color;
2252 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2255 /* Bindings and Time Quota */
2258 * struct iwm_binding_cmd - configuring bindings
2259 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2260 * @id_and_color: ID and color of the relevant Binding
2261 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2262 * @macs: array of MAC id and colors which belong to the binding
2263 * @phy: PHY id and color which belongs to the binding
2265 struct iwm_binding_cmd {
2266 /* COMMON_INDEX_HDR_API_S_VER_1 */
2267 uint32_t id_and_color;
2269 /* IWM_BINDING_DATA_API_S_VER_1 */
2270 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2272 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2274 /* The maximal number of fragments in the FW's schedule session */
2275 #define IWM_MVM_MAX_QUOTA 128
2278 * struct iwm_time_quota_data - configuration of time quota per binding
2279 * @id_and_color: ID and color of the relevant Binding
2280 * @quota: absolute time quota in TU. The scheduler will try to divide the
2281 * remainig quota (after Time Events) according to this quota.
2282 * @max_duration: max uninterrupted context duration in TU
2284 struct iwm_time_quota_data {
2285 uint32_t id_and_color;
2287 uint32_t max_duration;
2288 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2291 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2292 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2293 * @quotas: allocations per binding
2295 struct iwm_time_quota_cmd {
2296 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2297 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2302 /* Supported bands */
2303 #define IWM_PHY_BAND_5 (0)
2304 #define IWM_PHY_BAND_24 (1)
2306 /* Supported channel width, vary if there is VHT support */
2307 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2308 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2309 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2310 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2313 * Control channel position:
2314 * For legacy set bit means upper channel, otherwise lower.
2315 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2316 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2319 * 40Mhz |_______|_______|
2320 * 80Mhz |_______|_______|_______|_______|
2321 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2322 * code 011 010 001 000 | 100 101 110 111
2324 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2325 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2326 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2327 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2328 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2329 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2330 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2331 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2334 * @band: IWM_PHY_BAND_*
2335 * @channel: channel number
2336 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2337 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2339 struct iwm_fw_channel_info {
2346 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2347 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2348 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2349 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2350 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2351 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2352 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2353 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2354 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2355 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2356 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2357 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2358 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2359 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2360 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2361 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2362 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2363 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2364 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2365 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2366 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2368 /* TODO: fix the value, make it depend on firmware at runtime? */
2369 #define IWM_NUM_PHY_CTX 3
2371 /* TODO: complete missing documentation */
2373 * struct iwm_phy_context_cmd - config of the PHY context
2374 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2375 * @id_and_color: ID and color of the relevant Binding
2376 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2377 * @apply_time: 0 means immediate apply and context switch.
2378 * other value means apply new params after X usecs
2379 * @tx_param_color: ???
2381 * @txchain_info: ???
2382 * @rxchain_info: ???
2383 * @acquisition_data: ???
2384 * @dsp_cfg_flags: set to 0
2386 struct iwm_phy_context_cmd {
2387 /* COMMON_INDEX_HDR_API_S_VER_1 */
2388 uint32_t id_and_color;
2390 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2391 uint32_t apply_time;
2392 uint32_t tx_param_color;
2393 struct iwm_fw_channel_info ci;
2394 uint32_t txchain_info;
2395 uint32_t rxchain_info;
2396 uint32_t acquisition_data;
2397 uint32_t dsp_cfg_flags;
2398 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2400 #define IWM_RX_INFO_PHY_CNT 8
2401 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2402 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2403 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2404 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2405 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2406 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2407 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2409 #define IWM_RX_INFO_AGC_IDX 1
2410 #define IWM_RX_INFO_RSSI_AB_IDX 2
2411 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2412 #define IWM_OFDM_AGC_A_POS 0
2413 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2414 #define IWM_OFDM_AGC_B_POS 7
2415 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2416 #define IWM_OFDM_AGC_CODE_POS 20
2417 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2418 #define IWM_OFDM_RSSI_A_POS 0
2419 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2420 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2421 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2422 #define IWM_OFDM_RSSI_B_POS 16
2423 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2424 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2427 * struct iwm_rx_phy_info - phy info
2428 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2429 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2430 * @cfg_phy_cnt: configurable DSP phy data byte count
2431 * @stat_id: configurable DSP phy data set ID
2433 * @system_timestamp: GP2 at on air rise
2434 * @timestamp: TSF at on air rise
2435 * @beacon_time_stamp: beacon at on-air rise
2436 * @phy_flags: general phy flags: band, modulation, ...
2437 * @channel: channel number
2438 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2439 * @rate_n_flags: IWM_RATE_MCS_*
2440 * @byte_count: frame's byte-count
2441 * @frame_time: frame's time on the air, based on byte count and frame rate
2443 * @mac_active_msk: what MACs were active when the frame was received
2445 * Before each Rx, the device sends this data. It contains PHY information
2446 * about the reception of the packet.
2448 struct iwm_rx_phy_info {
2449 uint8_t non_cfg_phy_cnt;
2450 uint8_t cfg_phy_cnt;
2453 uint32_t system_timestamp;
2455 uint32_t beacon_time_stamp;
2457 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2459 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2463 uint32_t byte_count;
2464 uint16_t mac_active_msk;
2465 uint16_t frame_time;
2468 struct iwm_rx_mpdu_res_start {
2469 uint16_t byte_count;
2474 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2475 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2476 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2477 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2478 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2479 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2480 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2481 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2482 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2483 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2485 enum iwm_rx_phy_flags {
2486 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2487 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2488 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2489 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2490 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2491 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2492 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2493 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2494 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2495 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2499 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2500 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2501 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2502 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2503 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2504 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2505 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2506 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2508 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2509 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2510 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2511 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2512 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2513 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2514 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2515 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2516 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2517 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2518 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2519 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2520 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2521 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2522 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2523 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2524 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2525 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2526 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2527 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2528 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2530 enum iwm_mvm_rx_status {
2531 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2532 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2533 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2534 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2535 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2536 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2537 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2538 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2539 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2540 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2541 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2542 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2543 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2544 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2545 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2546 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2547 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2548 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2549 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2550 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2551 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2552 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2553 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2554 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2555 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2556 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2557 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2561 * struct iwm_radio_version_notif - information on the radio version
2562 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2567 struct iwm_radio_version_notif {
2568 uint32_t radio_flavor;
2569 uint32_t radio_step;
2570 uint32_t radio_dash;
2571 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2573 enum iwm_card_state_flags {
2574 IWM_CARD_ENABLED = 0x00,
2575 IWM_HW_CARD_DISABLED = 0x01,
2576 IWM_SW_CARD_DISABLED = 0x02,
2577 IWM_CT_KILL_CARD_DISABLED = 0x04,
2578 IWM_HALT_CARD_DISABLED = 0x08,
2579 IWM_CARD_DISABLED_MSK = 0x0f,
2580 IWM_CARD_IS_RX_ON = 0x10,
2584 * struct iwm_radio_version_notif - information on the radio version
2585 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2586 * @flags: %iwm_card_state_flags
2588 struct iwm_card_state_notif {
2590 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2593 * struct iwm_missed_beacons_notif - information on missed beacons
2594 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2595 * @mac_id: interface ID
2596 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2597 * beacons since last RX.
2598 * @consec_missed_beacons: number of consecutive missed beacons
2599 * @num_expected_beacons:
2600 * @num_recvd_beacons:
2602 struct iwm_missed_beacons_notif {
2604 uint32_t consec_missed_beacons_since_last_rx;
2605 uint32_t consec_missed_beacons;
2606 uint32_t num_expected_beacons;
2607 uint32_t num_recvd_beacons;
2608 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2611 * struct iwm_set_calib_default_cmd - set default value for calibration.
2612 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2613 * @calib_index: the calibration to set value for
2615 * @data: the value to set for the calibration result
2617 struct iwm_set_calib_default_cmd {
2618 uint16_t calib_index;
2621 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2623 #define IWM_MAX_PORT_ID_NUM 2
2624 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2627 * struct iwm_mcast_filter_cmd - configure multicast filter.
2628 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2629 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2630 * to identify network interface adopted in host-device IF.
2631 * It is used by FW as index in array of addresses. This array has
2632 * IWM_MAX_PORT_ID_NUM members.
2633 * @count: Number of MAC addresses in the array
2634 * @pass_all: Set 1 to pass all multicast packets.
2635 * @bssid: current association BSSID.
2636 * @addr_list: Place holder for array of MAC addresses.
2637 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2639 struct iwm_mcast_filter_cmd {
2645 uint8_t reserved[2];
2646 uint8_t addr_list[0];
2647 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2649 struct iwm_mvm_statistics_dbg {
2650 uint32_t burst_check;
2651 uint32_t burst_count;
2652 uint32_t wait_for_silence_timeout_cnt;
2653 uint32_t reserved[3];
2654 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2656 struct iwm_mvm_statistics_div {
2660 uint32_t probe_time;
2663 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2665 struct iwm_mvm_statistics_general_common {
2666 uint32_t temperature; /* radio temperature */
2667 uint32_t temperature_m; /* radio voltage */
2668 struct iwm_mvm_statistics_dbg dbg;
2669 uint32_t sleep_time;
2671 uint32_t slots_idle;
2672 uint32_t ttl_timestamp;
2673 struct iwm_mvm_statistics_div div;
2674 uint32_t rx_enable_counter;
2676 * num_of_sos_states:
2677 * count the number of times we have to re-tune
2678 * in order to get out of bad PHY status
2680 uint32_t num_of_sos_states;
2681 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2683 struct iwm_mvm_statistics_rx_non_phy {
2684 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2685 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2686 uint32_t non_bssid_frames; /* number of frames with BSSID that
2687 * doesn't belong to the STA BSSID */
2688 uint32_t filtered_frames; /* count frames that were dumped in the
2689 * filtering process */
2690 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2691 * our serving channel */
2692 uint32_t channel_beacons; /* beacons with our bss id and in our
2693 * serving channel */
2694 uint32_t num_missed_bcon; /* number of missed beacons */
2695 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2696 * ADC was in saturation */
2697 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2699 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2700 uint32_t interference_data_flag; /* flag for interference data
2701 * availability. 1 when data is
2703 uint32_t channel_load; /* counts RX Enable time in uSec */
2704 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2705 * and CCK) counter */
2706 uint32_t beacon_rssi_a;
2707 uint32_t beacon_rssi_b;
2708 uint32_t beacon_rssi_c;
2709 uint32_t beacon_energy_a;
2710 uint32_t beacon_energy_b;
2711 uint32_t beacon_energy_c;
2712 uint32_t num_bt_kills;
2714 uint32_t directed_data_mpdu;
2715 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2717 struct iwm_mvm_statistics_rx_phy {
2722 uint32_t overrun_err;
2723 uint32_t early_overrun_err;
2724 uint32_t crc32_good;
2725 uint32_t false_alarm_cnt;
2726 uint32_t fina_sync_err_cnt;
2727 uint32_t sfd_timeout;
2728 uint32_t fina_timeout;
2729 uint32_t unresponded_rts;
2730 uint32_t rxe_frame_limit_overrun;
2731 uint32_t sent_ack_cnt;
2732 uint32_t sent_cts_cnt;
2733 uint32_t sent_ba_rsp_cnt;
2734 uint32_t dsp_self_kill;
2735 uint32_t mh_format_err;
2736 uint32_t re_acq_main_rssi_sum;
2738 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2740 struct iwm_mvm_statistics_rx_ht_phy {
2742 uint32_t overrun_err;
2743 uint32_t early_overrun_err;
2744 uint32_t crc32_good;
2746 uint32_t mh_format_err;
2747 uint32_t agg_crc32_good;
2748 uint32_t agg_mpdu_cnt;
2750 uint32_t unsupport_mcs;
2751 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
2753 #define IWM_MAX_CHAINS 3
2755 struct iwm_mvm_statistics_tx_non_phy_agg {
2756 uint32_t ba_timeout;
2757 uint32_t ba_reschedule_frames;
2758 uint32_t scd_query_agg_frame_cnt;
2759 uint32_t scd_query_no_agg;
2760 uint32_t scd_query_agg;
2761 uint32_t scd_query_mismatch;
2762 uint32_t frame_not_ready;
2764 uint32_t bt_prio_kill;
2765 uint32_t rx_ba_rsp_cnt;
2766 int8_t txpower[IWM_MAX_CHAINS];
2769 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
2771 struct iwm_mvm_statistics_tx_channel_width {
2772 uint32_t ext_cca_narrow_ch20[1];
2773 uint32_t ext_cca_narrow_ch40[2];
2774 uint32_t ext_cca_narrow_ch80[3];
2775 uint32_t ext_cca_narrow_ch160[4];
2776 uint32_t last_tx_ch_width_indx;
2777 uint32_t rx_detected_per_ch_width[4];
2778 uint32_t success_per_ch_width[4];
2779 uint32_t fail_per_ch_width[4];
2780 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
2782 struct iwm_mvm_statistics_tx {
2783 uint32_t preamble_cnt;
2784 uint32_t rx_detected_cnt;
2785 uint32_t bt_prio_defer_cnt;
2786 uint32_t bt_prio_kill_cnt;
2787 uint32_t few_bytes_cnt;
2788 uint32_t cts_timeout;
2789 uint32_t ack_timeout;
2790 uint32_t expected_ack_cnt;
2791 uint32_t actual_ack_cnt;
2792 uint32_t dump_msdu_cnt;
2793 uint32_t burst_abort_next_frame_mismatch_cnt;
2794 uint32_t burst_abort_missing_next_frame_cnt;
2795 uint32_t cts_timeout_collision;
2796 uint32_t ack_or_ba_timeout_collision;
2797 struct iwm_mvm_statistics_tx_non_phy_agg agg;
2798 struct iwm_mvm_statistics_tx_channel_width channel_width;
2799 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
2802 struct iwm_mvm_statistics_bt_activity {
2803 uint32_t hi_priority_tx_req_cnt;
2804 uint32_t hi_priority_tx_denied_cnt;
2805 uint32_t lo_priority_tx_req_cnt;
2806 uint32_t lo_priority_tx_denied_cnt;
2807 uint32_t hi_priority_rx_req_cnt;
2808 uint32_t hi_priority_rx_denied_cnt;
2809 uint32_t lo_priority_rx_req_cnt;
2810 uint32_t lo_priority_rx_denied_cnt;
2811 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
2813 struct iwm_mvm_statistics_general {
2814 struct iwm_mvm_statistics_general_common common;
2815 uint32_t beacon_filtered;
2816 uint32_t missed_beacons;
2817 int8_t beacon_filter_average_energy;
2818 int8_t beacon_filter_reason;
2819 int8_t beacon_filter_current_energy;
2820 int8_t beacon_filter_reserved;
2821 uint32_t beacon_filter_delta_time;
2822 struct iwm_mvm_statistics_bt_activity bt_activity;
2823 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2825 struct iwm_mvm_statistics_rx {
2826 struct iwm_mvm_statistics_rx_phy ofdm;
2827 struct iwm_mvm_statistics_rx_phy cck;
2828 struct iwm_mvm_statistics_rx_non_phy general;
2829 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
2830 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
2833 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
2835 * By default, uCode issues this notification after receiving a beacon
2836 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
2837 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
2839 * Statistics counters continue to increment beacon after beacon, but are
2840 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
2841 * 0x9c with CLEAR_STATS bit set (see above).
2843 * uCode also issues this notification during scans. uCode clears statistics
2844 * appropriately so that each notification contains statistics for only the
2845 * one channel that has just been scanned.
2848 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
2850 struct iwm_mvm_statistics_rx rx;
2851 struct iwm_mvm_statistics_tx tx;
2852 struct iwm_mvm_statistics_general general;
2855 /***********************************
2857 ***********************************/
2858 /* Smart Fifo state */
2860 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
2864 IWM_SF_HW_NUM_STATES
2867 /* Smart Fifo possible scenario */
2868 enum iwm_sf_scenario {
2869 IWM_SF_SCENARIO_SINGLE_UNICAST,
2870 IWM_SF_SCENARIO_AGG_UNICAST,
2871 IWM_SF_SCENARIO_MULTICAST,
2872 IWM_SF_SCENARIO_BA_RESP,
2873 IWM_SF_SCENARIO_TX_RESP,
2877 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
2878 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
2880 /* smart FIFO default values */
2881 #define IWM_SF_W_MARK_SISO 4096
2882 #define IWM_SF_W_MARK_MIMO2 8192
2883 #define IWM_SF_W_MARK_MIMO3 6144
2884 #define IWM_SF_W_MARK_LEGACY 4096
2885 #define IWM_SF_W_MARK_SCAN 4096
2887 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
2888 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2889 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2890 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
2891 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
2892 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
2893 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
2894 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
2895 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
2896 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
2897 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
2899 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
2902 * Smart Fifo configuration command.
2903 * @state: smart fifo state, types listed in iwm_sf_sate.
2904 * @watermark: Minimum allowed available free space in RXF for transient state.
2905 * @long_delay_timeouts: aging and idle timer values for each scenario
2906 * in long delay state.
2907 * @full_on_timeouts: timer values for each scenario in full on state.
2909 struct iwm_sf_cfg_cmd {
2910 enum iwm_sf_state state;
2911 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
2912 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2913 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
2914 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
2921 * BEGIN mvm/fw-api-mac.h
2925 * The first MAC indices (starting from 0)
2926 * are available to the driver, AUX follows
2928 #define IWM_MAC_INDEX_AUX 4
2929 #define IWM_MAC_INDEX_MIN_DRIVER 0
2930 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
2941 * enum iwm_mac_protection_flags - MAC context flags
2942 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
2943 * this will require CCK RTS/CTS2self.
2944 * RTS/CTS will protect full burst time.
2945 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
2946 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
2947 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
2949 enum iwm_mac_protection_flags {
2950 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
2951 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
2952 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
2953 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
2956 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
2957 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
2960 * enum iwm_mac_types - Supported MAC types
2961 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
2962 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
2963 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
2964 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
2965 * @IWM_FW_MAC_TYPE_IBSS: IBSS
2966 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
2967 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
2968 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
2969 * @IWM_FW_MAC_TYPE_GO: P2P GO
2970 * @IWM_FW_MAC_TYPE_TEST: ?
2971 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
2973 enum iwm_mac_types {
2974 IWM_FW_MAC_TYPE_FIRST = 1,
2975 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
2976 IWM_FW_MAC_TYPE_LISTENER,
2977 IWM_FW_MAC_TYPE_PIBSS,
2978 IWM_FW_MAC_TYPE_IBSS,
2979 IWM_FW_MAC_TYPE_BSS_STA,
2980 IWM_FW_MAC_TYPE_P2P_DEVICE,
2981 IWM_FW_MAC_TYPE_P2P_STA,
2983 IWM_FW_MAC_TYPE_TEST,
2984 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
2985 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
2988 * enum iwm_tsf_id - TSF hw timer ID
2989 * @IWM_TSF_ID_A: use TSF A
2990 * @IWM_TSF_ID_B: use TSF B
2991 * @IWM_TSF_ID_C: use TSF C
2992 * @IWM_TSF_ID_D: use TSF D
2993 * @IWM_NUM_TSF_IDS: number of TSF timers available
3000 IWM_NUM_TSF_IDS = 4,
3001 }; /* IWM_TSF_ID_API_E_VER_1 */
3004 * struct iwm_mac_data_ap - configuration data for AP MAC context
3005 * @beacon_time: beacon transmit time in system time
3006 * @beacon_tsf: beacon transmit time in TSF
3007 * @bi: beacon interval in TU
3008 * @bi_reciprocal: 2^32 / bi
3009 * @dtim_interval: dtim transmit time in TU
3010 * @dtim_reciprocal: 2^32 / dtim_interval
3011 * @mcast_qid: queue ID for multicast traffic
3012 * @beacon_template: beacon template ID
3014 struct iwm_mac_data_ap {
3015 uint32_t beacon_time;
3016 uint64_t beacon_tsf;
3018 uint32_t bi_reciprocal;
3019 uint32_t dtim_interval;
3020 uint32_t dtim_reciprocal;
3022 uint32_t beacon_template;
3023 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3026 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3027 * @beacon_time: beacon transmit time in system time
3028 * @beacon_tsf: beacon transmit time in TSF
3029 * @bi: beacon interval in TU
3030 * @bi_reciprocal: 2^32 / bi
3031 * @beacon_template: beacon template ID
3033 struct iwm_mac_data_ibss {
3034 uint32_t beacon_time;
3035 uint64_t beacon_tsf;
3037 uint32_t bi_reciprocal;
3038 uint32_t beacon_template;
3039 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3042 * struct iwm_mac_data_sta - configuration data for station MAC context
3043 * @is_assoc: 1 for associated state, 0 otherwise
3044 * @dtim_time: DTIM arrival time in system time
3045 * @dtim_tsf: DTIM arrival time in TSF
3046 * @bi: beacon interval in TU, applicable only when associated
3047 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3048 * @dtim_interval: DTIM interval in TU, applicable only when associated
3049 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3050 * @listen_interval: in beacon intervals, applicable only when associated
3051 * @assoc_id: unique ID assigned by the AP during association
3053 struct iwm_mac_data_sta {
3058 uint32_t bi_reciprocal;
3059 uint32_t dtim_interval;
3060 uint32_t dtim_reciprocal;
3061 uint32_t listen_interval;
3063 uint32_t assoc_beacon_arrive_time;
3064 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3067 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3068 * @ap: iwm_mac_data_ap struct with most config data
3069 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3070 * 0 indicates that there is no CT window.
3071 * @opp_ps_enabled: indicate that opportunistic PS allowed
3073 struct iwm_mac_data_go {
3074 struct iwm_mac_data_ap ap;
3076 uint32_t opp_ps_enabled;
3077 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3080 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3081 * @sta: iwm_mac_data_sta struct with most config data
3082 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3083 * 0 indicates that there is no CT window.
3085 struct iwm_mac_data_p2p_sta {
3086 struct iwm_mac_data_sta sta;
3088 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3091 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3092 * @stats_interval: interval in TU between statistics notifications to host.
3094 struct iwm_mac_data_pibss {
3095 uint32_t stats_interval;
3096 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3099 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3101 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3102 * other channels as well. This should be to true only in case that the
3103 * device is discoverable and there is an active GO. Note that setting this
3104 * field when not needed, will increase the number of interrupts and have
3105 * effect on the platform power, as this setting opens the Rx filters on
3108 struct iwm_mac_data_p2p_dev {
3109 uint32_t is_disc_extended;
3110 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3113 * enum iwm_mac_filter_flags - MAC context filter flags
3114 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3115 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3116 * control frames to the host
3117 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3118 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3119 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3120 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3121 * (in station mode when associated)
3122 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3123 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3124 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3126 enum iwm_mac_filter_flags {
3127 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3128 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3129 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3130 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3131 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3132 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3133 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3134 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3135 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3139 * enum iwm_mac_qos_flags - QoS flags
3140 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3141 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3142 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3145 enum iwm_mac_qos_flags {
3146 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3147 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3148 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3152 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3153 * @cw_min: Contention window, start value in numbers of slots.
3154 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3155 * @cw_max: Contention window, max value in numbers of slots.
3156 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3157 * @aifsn: Number of slots in Arbitration Interframe Space (before
3158 * performing random backoff timing prior to Tx). Device default 1.
3159 * @fifos_mask: FIFOs used by this MAC for this AC
3160 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3162 * One instance of this config struct for each of 4 EDCA access categories
3163 * in struct iwm_qosparam_cmd.
3165 * Device will automatically increase contention window by (2*CW) + 1 for each
3166 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3167 * value, to cap the CW value.
3175 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3178 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3179 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3180 * @id_and_color: ID and color of the MAC
3181 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3182 * @mac_type: one of IWM_FW_MAC_TYPE_*
3183 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3184 * @node_addr: MAC address
3185 * @bssid_addr: BSSID
3186 * @cck_rates: basic rates available for CCK
3187 * @ofdm_rates: basic rates available for OFDM
3188 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3189 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3190 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3191 * @filter_flags: combination of IWM_MAC_FILTER_*
3192 * @qos_flags: from IWM_MAC_QOS_FLG_*
3193 * @ac: one iwm_mac_qos configuration for each AC
3194 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3196 struct iwm_mac_ctx_cmd {
3197 /* COMMON_INDEX_HDR_API_S_VER_1 */
3198 uint32_t id_and_color;
3200 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3203 uint8_t node_addr[6];
3204 uint16_t reserved_for_node_addr;
3205 uint8_t bssid_addr[6];
3206 uint16_t reserved_for_bssid_addr;
3208 uint32_t ofdm_rates;
3209 uint32_t protection_flags;
3210 uint32_t cck_short_preamble;
3211 uint32_t short_slot;
3212 uint32_t filter_flags;
3213 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3215 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3216 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3218 struct iwm_mac_data_ap ap;
3219 struct iwm_mac_data_go go;
3220 struct iwm_mac_data_sta sta;
3221 struct iwm_mac_data_p2p_sta p2p_sta;
3222 struct iwm_mac_data_p2p_dev p2p_dev;
3223 struct iwm_mac_data_pibss pibss;
3224 struct iwm_mac_data_ibss ibss;
3226 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3228 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3232 return 0xFFFFFFFF / v;
3235 #define IWM_NONQOS_SEQ_GET 0x1
3236 #define IWM_NONQOS_SEQ_SET 0x2
3237 struct iwm_nonqos_seq_query_cmd {
3238 uint32_t get_set_flag;
3239 uint32_t mac_id_n_color;
3242 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3245 * END mvm/fw-api-mac.h
3249 * BEGIN mvm/fw-api-power.h
3252 /* Power Management Commands, Responses, Notifications */
3254 /* Radio LP RX Energy Threshold measured in dBm */
3255 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3256 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3257 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3260 * enum iwm_scan_flags - masks for power table command flags
3261 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3262 * receiver and transmitter. '0' - does not allow.
3263 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3264 * '1' Driver enables PM (use rest of parameters)
3265 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3266 * '1' PM could sleep over DTIM till listen Interval.
3267 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3268 * access categories are both delivery and trigger enabled.
3269 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3270 * PBW Snoozing enabled
3271 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3272 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3273 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3274 * detection enablement
3276 enum iwm_power_flags {
3277 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3278 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3279 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3280 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3281 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3282 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3283 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3284 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3287 #define IWM_POWER_VEC_SIZE 5
3290 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3291 * is used also with a new power API for device wide power settings.
3292 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3294 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3295 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3296 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3297 * set regardless of power scheme or current power state.
3298 * FW use this value also when PM is disabled.
3299 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3300 * PSM transition - legacy PM
3301 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3302 * PSM transition - legacy PM
3303 * @sleep_interval: not in use
3304 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3305 * is set. For example, if it is required to skip over
3306 * one DTIM, this value need to be set to 2 (DTIM periods).
3307 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3310 struct iwm_powertable_cmd {
3311 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3313 uint8_t keep_alive_seconds;
3314 uint8_t debug_flags;
3315 uint32_t rx_data_timeout;
3316 uint32_t tx_data_timeout;
3317 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3318 uint32_t skip_dtim_periods;
3319 uint32_t lprx_rssi_threshold;
3323 * enum iwm_device_power_flags - masks for device power command flags
3324 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3325 * receiver and transmitter. '0' - does not allow. This flag should be
3326 * always set to '1' unless one need to disable actual power down for debug
3328 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3329 * that power management is disabled. '0' Power management is enabled, one
3330 * of power schemes is applied.
3332 enum iwm_device_power_flags {
3333 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3334 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3338 * struct iwm_device_power_cmd - device wide power command.
3339 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3341 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3343 struct iwm_device_power_cmd {
3344 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3350 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3351 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3352 * @id_and_color: MAC contex identifier
3353 * @flags: Power table command flags from POWER_FLAGS_*
3354 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3355 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3356 * set regardless of power scheme or current power state.
3357 * FW use this value also when PM is disabled.
3358 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3359 * PSM transition - legacy PM
3360 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3361 * PSM transition - legacy PM
3362 * @sleep_interval: not in use
3363 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3364 * is set. For example, if it is required to skip over
3365 * one DTIM, this value need to be set to 2 (DTIM periods).
3366 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3367 * PSM transition - uAPSD
3368 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3369 * PSM transition - uAPSD
3370 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3372 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3373 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3374 * from the AP [msec]
3375 * @snooze_window: A window of time in which PBW snoozing insures that all
3376 * packets received. It is also the minimum time from last
3377 * received unicast RX packet, before client stops snoozing
3380 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3381 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3382 * each corresponding AC.
3383 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3384 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3386 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3387 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3388 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3389 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3390 * @limited_ps_threshold:
3392 struct iwm_mac_power_cmd {
3393 /* CONTEXT_DESC_API_T_VER_1 */
3394 uint32_t id_and_color;
3396 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3398 uint16_t keep_alive_seconds;
3399 uint32_t rx_data_timeout;
3400 uint32_t tx_data_timeout;
3401 uint32_t rx_data_timeout_uapsd;
3402 uint32_t tx_data_timeout_uapsd;
3403 uint8_t lprx_rssi_threshold;
3404 uint8_t skip_dtim_periods;
3405 uint16_t snooze_interval;
3406 uint16_t snooze_window;
3407 uint8_t snooze_step;
3409 uint8_t uapsd_ac_flags;
3410 uint8_t uapsd_max_sp;
3411 uint8_t heavy_tx_thld_packets;
3412 uint8_t heavy_rx_thld_packets;
3413 uint8_t heavy_tx_thld_percentage;
3414 uint8_t heavy_rx_thld_percentage;
3415 uint8_t limited_ps_threshold;
3420 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3421 * associated AP is identified as improperly implementing uAPSD protocol.
3422 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3423 * @sta_id: index of station in uCode's station table - associated AP ID in
3426 struct iwm_uapsd_misbehaving_ap_notif {
3429 uint8_t reserved[3];
3433 * struct iwm_beacon_filter_cmd
3434 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3435 * @id_and_color: MAC contex identifier
3436 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3437 * to driver if delta in Energy values calculated for this and last
3438 * passed beacon is greater than this threshold. Zero value means that
3439 * the Energy change is ignored for beacon filtering, and beacon will
3440 * not be forced to be sent to driver regardless of this delta. Typical
3442 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3443 * Send beacon to driver if delta in Energy values calculated for this
3444 * and last passed beacon is greater than this threshold. Zero value
3445 * means that the Energy change is ignored for beacon filtering while in
3446 * Roaming state, typical energy delta 1dB.
3447 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3448 * calculated for current beacon is less than the threshold, use
3449 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3450 * Threshold. Typical energy threshold is -72dBm.
3451 * @bf_temp_threshold: This threshold determines the type of temperature
3452 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3453 * If the current temperature is above this threshold - Fast filter
3454 * will be used, If the current temperature is below this threshold -
3455 * Slow filter will be used.
3456 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3457 * calculated for this and the last passed beacon is greater than this
3458 * threshold. Zero value means that the temperature change is ignored for
3459 * beacon filtering; beacons will not be forced to be sent to driver
3460 * regardless of whether its temperature has been changed.
3461 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3462 * calculated for this and the last passed beacon is greater than this
3463 * threshold. Zero value means that the temperature change is ignored for
3464 * beacon filtering; beacons will not be forced to be sent to driver
3465 * regardless of whether its temperature has been changed.
3466 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3467 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3468 * for a specific period of time. Units: Beacons.
3469 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3470 * for a longer period of time then this escape-timeout. Units: Beacons.
3471 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3473 struct iwm_beacon_filter_cmd {
3474 uint32_t bf_energy_delta;
3475 uint32_t bf_roaming_energy_delta;
3476 uint32_t bf_roaming_state;
3477 uint32_t bf_temp_threshold;
3478 uint32_t bf_temp_fast_filter;
3479 uint32_t bf_temp_slow_filter;
3480 uint32_t bf_enable_beacon_filter;
3481 uint32_t bf_debug_flag;
3482 uint32_t bf_escape_timer;
3483 uint32_t ba_escape_timer;
3484 uint32_t ba_enable_beacon_abort;
3487 /* Beacon filtering and beacon abort */
3488 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3489 #define IWM_BF_ENERGY_DELTA_MAX 255
3490 #define IWM_BF_ENERGY_DELTA_MIN 0
3492 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3493 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3494 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3496 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3497 #define IWM_BF_ROAMING_STATE_MAX 255
3498 #define IWM_BF_ROAMING_STATE_MIN 0
3500 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3501 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3502 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3504 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3505 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3506 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3508 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3509 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3510 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3512 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3514 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3516 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3517 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3518 #define IWM_BF_ESCAPE_TIMER_MIN 0
3520 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3521 #define IWM_BA_ESCAPE_TIMER_D3 9
3522 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3523 #define IWM_BA_ESCAPE_TIMER_MIN 0
3525 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3527 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3528 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3529 .bf_roaming_energy_delta = \
3530 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3531 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3532 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3533 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3534 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3535 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3536 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3537 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3540 * END mvm/fw-api-power.h
3544 * BEGIN mvm/fw-api-rs.h
3548 * These serve as indexes into
3549 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3550 * TODO: avoid overlap between legacy and HT rates
3553 IWM_RATE_1M_INDEX = 0,
3554 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3558 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3560 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3561 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3562 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3563 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3566 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3568 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3570 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3572 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3574 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3576 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3577 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3579 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3580 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3581 IWM_RATE_MCS_8_INDEX,
3582 IWM_RATE_MCS_9_INDEX,
3583 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3584 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3585 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3588 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3590 /* fw API values for legacy bit rates, both OFDM and CCK */
3592 IWM_RATE_6M_PLCP = 13,
3593 IWM_RATE_9M_PLCP = 15,
3594 IWM_RATE_12M_PLCP = 5,
3595 IWM_RATE_18M_PLCP = 7,
3596 IWM_RATE_24M_PLCP = 9,
3597 IWM_RATE_36M_PLCP = 11,
3598 IWM_RATE_48M_PLCP = 1,
3599 IWM_RATE_54M_PLCP = 3,
3600 IWM_RATE_1M_PLCP = 10,
3601 IWM_RATE_2M_PLCP = 20,
3602 IWM_RATE_5M_PLCP = 55,
3603 IWM_RATE_11M_PLCP = 110,
3604 IWM_RATE_INVM_PLCP = -1,
3608 * rate_n_flags bit fields
3610 * The 32-bit value has different layouts in the low 8 bites depending on the
3611 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3612 * for CCK and OFDM).
3614 * High-throughput (HT) rate format
3615 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3616 * Very High-throughput (VHT) rate format
3617 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3618 * Legacy OFDM rate format for bits 7:0
3619 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3620 * Legacy CCK rate format for bits 7:0:
3621 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3624 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3625 #define IWM_RATE_MCS_HT_POS 8
3626 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3628 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3629 #define IWM_RATE_MCS_CCK_POS 9
3630 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3632 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3633 #define IWM_RATE_MCS_VHT_POS 26
3634 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3638 * High-throughput (HT) rate format for bits 7:0
3640 * 2-0: MCS rate base
3649 * 4-3: 0) Single stream (SISO)
3650 * 1) Dual stream (MIMO)
3651 * 2) Triple stream (MIMO)
3652 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3653 * (bits 7-6 are zero)
3655 * Together the low 5 bits work out to the MCS index because we don't
3656 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3657 * streams and 16-23 have three streams. We could also support MCS 32
3658 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3660 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3661 #define IWM_RATE_HT_MCS_NSS_POS 3
3662 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3664 /* Bit 10: (1) Use Green Field preamble */
3665 #define IWM_RATE_HT_MCS_GF_POS 10
3666 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3668 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3671 * Very High-throughput (VHT) rate format for bits 7:0
3673 * 3-0: VHT MCS (0-9)
3674 * 5-4: number of streams - 1:
3675 * 0) Single stream (SISO)
3676 * 1) Dual stream (MIMO)
3677 * 2) Triple stream (MIMO)
3680 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3681 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3682 #define IWM_RATE_VHT_MCS_NSS_POS 4
3683 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3686 * Legacy OFDM rate format for bits 7:0
3698 * Legacy CCK rate format for bits 7:0:
3699 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3707 #define IWM_RATE_LEGACY_RATE_MSK 0xff
3711 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3712 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3714 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3715 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3716 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3717 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3718 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3719 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3721 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3722 #define IWM_RATE_MCS_SGI_POS 13
3723 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3725 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3726 #define IWM_RATE_MCS_ANT_POS 14
3727 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3728 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3729 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3730 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3731 IWM_RATE_MCS_ANT_B_MSK)
3732 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3733 IWM_RATE_MCS_ANT_C_MSK)
3734 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3735 #define IWM_RATE_MCS_ANT_NUM 3
3737 /* Bit 17-18: (0) SS, (1) SS*2 */
3738 #define IWM_RATE_MCS_STBC_POS 17
3739 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
3741 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
3742 #define IWM_RATE_MCS_BF_POS 19
3743 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
3745 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
3746 #define IWM_RATE_MCS_ZLF_POS 20
3747 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
3749 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
3750 #define IWM_RATE_MCS_DUP_POS 24
3751 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
3753 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
3754 #define IWM_RATE_MCS_LDPC_POS 27
3755 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
3758 /* Link Quality definitions */
3760 /* # entries in rate scale table to support Tx retries */
3761 #define IWM_LQ_MAX_RETRY_NUM 16
3763 /* Link quality command flags bit fields */
3765 /* Bit 0: (0) Don't use RTS (1) Use RTS */
3766 #define IWM_LQ_FLAG_USE_RTS_POS 0
3767 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
3769 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
3770 #define IWM_LQ_FLAG_COLOR_POS 1
3771 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
3773 /* Bit 4-5: Tx RTS BW Signalling
3774 * (0) No RTS BW signalling
3775 * (1) Static BW signalling
3776 * (2) Dynamic BW signalling
3778 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
3779 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3780 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3781 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
3783 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
3784 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
3786 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
3787 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
3790 * struct iwm_lq_cmd - link quality command
3791 * @sta_id: station to update
3792 * @control: not used
3793 * @flags: combination of IWM_LQ_FLAG_*
3794 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
3796 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
3797 * Should be ANT_[ABC]
3798 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
3799 * @initial_rate_index: first index from rs_table per AC category
3800 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
3801 * value of 100 is one usec. Range is 100 to 8000
3802 * @agg_disable_start_th: try-count threshold for starting aggregation.
3803 * If a frame has higher try-count, it should not be selected for
3804 * starting an aggregation sequence.
3805 * @agg_frame_cnt_limit: max frame count in an aggregation.
3807 * 1: no aggregation (one frame per aggregation)
3808 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
3809 * @rs_table: array of rates for each TX try, each is rate_n_flags,
3810 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
3811 * @bf_params: beam forming params, currently not used
3817 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
3820 uint8_t single_stream_ant_msk;
3821 uint8_t dual_stream_ant_msk;
3822 uint8_t initial_rate_index[IWM_AC_NUM];
3823 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
3824 uint16_t agg_time_limit;
3825 uint8_t agg_disable_start_th;
3826 uint8_t agg_frame_cnt_limit;
3828 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
3830 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
3833 * END mvm/fw-api-rs.h
3837 * BEGIN mvm/fw-api-tx.h
3841 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
3842 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
3843 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
3844 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
3845 * Otherwise, use rate_n_flags from the TX command
3846 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
3847 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
3848 * Must set IWM_TX_CMD_FLG_ACK with this flag.
3849 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
3850 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
3851 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
3852 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
3853 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
3854 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
3855 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
3856 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
3857 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
3858 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
3859 * Should be set for beacons and probe responses
3860 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
3861 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
3862 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
3863 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
3864 * Should be set for 26/30 length MAC headers
3865 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
3866 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
3867 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
3868 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
3869 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
3870 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
3871 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
3872 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
3875 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
3876 IWM_TX_CMD_FLG_ACK = (1 << 3),
3877 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
3878 IWM_TX_CMD_FLG_BA = (1 << 5),
3879 IWM_TX_CMD_FLG_BAR = (1 << 6),
3880 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
3881 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
3882 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
3883 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
3884 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
3885 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
3886 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
3887 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
3888 IWM_TX_CMD_FLG_TSF = (1 << 16),
3889 IWM_TX_CMD_FLG_CALIB = (1 << 17),
3890 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
3891 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
3892 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
3893 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
3894 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
3895 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
3896 IWM_TX_CMD_FLG_DUR = (1 << 25),
3897 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
3898 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
3899 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
3900 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
3901 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
3904 * TX command security control
3906 #define IWM_TX_CMD_SEC_WEP 0x01
3907 #define IWM_TX_CMD_SEC_CCM 0x02
3908 #define IWM_TX_CMD_SEC_TKIP 0x03
3909 #define IWM_TX_CMD_SEC_EXT 0x04
3910 #define IWM_TX_CMD_SEC_MSK 0x07
3911 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
3912 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
3913 #define IWM_TX_CMD_SEC_KEY128 0x08
3915 /* TODO: how does these values are OK with only 16 bit variable??? */
3917 * TX command next frame info
3919 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
3920 * bit 3 - immediate ACK required
3921 * bit 4 - rate is taken from STA table
3922 * bit 5 - frame belongs to BA stream
3923 * bit 6 - immediate BA response expected
3925 * bits 8:15 - Station ID
3928 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
3929 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
3930 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
3931 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
3932 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
3933 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
3934 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
3935 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
3936 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
3939 * TX command Frame life time in us - to be written in pm_frame_timeout
3941 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
3942 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
3943 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
3944 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
3947 * TID for non QoS frames - to be written in tid_tspec
3949 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
3952 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
3954 #define IWM_DEFAULT_TX_RETRY 15
3955 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
3956 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
3957 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
3958 #define IWM_LOW_RETRY_LIMIT 7
3960 /* TODO: complete documentation for try_cnt and btkill_cnt */
3962 * struct iwm_tx_cmd - TX command struct to FW
3963 * ( IWM_TX_CMD = 0x1c )
3964 * @len: in bytes of the payload, see below for details
3965 * @next_frame_len: same as len, but for next frame (0 if not applicable)
3966 * Used for fragmentation and bursting, but not in 11n aggregation.
3967 * @tx_flags: combination of IWM_TX_CMD_FLG_*
3968 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
3969 * cleared. Combination of IWM_RATE_MCS_*
3970 * @sta_id: index of destination station in FW station table
3971 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
3972 * @initial_rate_index: index into the rate table for initial TX attempt.
3973 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
3974 * @key: security key
3975 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
3976 * @life_time: frame life time (usecs??)
3977 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
3978 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
3979 * @dram_msb_ptr: upper bits of the scratch physical address
3980 * @rts_retry_limit: max attempts for RTS
3981 * @data_retry_limit: max attempts to send the data packet
3982 * @tid_spec: TID/tspec
3983 * @pm_frame_timeout: PM TX frame timeout
3984 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
3985 * specified by HCCA protocol
3987 * The byte count (both len and next_frame_len) includes MAC header
3988 * (24/26/30/32 bytes)
3989 * + 2 bytes pad if 26/30 header size
3990 * + 8 byte IV for CCM or TKIP (not used for WEP)
3992 * + 8-byte MIC (not used for CCM/WEP)
3993 * It does not include post-MAC padding, i.e.,
3994 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
3995 * Range of len: 14-2342 bytes.
3997 * After the struct fields the MAC header is placed, plus any padding,
3998 * and then the actial payload.
4002 uint16_t next_frame_len;
4008 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4009 uint32_t rate_n_flags;
4012 uint8_t initial_rate_index;
4015 uint16_t next_frame_flags;
4018 uint32_t dram_lsb_ptr;
4019 uint8_t dram_msb_ptr;
4020 uint8_t rts_retry_limit;
4021 uint8_t data_retry_limit;
4023 uint16_t pm_frame_timeout;
4024 uint16_t driver_txop;
4026 struct ieee80211_frame hdr[0];
4027 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4030 * TX response related data
4034 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4035 * @IWM_TX_STATUS_SUCCESS:
4036 * @IWM_TX_STATUS_DIRECT_DONE:
4037 * @IWM_TX_STATUS_POSTPONE_DELAY:
4038 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4039 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4040 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4041 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4042 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4043 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4044 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4045 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4046 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4047 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4048 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4049 * @IWM_TX_STATUS_FAIL_DEST_PS:
4050 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4051 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4052 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4053 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4054 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4055 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4056 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4057 * @IWM_TX_STATUS_FAIL_FW_DROP:
4058 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4060 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4062 * @IWM_TX_MODE_NO_BURST:
4063 * @IWM_TX_MODE_IN_BURST_SEQ:
4064 * @IWM_TX_MODE_FIRST_IN_BURST:
4065 * @IWM_TX_QUEUE_NUM_MSK:
4067 * Valid only if frame_count =1
4068 * TODO: complete documentation
4070 enum iwm_tx_status {
4071 IWM_TX_STATUS_MSK = 0x000000ff,
4072 IWM_TX_STATUS_SUCCESS = 0x01,
4073 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4075 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4076 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4077 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4078 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4079 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4081 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4082 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4083 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4084 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4085 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4086 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4087 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4088 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4089 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4090 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4091 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4092 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4093 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4094 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4095 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4096 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4097 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4098 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4099 IWM_TX_MODE_MSK = 0x00000f00,
4100 IWM_TX_MODE_NO_BURST = 0x00000000,
4101 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4102 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4103 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4104 IWM_TX_NARROW_BW_MSK = 0x00060000,
4105 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4106 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4107 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4111 * enum iwm_tx_agg_status - TX aggregation status
4112 * @IWM_AGG_TX_STATE_STATUS_MSK:
4113 * @IWM_AGG_TX_STATE_TRANSMITTED:
4114 * @IWM_AGG_TX_STATE_UNDERRUN:
4115 * @IWM_AGG_TX_STATE_BT_PRIO:
4116 * @IWM_AGG_TX_STATE_FEW_BYTES:
4117 * @IWM_AGG_TX_STATE_ABORT:
4118 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4119 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4120 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4121 * @IWM_AGG_TX_STATE_SCD_QUERY:
4122 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4123 * @IWM_AGG_TX_STATE_RESPONSE:
4124 * @IWM_AGG_TX_STATE_DUMP_TX:
4125 * @IWM_AGG_TX_STATE_DELAY_TX:
4126 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4127 * occur if tx failed for this frame when it was a member of a previous
4128 * aggregation block). If rate scaling is used, retry count indicates the
4129 * rate table entry used for all frames in the new agg.
4130 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4133 * TODO: complete documentation
4135 enum iwm_tx_agg_status {
4136 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4137 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4138 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4139 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4140 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4141 IWM_AGG_TX_STATE_ABORT = 0x008,
4142 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4143 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4144 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4145 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4146 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4147 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4148 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4149 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4150 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4151 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4154 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4155 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4156 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4159 * The mask below describes a status where we are absolutely sure that the MPDU
4160 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4161 * written the bytes to the TXE, but we know nothing about what the DSP did.
4163 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4164 IWM_AGG_TX_STATE_ABORT | \
4165 IWM_AGG_TX_STATE_SCD_QUERY)
4168 * IWM_REPLY_TX = 0x1c (response)
4170 * This response may be in one of two slightly different formats, indicated
4171 * by the frame_count field:
4173 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4174 * frame. Multiple attempts, at various bit rates, may have been made for
4177 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4178 * frames that used block-acknowledge. All frames were transmitted at
4179 * same rate. Rate scaling may have been used if first frame in this new
4180 * agg block failed in previous agg block(s).
4182 * Note that, for aggregation, ACK (block-ack) status is not delivered
4183 * here; block-ack has not been received by the time the device records
4185 * This status relates to reasons the tx might have been blocked or aborted
4186 * within the device, rather than whether it was received successfully by
4187 * the destination station.
4191 * struct iwm_agg_tx_status - per packet TX aggregation status
4192 * @status: enum iwm_tx_agg_status
4193 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4195 struct iwm_agg_tx_status {
4201 * definitions for initial rate index field
4202 * bits [3:0] initial rate index
4203 * bits [6:4] rate table color, used for the initial rate
4204 * bit-7 invalid rate indication
4206 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4207 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4208 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4210 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4211 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4214 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4215 * ( IWM_REPLY_TX = 0x1c )
4216 * @frame_count: 1 no aggregation, >1 aggregation
4217 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4218 * @failure_rts: num of failures due to unsuccessful RTS
4219 * @failure_frame: num failures due to no ACK (unused for agg)
4220 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4221 * Tx of all the batch. IWM_RATE_MCS_*
4222 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4223 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4225 * @pa_status: tx power info
4226 * @pa_integ_res_a: tx power info
4227 * @pa_integ_res_b: tx power info
4228 * @pa_integ_res_c: tx power info
4229 * @measurement_req_id: tx power info
4230 * @tfd_info: TFD information set by the FH
4231 * @seq_ctl: sequence control from the Tx cmd
4232 * @byte_cnt: byte count from the Tx cmd
4233 * @tlc_info: TLC rate info
4234 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4235 * @frame_ctrl: frame control
4236 * @status: for non-agg: frame status IWM_TX_STATUS_*
4237 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4238 * follow this one, up to frame_count.
4240 * After the array of statuses comes the SSN of the SCD. Look at
4241 * %iwm_mvm_get_scd_ssn for more details.
4243 struct iwm_mvm_tx_resp {
4244 uint8_t frame_count;
4245 uint8_t bt_kill_count;
4246 uint8_t failure_rts;
4247 uint8_t failure_frame;
4248 uint32_t initial_rate;
4249 uint16_t wireless_media_time;
4252 uint8_t pa_integ_res_a[3];
4253 uint8_t pa_integ_res_b[3];
4254 uint8_t pa_integ_res_c[3];
4255 uint16_t measurement_req_id;
4263 uint16_t frame_ctrl;
4265 struct iwm_agg_tx_status status;
4266 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4269 * struct iwm_mvm_ba_notif - notifies about reception of BA
4270 * ( IWM_BA_NOTIF = 0xc5 )
4271 * @sta_addr_lo32: lower 32 bits of the MAC address
4272 * @sta_addr_hi16: upper 16 bits of the MAC address
4273 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4274 * @tid: tid of the session
4276 * @bitmap: the bitmap of the BA notification as seen in the air
4277 * @scd_flow: the tx queue this BA relates to
4278 * @scd_ssn: the index of the last contiguously sent packet
4279 * @txed: number of Txed frames in this batch
4280 * @txed_2_done: number of Acked frames in this batch
4282 struct iwm_mvm_ba_notif {
4283 uint32_t sta_addr_lo32;
4284 uint16_t sta_addr_hi16;
4294 uint8_t txed_2_done;
4299 * struct iwm_mac_beacon_cmd - beacon template command
4300 * @tx: the tx commands associated with the beacon frame
4301 * @template_id: currently equal to the mac context id of the coresponding
4303 * @tim_idx: the offset of the tim IE in the beacon
4304 * @tim_size: the length of the tim IE
4305 * @frame: the template of the beacon frame
4307 struct iwm_mac_beacon_cmd {
4308 struct iwm_tx_cmd tx;
4309 uint32_t template_id;
4312 struct ieee80211_frame frame[0];
4315 struct iwm_beacon_notif {
4316 struct iwm_mvm_tx_resp beacon_notify_hdr;
4318 uint32_t ibss_mgr_status;
4322 * enum iwm_dump_control - dump (flush) control flags
4323 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4324 * and the TFD queues are empty.
4326 enum iwm_dump_control {
4327 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4331 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4332 * @queues_ctl: bitmap of queues to flush
4333 * @flush_ctl: control flags
4334 * @reserved: reserved
4336 struct iwm_tx_path_flush_cmd {
4337 uint32_t queues_ctl;
4340 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4343 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4344 * @tx_resp: the Tx response from the fw (agg or non-agg)
4346 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4347 * it can't know that everything will go well until the end of the AMPDU, it
4348 * can't know in advance the number of MPDUs that will be sent in the current
4349 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4350 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4351 * of the batch. This is why the SSN of the SCD is written at the end of the
4352 * whole struct at a variable offset. This function knows how to cope with the
4353 * variable offset and returns the SSN of the SCD.
4355 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4357 return le32_to_cpup((uint32_t *)&tx_resp->status +
4358 tx_resp->frame_count) & 0xfff;
4362 * END mvm/fw-api-tx.h
4366 * BEGIN mvm/fw-api-scan.h
4369 /* Scan Commands, Responses, Notifications */
4371 /* Masks for iwm_scan_channel.type flags */
4372 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4373 #define IWM_SCAN_CHANNEL_NARROW_BAND (1 << 22)
4375 /* Max number of IEs for direct SSID scans in a command */
4376 #define IWM_PROBE_OPTION_MAX 20
4379 * struct iwm_scan_channel - entry in IWM_REPLY_SCAN_CMD channel table
4380 * @channel: band is selected by iwm_scan_cmd "flags" field
4381 * @tx_gain: gain for analog radio
4382 * @dsp_atten: gain for DSP
4383 * @active_dwell: dwell time for active scan in TU, typically 5-50
4384 * @passive_dwell: dwell time for passive scan in TU, typically 20-500
4385 * @type: type is broken down to these bits:
4386 * bit 0: 0 = passive, 1 = active
4387 * bits 1-20: SSID direct bit map. If any of these bits is set then
4388 * the corresponding SSID IE is transmitted in probe request
4389 * (bit i adds IE in position i to the probe request)
4390 * bit 22: channel width, 0 = regular, 1 = TGj narrow channel
4393 * @iteration_interval:
4394 * This struct is used once for each channel in the scan list.
4395 * Each channel can independently select:
4396 * 1) SSID for directed active scans
4397 * 2) Txpower setting (for rate specified within Tx command)
4398 * 3) How long to stay on-channel (behavior may be modified by quiet_time,
4399 * quiet_plcp_th, good_CRC_th)
4401 * To avoid uCode errors, make sure the following are true (see comments
4402 * under struct iwm_scan_cmd about max_out_time and quiet_time):
4403 * 1) If using passive_dwell (i.e. passive_dwell != 0):
4404 * active_dwell <= passive_dwell (< max_out_time if max_out_time != 0)
4405 * 2) quiet_time <= active_dwell
4406 * 3) If restricting off-channel time (i.e. max_out_time !=0):
4407 * passive_dwell < max_out_time
4408 * active_dwell < max_out_time
4410 struct iwm_scan_channel {
4413 uint16_t iteration_count;
4414 uint32_t iteration_interval;
4415 uint16_t active_dwell;
4416 uint16_t passive_dwell;
4417 } __packed; /* IWM_SCAN_CHANNEL_CONTROL_API_S_VER_1 */
4420 * struct iwm_ssid_ie - directed scan network information element
4422 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4423 * selected by "type" bit field in struct iwm_scan_channel;
4424 * each channel may select different ssids from among the 20 entries.
4425 * SSID IEs get transmitted in reverse order of entry.
4427 struct iwm_ssid_ie {
4430 uint8_t ssid[IEEE80211_NWID_LEN];
4431 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4434 * iwm_scan_flags - masks for scan command flags
4435 *@IWM_SCAN_FLAGS_PERIODIC_SCAN:
4436 *@IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX:
4437 *@IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND:
4438 *@IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND:
4439 *@IWM_SCAN_FLAGS_FRAGMENTED_SCAN:
4440 *@IWM_SCAN_FLAGS_PASSIVE2ACTIVE: use active scan on channels that was active
4441 * in the past hour, even if they are marked as passive.
4443 enum iwm_scan_flags {
4444 IWM_SCAN_FLAGS_PERIODIC_SCAN = (1 << 0),
4445 IWM_SCAN_FLAGS_P2P_PUBLIC_ACTION_FRAME_TX = (1 << 1),
4446 IWM_SCAN_FLAGS_DELAYED_SCAN_LOWBAND = (1 << 2),
4447 IWM_SCAN_FLAGS_DELAYED_SCAN_HIGHBAND = (1 << 3),
4448 IWM_SCAN_FLAGS_FRAGMENTED_SCAN = (1 << 4),
4449 IWM_SCAN_FLAGS_PASSIVE2ACTIVE = (1 << 5),
4453 * enum iwm_scan_type - Scan types for scan command
4454 * @IWM_SCAN_TYPE_FORCED:
4455 * @IWM_SCAN_TYPE_BACKGROUND:
4456 * @IWM_SCAN_TYPE_OS:
4457 * @IWM_SCAN_TYPE_ROAMING:
4458 * @IWM_SCAN_TYPE_ACTION:
4459 * @IWM_SCAN_TYPE_DISCOVERY:
4460 * @IWM_SCAN_TYPE_DISCOVERY_FORCED:
4462 enum iwm_scan_type {
4463 IWM_SCAN_TYPE_FORCED = 0,
4464 IWM_SCAN_TYPE_BACKGROUND = 1,
4465 IWM_SCAN_TYPE_OS = 2,
4466 IWM_SCAN_TYPE_ROAMING = 3,
4467 IWM_SCAN_TYPE_ACTION = 4,
4468 IWM_SCAN_TYPE_DISCOVERY = 5,
4469 IWM_SCAN_TYPE_DISCOVERY_FORCED = 6,
4470 }; /* IWM_SCAN_ACTIVITY_TYPE_E_VER_1 */
4472 /* Maximal number of channels to scan */
4473 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24
4476 * struct iwm_scan_cmd - scan request command
4477 * ( IWM_SCAN_REQUEST_CMD = 0x80 )
4478 * @len: command length in bytes
4479 * @scan_flags: scan flags from IWM_SCAN_FLAGS_*
4480 * @channel_count: num of channels in channel list (1 - IWM_MAX_NUM_SCAN_CHANNELS)
4481 * @quiet_time: in msecs, dwell this time for active scan on quiet channels
4482 * @quiet_plcp_th: quiet PLCP threshold (channel is quiet if less than
4483 * this number of packets were received (typically 1)
4484 * @passive2active: is auto switching from passive to active during scan allowed
4485 * @rxchain_sel_flags: RXON_RX_CHAIN_*
4486 * @max_out_time: in usecs, max out of serving channel time
4487 * @suspend_time: how long to pause scan when returning to service channel:
4488 * bits 0-19: beacon interval in usecs (suspend before executing)
4489 * bits 20-23: reserved
4490 * bits 24-31: number of beacons (suspend between channels)
4491 * @rxon_flags: RXON_FLG_*
4492 * @filter_flags: RXON_FILTER_*
4493 * @tx_cmd: for active scans (zero for passive), w/o payload,
4494 * no RS so specify TX rate
4495 * @direct_scan: direct scan SSIDs
4496 * @type: one of IWM_SCAN_TYPE_*
4497 * @repeats: how many time to repeat the scan
4499 struct iwm_scan_cmd {
4502 uint8_t channel_count;
4503 uint16_t quiet_time;
4504 uint16_t quiet_plcp_th;
4505 uint16_t passive2active;
4506 uint16_t rxchain_sel_flags;
4507 uint32_t max_out_time;
4508 uint32_t suspend_time;
4509 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4510 uint32_t rxon_flags;
4511 uint32_t filter_flags;
4512 struct iwm_tx_cmd tx_cmd;
4513 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4518 * Probe request frame, followed by channel list.
4520 * Size of probe request frame is specified by byte count in tx_cmd.
4521 * Channel list follows immediately after probe request frame.
4522 * Number of channels in list is specified by channel_count.
4523 * Each channel in list is of type:
4525 * struct iwm_scan_channel channels[0];
4527 * NOTE: Only one band of channels can be scanned per pass. You
4528 * must not mix 2.4GHz channels and 5.2GHz channels, and you must wait
4529 * for one scan to complete (i.e. receive IWM_SCAN_COMPLETE_NOTIFICATION)
4530 * before requesting another scan.
4533 } __packed; /* IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_5 */
4535 /* Response to scan request contains only status with one of these values */
4536 #define IWM_SCAN_RESPONSE_OK 0x1
4537 #define IWM_SCAN_RESPONSE_ERROR 0x2
4540 * IWM_SCAN_ABORT_CMD = 0x81
4541 * When scan abort is requested, the command has no fields except the common
4542 * header. The response contains only a status with one of these values.
4544 #define IWM_SCAN_ABORT_POSSIBLE 0x1
4545 #define IWM_SCAN_ABORT_IGNORED 0x2 /* no pending scans */
4547 /* TODO: complete documentation */
4548 #define IWM_SCAN_OWNER_STATUS 0x1
4549 #define IWM_MEASURE_OWNER_STATUS 0x2
4552 * struct iwm_scan_start_notif - notifies start of scan in the device
4553 * ( IWM_SCAN_START_NOTIFICATION = 0x82 )
4554 * @tsf_low: TSF timer (lower half) in usecs
4555 * @tsf_high: TSF timer (higher half) in usecs
4556 * @beacon_timer: structured as follows:
4557 * bits 0:19 - beacon interval in usecs
4558 * bits 20:23 - reserved (0)
4559 * bits 24:31 - number of beacons
4560 * @channel: which channel is scanned
4561 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4562 * @status: one of *_OWNER_STATUS
4564 struct iwm_scan_start_notif {
4567 uint32_t beacon_timer;
4570 uint8_t reserved[2];
4572 } __packed; /* IWM_SCAN_START_NTF_API_S_VER_1 */
4574 /* scan results probe_status first bit indicates success */
4575 #define IWM_SCAN_PROBE_STATUS_OK 0
4576 #define IWM_SCAN_PROBE_STATUS_TX_FAILED (1 << 0)
4577 /* error statuses combined with TX_FAILED */
4578 #define IWM_SCAN_PROBE_STATUS_FAIL_TTL (1 << 1)
4579 #define IWM_SCAN_PROBE_STATUS_FAIL_BT (1 << 2)
4581 /* How many statistics are gathered for each channel */
4582 #define IWM_SCAN_RESULTS_STATISTICS 1
4585 * enum iwm_scan_complete_status - status codes for scan complete notifications
4586 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4587 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4588 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4589 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4590 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4591 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4592 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4593 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4594 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4595 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4597 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4599 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4601 enum iwm_scan_complete_status {
4602 IWM_SCAN_COMP_STATUS_OK = 0x1,
4603 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4604 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4605 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4606 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4607 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4608 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4609 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4610 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4611 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4612 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4613 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4617 * struct iwm_scan_results_notif - scan results for one channel
4618 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4619 * @channel: which channel the results are from
4620 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4621 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4622 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4623 * @duration: duration spent in channel, in usecs
4624 * @statistics: statistics gathered for this channel
4626 struct iwm_scan_results_notif {
4629 uint8_t probe_status;
4630 uint8_t num_probe_not_sent;
4632 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4633 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4636 * struct iwm_scan_complete_notif - notifies end of scanning (all channels)
4637 * ( IWM_SCAN_COMPLETE_NOTIFICATION = 0x84 )
4638 * @scanned_channels: number of channels scanned (and number of valid results)
4639 * @status: one of IWM_SCAN_COMP_STATUS_*
4640 * @bt_status: BT on/off status
4641 * @last_channel: last channel that was scanned
4642 * @tsf_low: TSF timer (lower half) in usecs
4643 * @tsf_high: TSF timer (higher half) in usecs
4644 * @results: all scan results, only "scanned_channels" of them are valid
4646 struct iwm_scan_complete_notif {
4647 uint8_t scanned_channels;
4650 uint8_t last_channel;
4653 struct iwm_scan_results_notif results[IWM_MAX_NUM_SCAN_CHANNELS];
4654 } __packed; /* IWM_SCAN_COMPLETE_NTF_API_S_VER_2 */
4657 #define IWM_MAX_SCAN_CHANNELS 40
4658 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4659 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4660 #define IWM_SCAN_MAX_PROFILES 11
4661 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4663 /* Default watchdog (in MS) for scheduled scan iteration */
4664 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4666 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4667 #define IWM_CAN_ABORT_STATUS 1
4669 #define IWM_FULL_SCAN_MULTIPLIER 5
4670 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4672 enum iwm_scan_framework_client {
4673 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4674 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4675 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4679 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6
4680 * @scan_flags: see enum iwm_scan_flags
4681 * @channel_count: channels in channel list
4682 * @quiet_time: dwell time, in milisiconds, on quiet channel
4683 * @quiet_plcp_th: quiet channel num of packets threshold
4684 * @good_CRC_th: passive to active promotion threshold
4685 * @rx_chain: RXON rx chain.
4686 * @max_out_time: max uSec to be out of assoceated channel
4687 * @suspend_time: pause scan this long when returning to service channel
4688 * @flags: RXON flags
4689 * @filter_flags: RXONfilter
4690 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz.
4691 * @direct_scan: list of SSIDs for directed active scan
4692 * @scan_type: see enum iwm_scan_type.
4693 * @rep_count: repetition count for each scheduled scan iteration.
4695 struct iwm_scan_offload_cmd {
4698 uint8_t channel_count;
4699 uint16_t quiet_time;
4700 uint16_t quiet_plcp_th;
4701 uint16_t good_CRC_th;
4703 uint32_t max_out_time;
4704 uint32_t suspend_time;
4705 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4707 uint32_t filter_flags;
4708 struct iwm_tx_cmd tx_cmd[2];
4709 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4710 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4715 enum iwm_scan_offload_channel_flags {
4716 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0),
4717 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22),
4718 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24),
4719 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25),
4723 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S
4724 * @type: bitmap - see enum iwm_scan_offload_channel_flags.
4725 * 0: passive (0) or active (1) scan.
4726 * 1-20: directed scan to i'th ssid.
4727 * 22: channel width configuation - 1 for narrow.
4730 * @channel_number: channel number 1-13 etc.
4731 * @iter_count: repetition count for the channel.
4732 * @iter_interval: interval between two innteration on one channel.
4733 * @dwell_time: entry 0 - active scan, entry 1 - passive scan.
4735 struct iwm_scan_channel_cfg {
4736 uint32_t type[IWM_MAX_SCAN_CHANNELS];
4737 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS];
4738 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS];
4739 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS];
4740 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2];
4744 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S
4745 * @scan_cmd: scan command fixed part
4746 * @channel_cfg: scan channel configuration
4747 * @data: probe request frames (one per band)
4749 struct iwm_scan_offload_cfg {
4750 struct iwm_scan_offload_cmd scan_cmd;
4751 struct iwm_scan_channel_cfg channel_cfg;
4756 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4757 * @ssid: MAC address to filter out
4758 * @reported_rssi: AP rssi reported to the host
4759 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4761 struct iwm_scan_offload_blacklist {
4762 uint8_t ssid[IEEE80211_ADDR_LEN];
4763 uint8_t reported_rssi;
4764 uint8_t client_bitmap;
4767 enum iwm_scan_offload_network_type {
4768 IWM_NETWORK_TYPE_BSS = 1,
4769 IWM_NETWORK_TYPE_IBSS = 2,
4770 IWM_NETWORK_TYPE_ANY = 3,
4773 enum iwm_scan_offload_band_selection {
4774 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4775 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4776 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4780 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4781 * @ssid_index: index to ssid list in fixed part
4782 * @unicast_cipher: encryption olgorithm to match - bitmap
4783 * @aut_alg: authentication olgorithm to match - bitmap
4784 * @network_type: enum iwm_scan_offload_network_type
4785 * @band_selection: enum iwm_scan_offload_band_selection
4786 * @client_bitmap: clients waiting for match - enum scan_framework_client
4788 struct iwm_scan_offload_profile {
4790 uint8_t unicast_cipher;
4792 uint8_t network_type;
4793 uint8_t band_selection;
4794 uint8_t client_bitmap;
4795 uint8_t reserved[2];
4799 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4800 * @blaclist: AP list to filter off from scan results
4801 * @profiles: profiles to search for match
4802 * @blacklist_len: length of blacklist
4803 * @num_profiles: num of profiles in the list
4804 * @match_notify: clients waiting for match found notification
4805 * @pass_match: clients waiting for the results
4806 * @active_clients: active clients bitmap - enum scan_framework_client
4807 * @any_beacon_notify: clients waiting for match notification without match
4809 struct iwm_scan_offload_profile_cfg {
4810 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4811 uint8_t blacklist_len;
4812 uint8_t num_profiles;
4813 uint8_t match_notify;
4815 uint8_t active_clients;
4816 uint8_t any_beacon_notify;
4817 uint8_t reserved[2];
4821 * iwm_scan_offload_schedule - schedule of scan offload
4822 * @delay: delay between iterations, in seconds.
4823 * @iterations: num of scan iterations
4824 * @full_scan_mul: number of partial scans before each full scan
4826 struct iwm_scan_offload_schedule {
4829 uint8_t full_scan_mul;
4833 * iwm_scan_offload_flags
4835 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
4836 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
4837 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
4840 enum iwm_scan_offload_flags {
4841 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0),
4842 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2),
4843 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3),
4847 * iwm_scan_offload_req - scan offload request command
4848 * @flags: bitmap - enum iwm_scan_offload_flags.
4849 * @watchdog: maximum scan duration in TU.
4850 * @delay: delay in seconds before first iteration.
4851 * @schedule_line: scan offload schedule, for fast and regular scan.
4853 struct iwm_scan_offload_req {
4858 struct iwm_scan_offload_schedule schedule_line[2];
4861 enum iwm_scan_offload_compleate_status {
4862 IWM_SCAN_OFFLOAD_COMPLETED = 1,
4863 IWM_SCAN_OFFLOAD_ABORTED = 2,
4867 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1
4868 * @last_schedule_line: last schedule line executed (fast or regular)
4869 * @last_schedule_iteration: last scan iteration executed before scan abort
4870 * @status: enum iwm_scan_offload_compleate_status
4872 struct iwm_scan_offload_complete {
4873 uint8_t last_schedule_line;
4874 uint8_t last_schedule_iteration;
4880 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1
4881 * @ssid_bitmap: SSIDs indexes found in this iteration
4882 * @client_bitmap: clients that are active and wait for this notification
4884 struct iwm_sched_scan_results {
4885 uint16_t ssid_bitmap;
4886 uint8_t client_bitmap;
4891 * END mvm/fw-api-scan.h
4895 * BEGIN mvm/fw-api-sta.h
4899 * enum iwm_sta_flags - flags for the ADD_STA host command
4900 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
4901 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
4902 * @IWM_STA_FLG_FLG_ANT_MSK: Antenna selection
4903 * @IWM_STA_FLG_PS: set if STA is in Power Save
4904 * @IWM_STA_FLG_INVALID: set if STA is invalid
4905 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
4906 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
4907 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
4908 * @IWM_STA_FLG_PAN: STA is for PAN interface
4909 * @IWM_STA_FLG_CLASS_AUTH:
4910 * @IWM_STA_FLG_CLASS_ASSOC:
4911 * @IWM_STA_FLG_CLASS_MIMO_PROT:
4912 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
4913 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
4914 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
4915 * initialised by driver and can be updated by fw upon reception of
4916 * action frames that can change the channel width. When cleared the fw
4917 * will send all the frames in 20MHz even when FAT channel is requested.
4918 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
4919 * driver and can be updated by fw upon reception of action frames.
4920 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
4922 enum iwm_sta_flags {
4923 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
4924 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
4926 IWM_STA_FLG_FLG_ANT_A = (1 << 4),
4927 IWM_STA_FLG_FLG_ANT_B = (2 << 4),
4928 IWM_STA_FLG_FLG_ANT_MSK = (IWM_STA_FLG_FLG_ANT_A |
4929 IWM_STA_FLG_FLG_ANT_B),
4931 IWM_STA_FLG_PS = (1 << 8),
4932 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
4933 IWM_STA_FLG_PAN = (1 << 13),
4934 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
4935 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
4936 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
4938 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
4939 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4940 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4941 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4942 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4943 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4944 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4945 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4946 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4947 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
4949 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
4950 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4951 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4952 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4953 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4954 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
4956 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
4957 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
4958 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
4959 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
4960 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
4962 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
4963 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
4964 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
4965 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
4969 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
4970 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
4971 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
4972 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
4973 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
4974 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
4975 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
4976 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
4977 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
4978 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
4979 * station info array (1 - n 1X mode)
4980 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
4981 * @IWM_STA_KEY_NOT_VALID: key is invalid
4982 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
4983 * @IWM_STA_KEY_MULTICAST: set for multical key
4984 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
4986 enum iwm_sta_key_flag {
4987 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
4988 IWM_STA_KEY_FLG_WEP = (1 << 0),
4989 IWM_STA_KEY_FLG_CCM = (2 << 0),
4990 IWM_STA_KEY_FLG_TKIP = (3 << 0),
4991 IWM_STA_KEY_FLG_EXT = (4 << 0),
4992 IWM_STA_KEY_FLG_CMAC = (6 << 0),
4993 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
4994 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
4996 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
4997 IWM_STA_KEY_FLG_KEYID_POS = 8,
4998 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
4999 IWM_STA_KEY_NOT_VALID = (1 << 11),
5000 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5001 IWM_STA_KEY_MULTICAST = (1 << 14),
5002 IWM_STA_KEY_MFP = (1 << 15),
5006 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5007 * @IWM_STA_MODIFY_KEY: this command modifies %key
5008 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5009 * @IWM_STA_MODIFY_TX_RATE: unused
5010 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5011 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5012 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5013 * @IWM_STA_MODIFY_PROT_TH:
5014 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5016 enum iwm_sta_modify_flag {
5017 IWM_STA_MODIFY_KEY = (1 << 0),
5018 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5019 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5020 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5021 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5022 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5023 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5024 IWM_STA_MODIFY_QUEUES = (1 << 7),
5027 #define IWM_STA_MODE_MODIFY 1
5030 * enum iwm_sta_sleep_flag - type of sleep of the station
5031 * @IWM_STA_SLEEP_STATE_AWAKE:
5032 * @IWM_STA_SLEEP_STATE_PS_POLL:
5033 * @IWM_STA_SLEEP_STATE_UAPSD:
5035 enum iwm_sta_sleep_flag {
5036 IWM_STA_SLEEP_STATE_AWAKE = 0,
5037 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5038 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5041 /* STA ID and color bits definitions */
5042 #define IWM_STA_ID_SEED (0x0f)
5043 #define IWM_STA_ID_POS (0)
5044 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5046 #define IWM_STA_COLOR_SEED (0x7)
5047 #define IWM_STA_COLOR_POS (4)
5048 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5050 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5051 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5052 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5053 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5055 #define IWM_STA_KEY_MAX_NUM (16)
5056 #define IWM_STA_KEY_IDX_INVALID (0xff)
5057 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5058 #define IWM_MAX_GLOBAL_KEYS (4)
5059 #define IWM_STA_KEY_LEN_WEP40 (5)
5060 #define IWM_STA_KEY_LEN_WEP104 (13)
5063 * struct iwm_mvm_keyinfo - key information
5064 * @key_flags: type %iwm_sta_key_flag
5065 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5066 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5067 * @key_offset: key offset in the fw's key table
5068 * @key: 16-byte unicast decryption key
5069 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5070 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5071 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5073 struct iwm_mvm_keyinfo {
5075 uint8_t tkip_rx_tsc_byte2;
5077 uint16_t tkip_rx_ttak[5];
5081 uint64_t tx_secur_seq_cnt;
5082 uint64_t hw_tkip_mic_rx_key;
5083 uint64_t hw_tkip_mic_tx_key;
5087 * struct iwm_mvm_add_sta_cmd_v5 - Add/modify a station in the fw's sta table.
5088 * ( IWM_REPLY_ADD_STA = 0x18 )
5089 * @add_modify: 1: modify existing, 0: add new station
5090 * @unicast_tx_key_id: unicast tx key id. Relevant only when unicast key sent
5091 * @multicast_tx_key_id: multicast tx key id. Relevant only when multicast key
5093 * @mac_id_n_color: the Mac context this station belongs to
5094 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5095 * @sta_id: index of station in uCode's station table
5096 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5097 * alone. 1 - modify, 0 - don't change.
5098 * @key: look at %iwm_mvm_keyinfo
5099 * @station_flags: look at %iwm_sta_flags
5100 * @station_flags_msk: what of %station_flags have changed
5101 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5102 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5103 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5104 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5105 * add_immediate_ba_ssn.
5106 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5107 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5108 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5109 * add_immediate_ba_tid.
5110 * @sleep_tx_count: number of packets to transmit to station even though it is
5111 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5112 * keeps track of STA sleep state.
5113 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5114 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5116 * @beamform_flags: beam forming controls
5117 * @tfd_queue_msk: tfd queues used by this station
5119 * The device contains an internal table of per-station information, with info
5120 * on security keys, aggregation parameters, and Tx rates for initial Tx
5121 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5123 * ADD_STA sets up the table entry for one station, either creating a new
5124 * entry, or modifying a pre-existing one.
5126 struct iwm_mvm_add_sta_cmd_v5 {
5128 uint8_t unicast_tx_key_id;
5129 uint8_t multicast_tx_key_id;
5131 uint32_t mac_id_n_color;
5132 uint8_t addr[IEEE80211_ADDR_LEN];
5135 uint8_t modify_mask;
5137 struct iwm_mvm_keyinfo key;
5138 uint32_t station_flags;
5139 uint32_t station_flags_msk;
5140 uint16_t tid_disable_tx;
5142 uint8_t add_immediate_ba_tid;
5143 uint8_t remove_immediate_ba_tid;
5144 uint16_t add_immediate_ba_ssn;
5145 uint16_t sleep_tx_count;
5146 uint16_t sleep_state_flags;
5148 uint16_t beamform_flags;
5149 uint32_t tfd_queue_msk;
5150 } __packed; /* IWM_ADD_STA_CMD_API_S_VER_5 */
5153 * struct iwm_mvm_add_sta_cmd_v6 - Add / modify a station
5154 * VER_6 of this command is quite similar to VER_5 except
5155 * exclusion of all fields related to the security key installation.
5157 struct iwm_mvm_add_sta_cmd_v6 {
5160 uint16_t tid_disable_tx;
5161 uint32_t mac_id_n_color;
5162 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5165 uint8_t modify_mask;
5167 uint32_t station_flags;
5168 uint32_t station_flags_msk;
5169 uint8_t add_immediate_ba_tid;
5170 uint8_t remove_immediate_ba_tid;
5171 uint16_t add_immediate_ba_ssn;
5172 uint16_t sleep_tx_count;
5173 uint16_t sleep_state_flags;
5175 uint16_t beamform_flags;
5176 uint32_t tfd_queue_msk;
5177 } __packed; /* IWM_ADD_STA_CMD_API_S_VER_6 */
5180 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5181 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5182 * @sta_id: index of station in uCode's station table
5183 * @key_offset: key offset in key storage
5184 * @key_flags: type %iwm_sta_key_flag
5185 * @key: key material data
5186 * @key2: key material data
5187 * @rx_secur_seq_cnt: RX security sequence counter for the key
5188 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5189 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5191 struct iwm_mvm_add_sta_key_cmd {
5197 uint8_t rx_secur_seq_cnt[16];
5198 uint8_t tkip_rx_tsc_byte2;
5200 uint16_t tkip_rx_ttak[5];
5201 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5204 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5205 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5206 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5207 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5208 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5209 * that doesn't exist.
5211 enum iwm_mvm_add_sta_rsp_status {
5212 IWM_ADD_STA_SUCCESS = 0x1,
5213 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5214 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5215 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5219 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5220 * ( IWM_REMOVE_STA = 0x19 )
5221 * @sta_id: the station id of the station to be removed
5223 struct iwm_mvm_rm_sta_cmd {
5225 uint8_t reserved[3];
5226 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5229 * struct iwm_mvm_mgmt_mcast_key_cmd
5230 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5231 * @ctrl_flags: %iwm_sta_key_flag
5233 * @K1: IGTK master key
5235 * @sta_id: station ID that support IGTK
5237 * @receive_seq_cnt: initial RSC/PN needed for replay check
5239 struct iwm_mvm_mgmt_mcast_key_cmd {
5240 uint32_t ctrl_flags;
5246 uint64_t receive_seq_cnt;
5247 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5249 struct iwm_mvm_wep_key {
5254 uint8_t reserved2[3];
5258 struct iwm_mvm_wep_key_cmd {
5259 uint32_t mac_id_n_color;
5261 uint8_t decryption_type;
5264 struct iwm_mvm_wep_key wep_key[0];
5265 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5269 * END mvm/fw-api-sta.h
5273 * Some cherry-picked definitions
5276 #define IWM_FRAME_LIMIT 64
5278 struct iwm_cmd_header {
5285 enum iwm_power_scheme {
5286 IWM_POWER_SCHEME_CAM = 1,
5287 IWM_POWER_SCHEME_BPS,
5291 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
5292 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
5293 #define IWM_CMD_FAILED_MSK 0x40
5295 struct iwm_device_cmd {
5296 struct iwm_cmd_header hdr;
5298 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5301 struct iwm_rx_packet {
5303 * The first 4 bytes of the RX frame header contain both the RX frame
5304 * size and some flags.
5306 * 31: flag flush RB request
5307 * 30: flag ignore TC (terminal counter) request
5308 * 29: flag fast IRQ request
5310 * 13-00: RX frame size
5312 uint32_t len_n_flags;
5313 struct iwm_cmd_header hdr;
5317 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5319 static inline uint32_t
5320 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5323 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
5326 static inline uint32_t
5327 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
5330 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
5334 #define IWM_MIN_DBM -100
5335 #define IWM_MAX_DBM -33 /* realistic guess */
5337 #define IWM_READ(sc, reg) \
5338 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
5340 #define IWM_WRITE(sc, reg, val) \
5341 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5343 #define IWM_WRITE_1(sc, reg, val) \
5344 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
5346 #define IWM_SETBITS(sc, reg, mask) \
5347 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
5349 #define IWM_CLRBITS(sc, reg, mask) \
5350 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
5352 #define IWM_BARRIER_WRITE(sc) \
5353 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5354 BUS_SPACE_BARRIER_WRITE)
5356 #define IWM_BARRIER_READ_WRITE(sc) \
5357 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
5358 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
5360 #define IWM_FW_VALID_TX_ANT(sc) \
5361 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_TX_CHAIN) \
5362 >> IWM_FW_PHY_CFG_TX_CHAIN_POS)
5363 #define IWM_FW_VALID_RX_ANT(sc) \
5364 ((sc->sc_fw_phy_config & IWM_FW_PHY_CFG_RX_CHAIN) \
5365 >> IWM_FW_PHY_CFG_RX_CHAIN_POS)
5367 #endif /* __IF_IWM_REG_H__ */