1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
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18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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28 * in the file called COPYING.
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
77 * CSR (control and status registers)
79 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * whenever platform supplies power to device, even when device is in
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
84 * Use iwl_write32() and iwl_read32() family to access these registers;
85 * these provide simple PCI bus access, without waking up the MAC.
86 * Do not use iwl_write_direct32() family for these registers;
87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
91 * NOTE: Device does need to be awake in order to read this memory
92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101 #define IWM_CSR_GP_CNTRL (0x024)
103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
104 #define IWM_CSR_INT_PERIODIC_REG (0x005)
107 * Hardware revision info
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
114 #define IWM_CSR_HW_REV (0x028)
117 * EEPROM and OTP (one-time-programmable) memory reads
119 * NOTE: Device must be awake, initialized via apm_ops.init(),
122 #define IWM_CSR_EEPROM_REG (0x02c)
123 #define IWM_CSR_EEPROM_GP (0x030)
124 #define IWM_CSR_OTP_GP_REG (0x034)
126 #define IWM_CSR_GIO_REG (0x03C)
127 #define IWM_CSR_GP_UCODE_REG (0x048)
128 #define IWM_CSR_GP_DRIVER_REG (0x050)
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
132 * SET/CLR registers set/clear bit(s) if "1" is written.
134 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
139 #define IWM_CSR_MBOX_SET_REG (0x088)
140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
142 #define IWM_CSR_LED_REG (0x094)
143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
147 /* GIO Chicken Bits (PCI Express bus link power management) */
148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
150 /* Analog phase-lock-loop configuration */
151 #define IWM_CSR_ANA_PLL_CFG (0x20c)
154 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
156 * See also IWM_CSR_HW_REV register.
158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
159 * 1-0: "Dash" (-) value, as in C-1, etc.
161 #define IWM_CSR_HW_REV_WA_REG (0x22C)
163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
195 * acknowledged (reset) by host writing "1" to flagged bits. */
196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
209 IWM_CSR_INT_BIT_HW_ERR | \
210 IWM_CSR_INT_BIT_FH_TX | \
211 IWM_CSR_INT_BIT_SW_ERR | \
212 IWM_CSR_INT_BIT_RF_KILL | \
213 IWM_CSR_INT_BIT_SW_RX | \
214 IWM_CSR_INT_BIT_WAKEUP | \
215 IWM_CSR_INT_BIT_ALIVE | \
216 IWM_CSR_INT_BIT_RX_PERIODIC)
218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
228 IWM_CSR_FH_INT_BIT_RX_CHNL0)
230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
231 IWM_CSR_FH_INT_BIT_TX_CHNL0)
234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
247 * GP (general purpose) CONTROL REGISTER
250 * Indicates state of (platform's) hardware RF-Kill switch
251 * 26-24: POWER_SAVE_TYPE
252 * Indicates current power-saving mode:
253 * 000 -- No power saving
254 * 001 -- MAC power-down
255 * 010 -- PHY (radio) power-down
258 * Indicates current system configuration, reflecting pins on chip
259 * as forced high/low by device circuit board.
261 * Indicates MAC is entering a power-saving sleep power-down.
262 * Not a good time to access device-internal resources.
264 * Host sets this to request and maintain MAC wakeup, to allow host
265 * access to device-internal resources. Host must wait for
266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
269 * Host sets this to put device into fully operational D0 power mode.
270 * Host resets this after SW_RESET to put device into low power mode.
272 * Indicates MAC (ucode processor, etc.) is powered up and can run.
273 * Internal resources are accessible.
274 * NOTE: This does not indicate that the processor is actually running.
275 * NOTE: This does not indicate that device has completed
276 * init or post-power-down restore of internal SRAM memory.
277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
278 * SRAM is restored and uCode is in normal operation mode.
279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
280 * do not need to save/restore it.
281 * NOTE: After device reset, this bit remains "0" until host sets
284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
304 IWM_SILICON_A_STEP = 0,
310 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
311 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
312 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
313 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
314 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
315 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
316 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
317 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
318 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
319 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
320 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
321 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
322 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
323 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
324 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
325 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
326 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
327 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
330 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
331 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
332 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
333 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
336 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
337 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
338 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
339 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
341 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
343 /* One-time-programmable memory general purpose reg */
344 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
345 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
346 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
347 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
350 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
351 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
352 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
353 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
354 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
358 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
361 * UCODE-DRIVER GP (general purpose) mailbox register 1
362 * Host driver and uCode write and/or read this register to communicate with
366 * Host sets this to request permanent halt of uCode, same as
367 * sending CARD_STATE command with "halt" bit set.
369 * Host sets this to request exit from CT_KILL state, i.e. host thinks
370 * device temperature is low enough to continue normal operation.
372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
373 * to release uCode to clear all Tx and command queues, enter
374 * unassociated mode, and power down.
375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
377 * Host sets this when issuing CARD_STATE command to request
380 * uCode sets this when preparing a power-saving power-down.
381 * uCode resets this when power-up is complete and SRAM is sane.
382 * NOTE: device saves internal SRAM data to host when powering down,
383 * and must restore this data after powering back up.
384 * MAC_SLEEP is the best indication that restore is complete.
385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
386 * do not need to save/restore it.
388 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
389 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
390 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
391 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
392 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
399 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
400 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
402 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
404 /* GIO Chicken Bits (PCI Express bus link power management) */
405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
406 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
409 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
410 #define IWM_CSR_LED_REG_TURN_ON (0x60)
411 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
414 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
417 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
420 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
421 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
422 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
424 /* SECURE boot registers */
425 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
426 enum iwm_secure_boot_config_reg {
427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
431 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
432 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
433 enum iwm_secure_boot_status_reg {
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
441 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
442 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70
443 enum iwm_secure_load_status_reg {
444 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
445 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
446 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
447 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
448 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
450 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
452 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38
453 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c
454 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
455 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
457 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000
458 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000
459 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
460 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
462 #define IWM_CSR_SECURE_TIME_OUT (100)
464 /* extended range in FW SRAM */
465 #define IWM_FW_MEM_EXTENDED_START 0x40000
466 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
468 /* FW chicken bits */
469 #define IWM_LMPM_CHICK 0xa01ff8
470 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
472 #define IWM_FH_TCSR_0_REG0 (0x1D00)
475 * HBUS (Host-side Bus)
477 * HBUS registers are mapped directly into PCI bus space, but are used
478 * to indirectly access device's internal memory or registers that
479 * may be powered-down.
481 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
482 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
483 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
484 * internal resources.
486 * Do not use iwl_write32()/iwl_read32() family to access these registers;
487 * these provide only simple PCI bus access, without waking up the MAC.
489 #define IWM_HBUS_BASE (0x400)
492 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
493 * structures, error log, event log, verifying uCode load).
494 * First write to address register, then read from or write to data register
495 * to complete the job. Once the address register is set up, accesses to
496 * data registers auto-increment the address by one dword.
497 * Bit usage for address registers (read or write):
498 * 0-31: memory address within device
500 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
501 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
502 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
503 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
505 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
506 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
507 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
510 * Registers for accessing device's internal peripheral registers
511 * (e.g. SCD, BSM, etc.). First write to address register,
512 * then read from or write to data register to complete the job.
513 * Bit usage for address registers (read or write):
514 * 0-15: register address (offset) within device
515 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
517 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
518 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
519 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
520 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
522 /* enable the ID buf for read */
523 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
524 #define IWM_WFMP_MAC_ADDR_0 0xa03080
525 #define IWM_WFMP_MAC_ADDR_1 0xa03084
526 #define IWM_LMPM_PMG_EN 0xa01cec
527 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
528 #define IWM_RFIC_REG_RD 0xad0470
529 #define IWM_WFPM_CTRL_REG 0xa03030
530 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
531 #define IWM_ENABLE_WFPM 0x80000000
533 #define IWM_AUX_MISC_REG 0xa200b0
534 #define IWM_HW_STEP_LOCATION_BITS 24
536 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
537 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
538 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
539 #define IWM_RSA_ENABLE 0xa24b08
540 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
541 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
542 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
543 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
544 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
545 #define IWM_SB_CPU_1_STATUS 0xa01e30
546 #define IWM_SB_CPU_2_STATUS 0Xa01e34
548 /* Used to enable DBGM */
549 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
552 * Per-Tx-queue write pointer (index, really!)
553 * Indicates index to next TFD that driver will fill (1 past latest filled).
555 * 0-7: queue write index
556 * 11-8: queue selector
558 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
560 /**********************************************************
562 **********************************************************/
564 * host interrupt timeout value
565 * used with setting interrupt coalescing timer
566 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
568 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
570 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
571 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
572 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
573 #define IWM_HOST_INT_OPER_MODE (1 << 31)
575 /*****************************************************************************
576 * 7000/3000 series SHR DTS addresses *
577 *****************************************************************************/
579 /* Diode Results Register Structure: */
580 enum iwm_dtd_diode_reg {
581 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
582 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
583 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
584 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
585 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
586 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
587 /* Those are the masks INSIDE the flags bit-field: */
588 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
589 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
590 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
591 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
603 * enum iwm_ucode_tlv_flag - ucode API flags
604 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
605 * was a separate TLV but moved here to save space.
606 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
607 * treats good CRC threshold as a boolean
608 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
609 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
610 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
611 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
612 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
613 * offload profile config command.
614 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
615 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
616 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
617 * (rather than two) IPv6 addresses
618 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
619 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
620 * from the probe request template.
621 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
622 * connection when going back to D0
623 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
624 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
625 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
626 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
627 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
628 * containing CAM (Continuous Active Mode) indication.
629 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
630 * single bound interface).
631 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
632 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
633 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
634 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
635 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
638 enum iwm_ucode_tlv_flag {
639 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
640 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
641 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
642 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
643 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
644 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
645 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
646 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
647 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
648 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
649 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
650 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
651 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
652 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
653 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
654 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
655 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
656 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
657 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
658 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
659 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22),
660 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23),
661 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
662 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
663 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
664 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
665 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30),
666 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31),
669 #define IWM_UCODE_TLV_FLAG_BITS \
670 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
671 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
672 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
673 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
676 * enum iwm_ucode_tlv_api - ucode api
677 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
678 * longer than the passive one, which is essential for fragmented scan.
679 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
680 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
681 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
682 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
684 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
685 * (command version 3) that supports per-chain limits
687 * @IWM_NUM_UCODE_TLV_API: number of bits used
689 enum iwm_ucode_tlv_api {
690 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8),
691 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9),
692 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14),
693 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18),
694 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24),
695 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27),
697 IWM_NUM_UCODE_TLV_API = 32
700 #define IWM_UCODE_TLV_API_BITS \
701 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
704 * enum iwm_ucode_tlv_capa - ucode capabilities
705 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
706 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
707 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
708 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
709 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
710 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
711 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
712 * tx power value into TPC Report action frame and Link Measurement Report
714 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
715 * channel in DS parameter set element in probe requests.
716 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
718 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
719 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
720 * which also implies support for the scheduler configuration command
721 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
722 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
723 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
724 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
725 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
726 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
727 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
728 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
729 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
730 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
731 * sources for the MCC. This TLV bit is a future replacement to
732 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
734 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
735 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
736 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
737 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
739 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
740 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
741 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
742 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
743 * antenna the beacon should be transmitted
744 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
745 * from AP and will send it upon d0i3 exit.
746 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
747 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
748 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
749 * thresholds reporting
750 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
751 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
753 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
754 * memory addresses from the firmware.
755 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
756 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
759 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
761 enum iwm_ucode_tlv_capa {
762 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
763 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
764 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
765 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
766 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
767 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
768 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
769 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
770 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
771 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
772 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
773 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
774 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
775 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
776 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
777 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
778 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
779 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
780 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
781 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
782 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
783 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
784 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
785 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
786 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
787 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
788 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
789 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
790 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
791 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
792 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
793 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
794 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
795 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
796 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
797 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
798 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79,
799 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
800 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
802 IWM_NUM_UCODE_TLV_CAPA = 128
805 /* The default calibrate table size if not specified by firmware file */
806 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
807 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
808 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
810 /* The default max probe length if not specified by the firmware file */
811 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
814 * enumeration of ucode section.
815 * This enumeration is used directly for older firmware (before 16.0).
816 * For new firmware, there can be up to 4 sections (see below) but the
817 * first one packaged into the firmware file is the DATA section and
818 * some debugging code accesses that.
821 IWM_UCODE_SECTION_DATA,
822 IWM_UCODE_SECTION_INST,
825 * For 16.0 uCode and above, there is no differentiation between sections,
826 * just an offset to the HW address.
828 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
829 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
831 /* uCode version contains 4 values: Major/Minor/API/Serial */
832 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
833 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
834 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
835 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
838 * Calibration control struct.
839 * Sent as part of the phy configuration command.
840 * @flow_trigger: bitmap for which calibrations to perform according to
842 * @event_trigger: bitmap for which calibrations to perform according to
845 struct iwm_tlv_calib_ctrl {
846 uint32_t flow_trigger;
847 uint32_t event_trigger;
850 enum iwm_fw_phy_cfg {
851 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
852 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
853 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
854 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
855 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
856 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
857 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
858 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
859 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
860 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
863 #define IWM_UCODE_MAX_CS 1
866 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
867 * @cipher: a cipher suite selector
868 * @flags: cipher scheme flags (currently reserved for a future use)
869 * @hdr_len: a size of MPDU security header
870 * @pn_len: a size of PN
871 * @pn_off: an offset of pn from the beginning of the security header
872 * @key_idx_off: an offset of key index byte in the security header
873 * @key_idx_mask: a bit mask of key_idx bits
874 * @key_idx_shift: bit shift needed to get key_idx
875 * @mic_len: mic length in bytes
876 * @hw_cipher: a HW cipher index used in host commands
878 struct iwm_fw_cipher_scheme {
885 uint8_t key_idx_mask;
886 uint8_t key_idx_shift;
892 * Block paging calculations
894 #define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */
895 #define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */
896 #define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3
897 /* 8 pages per group */
898 #define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE)
899 /* don't change, support only 32KB size */
900 #define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE)
902 #define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE)
905 * Image paging calculations
907 #define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5
908 /* 2^5 == 32 blocks per image */
909 #define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE)
910 /* maximum image size 1024KB */
911 #define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE)
914 * struct iwm_fw_cscheme_list - a cipher scheme list
915 * @size: a number of entries
916 * @cs: cipher scheme entries
918 struct iwm_fw_cscheme_list {
920 struct iwm_fw_cipher_scheme cs[];
928 * BEGIN iwl-fw-file.h
931 /* v1/v2 uCode file layout */
932 struct iwm_ucode_header {
933 uint32_t ver; /* major/minor/API/serial */
936 uint32_t inst_size; /* bytes of runtime code */
937 uint32_t data_size; /* bytes of runtime data */
938 uint32_t init_size; /* bytes of init code */
939 uint32_t init_data_size; /* bytes of init data */
940 uint32_t boot_size; /* bytes of bootstrap code */
941 uint8_t data[0]; /* in same order as sizes */
944 uint32_t build; /* build number */
945 uint32_t inst_size; /* bytes of runtime code */
946 uint32_t data_size; /* bytes of runtime data */
947 uint32_t init_size; /* bytes of init code */
948 uint32_t init_data_size; /* bytes of init data */
949 uint32_t boot_size; /* bytes of bootstrap code */
950 uint8_t data[0]; /* in same order as sizes */
956 * new TLV uCode file layout
958 * The new TLV file format contains TLVs, that each specify
959 * some piece of data.
962 enum iwm_ucode_tlv_type {
963 IWM_UCODE_TLV_INVALID = 0, /* unused */
964 IWM_UCODE_TLV_INST = 1,
965 IWM_UCODE_TLV_DATA = 2,
966 IWM_UCODE_TLV_INIT = 3,
967 IWM_UCODE_TLV_INIT_DATA = 4,
968 IWM_UCODE_TLV_BOOT = 5,
969 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
970 IWM_UCODE_TLV_PAN = 7,
971 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
972 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
973 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
974 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
975 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
976 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
977 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
978 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
979 IWM_UCODE_TLV_WOWLAN_INST = 16,
980 IWM_UCODE_TLV_WOWLAN_DATA = 17,
981 IWM_UCODE_TLV_FLAGS = 18,
982 IWM_UCODE_TLV_SEC_RT = 19,
983 IWM_UCODE_TLV_SEC_INIT = 20,
984 IWM_UCODE_TLV_SEC_WOWLAN = 21,
985 IWM_UCODE_TLV_DEF_CALIB = 22,
986 IWM_UCODE_TLV_PHY_SKU = 23,
987 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
988 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
989 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
990 IWM_UCODE_TLV_NUM_OF_CPU = 27,
991 IWM_UCODE_TLV_CSCHEME = 28,
994 * Following two are not in our base tag, but allow
995 * handling ucode version 9.
997 IWM_UCODE_TLV_API_CHANGES_SET = 29,
998 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
1000 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
1001 IWM_UCODE_TLV_PAGING = 32,
1002 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
1003 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
1004 IWM_UCODE_TLV_FW_VERSION = 36,
1005 IWM_UCODE_TLV_FW_DBG_DEST = 38,
1006 IWM_UCODE_TLV_FW_DBG_CONF = 39,
1007 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
1008 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
1011 struct iwm_ucode_tlv {
1012 uint32_t type; /* see above */
1013 uint32_t length; /* not including type/length fields */
1017 struct iwm_ucode_api {
1022 struct iwm_ucode_capa {
1027 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
1029 struct iwm_tlv_ucode_header {
1031 * The TLV style ucode header is distinguished from
1032 * the v1/v2 style header by first four bytes being
1033 * zero, as such is an invalid combination of
1034 * major/minor/API/serial versions.
1038 uint8_t human_readable[64];
1039 uint32_t ver; /* major/minor/API/serial */
1043 * The data contained herein has a TLV layout,
1044 * see above for the TLV header and types.
1045 * Note that each TLV is padded to a length
1046 * that is a multiple of 4 for alignment.
1060 * Registers in this file are internal, not PCI bus memory mapped.
1061 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
1063 #define IWM_PRPH_BASE (0x00000)
1064 #define IWM_PRPH_END (0xFFFFF)
1066 /* APMG (power management) constants */
1067 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1068 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1069 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1070 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1071 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1072 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1073 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1074 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1075 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1076 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1077 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1079 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1080 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1081 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1083 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1084 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1085 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1086 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1087 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1088 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1089 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1091 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1093 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1095 /* Device system time */
1096 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1098 /* Device NMI register */
1099 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1100 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1101 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1102 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1103 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1106 * Device reset for family 8000
1107 * write to bit 24 in order to reset the CPU
1109 #define IWM_RELEASE_CPU_RESET 0x300c
1110 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1113 /*****************************************************************************
1114 * 7000/3000 series SHR DTS addresses *
1115 *****************************************************************************/
1117 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1118 #define IWM_DTSC_CFG_MODE (0x00a10604)
1119 #define IWM_DTSC_VREF_AVG (0x00a10648)
1120 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1121 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1122 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1128 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1129 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1130 * host DRAM. It steers each frame's Tx command (which contains the frame
1131 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1132 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1133 * but one DMA channel may take input from several queues.
1135 * Tx DMA FIFOs have dedicated purposes.
1137 * For 5000 series and up, they are used differently
1138 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1140 * 0 -- EDCA BK (background) frames, lowest priority
1141 * 1 -- EDCA BE (best effort) frames, normal priority
1142 * 2 -- EDCA VI (video) frames, higher priority
1143 * 3 -- EDCA VO (voice) and management frames, highest priority
1149 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1150 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1151 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1153 * The driver sets up each queue to work in one of two modes:
1155 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1156 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1157 * contains TFDs for a unique combination of Recipient Address (RA)
1158 * and Traffic Identifier (TID), that is, traffic of a given
1159 * Quality-Of-Service (QOS) priority, destined for a single station.
1161 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1162 * each frame within the BA window, including whether it's been transmitted,
1163 * and whether it's been acknowledged by the receiving station. The device
1164 * automatically processes block-acks received from the receiving STA,
1165 * and reschedules un-acked frames to be retransmitted (successful
1166 * Tx completion may end up being out-of-order).
1168 * The driver must maintain the queue's Byte Count table in host DRAM
1170 * This mode does not support fragmentation.
1172 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1173 * The device may automatically retry Tx, but will retry only one frame
1174 * at a time, until receiving ACK from receiving station, or reaching
1175 * retry limit and giving up.
1177 * The command queue (#4/#9) must use this mode!
1178 * This mode does not require use of the Byte Count table in host DRAM.
1180 * Driver controls scheduler operation via 3 means:
1181 * 1) Scheduler registers
1182 * 2) Shared scheduler data base in internal SRAM
1183 * 3) Shared data in host DRAM
1187 * When loading, driver should allocate memory for:
1188 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1189 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1190 * (1024 bytes for each queue).
1192 * After receiving "Alive" response from uCode, driver must initialize
1193 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1194 * the driver can't issue commands!):
1196 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1199 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1200 * can keep track of at one time when creating block-ack chains of frames.
1201 * Note that "64" matches the number of ack bits in a block-ack packet.
1203 #define IWM_SCD_WIN_SIZE 64
1204 #define IWM_SCD_FRAME_LIMIT 64
1206 #define IWM_SCD_TXFIFO_POS_TID (0)
1207 #define IWM_SCD_TXFIFO_POS_RA (4)
1208 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1211 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1212 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1213 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1214 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1215 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1217 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1218 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1219 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1220 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1221 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1222 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1223 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1224 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1225 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1226 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1229 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1230 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1233 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1234 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1236 /* Translation Data */
1237 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1238 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1240 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1241 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1243 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1244 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1246 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1247 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1249 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1251 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1252 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1253 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1254 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1255 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1256 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1257 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1258 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1259 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1260 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1261 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1263 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1266 return IWM_SCD_BASE + 0x18 + chnl * 4;
1267 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1270 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1273 return IWM_SCD_BASE + 0x68 + chnl * 4;
1274 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1277 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1280 return IWM_SCD_BASE + 0x10c + chnl * 4;
1281 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1284 /*********************** END TX SCHEDULER *************************************/
1286 /* Oscillator clock */
1287 #define IWM_OSC_CLK (0xa04068)
1288 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1298 /****************************/
1299 /* Flow Handler Definitions */
1300 /****************************/
1303 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1304 * Addresses are offsets from device's PCI hardware base address.
1306 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1307 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1310 * Keep-Warm (KW) buffer base address.
1312 * Driver must allocate a 4KByte buffer that is for keeping the
1313 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1314 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1315 * from going into a power-savings mode that would cause higher DRAM latency,
1316 * and possible data over/under-runs, before all Tx/Rx is complete.
1318 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1319 * of the buffer, which must be 4K aligned. Once this is set up, the device
1320 * automatically invokes keep-warm accesses when normal accesses might not
1321 * be sufficient to maintain fast DRAM response.
1324 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1326 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1330 * TFD Circular Buffers Base (CBBC) addresses
1332 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1333 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1334 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1335 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1336 * aligned (address bits 0-7 must be 0).
1337 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1338 * for them are in different places.
1340 * Bit fields in each pointer register:
1341 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1343 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1344 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1345 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1346 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1347 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1348 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1350 /* Find TFD CB base pointer for given queue */
1351 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1354 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1356 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1357 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1362 * Rx SRAM Control and Status Registers (RSCSR)
1364 * These registers provide handshake between driver and device for the Rx queue
1365 * (this queue handles *all* command responses, notifications, Rx data, etc.
1366 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1367 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1368 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1369 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1370 * mapping between RBDs and RBs.
1372 * Driver must allocate host DRAM memory for the following, and set the
1373 * physical address of each into device registers:
1375 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1376 * entries (although any power of 2, up to 4096, is selectable by driver).
1377 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1378 * (typically 4K, although 8K or 16K are also selectable by driver).
1379 * Driver sets up RB size and number of RBDs in the CB via Rx config
1380 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1382 * Bit fields within one RBD:
1383 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1385 * Driver sets physical address [35:8] of base of RBD circular buffer
1386 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1388 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1389 * (RBs) have been filled, via a "write pointer", actually the index of
1390 * the RB's corresponding RBD within the circular buffer. Driver sets
1391 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1393 * Bit fields in lower dword of Rx status buffer (upper dword not used
1395 * 31-12: Not used by driver
1396 * 11- 0: Index of last filled Rx buffer descriptor
1397 * (device writes, driver reads this value)
1399 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1400 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1401 * and update the device's "write" index register,
1402 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1404 * This "write" index corresponds to the *next* RBD that the driver will make
1405 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1406 * the circular buffer. This value should initially be 0 (before preparing any
1407 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1408 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1409 * "read" index has advanced past 1! See below).
1410 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1412 * As the device fills RBs (referenced from contiguous RBDs within the circular
1413 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1414 * to tell the driver the index of the latest filled RBD. The driver must
1415 * read this "read" index from DRAM after receiving an Rx interrupt from device
1417 * The driver must also internally keep track of a third index, which is the
1418 * next RBD to process. When receiving an Rx interrupt, driver should process
1419 * all filled but unprocessed RBs up to, but not including, the RB
1420 * corresponding to the "read" index. For example, if "read" index becomes "1",
1421 * driver may process the RB pointed to by RBD 0. Depending on volume of
1422 * traffic, there may be many RBs to process.
1424 * If read index == write index, device thinks there is no room to put new data.
1425 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1426 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1427 * and "read" indexes; that is, make sure that there are no more than 254
1428 * buffers waiting to be filled.
1430 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1431 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1432 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1435 * Physical base address of 8-byte Rx Status buffer.
1437 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1439 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1442 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1444 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1446 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1449 * Rx write pointer (index, really!).
1451 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1452 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1454 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1455 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1457 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1458 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1461 * Rx Config/Status Registers (RCSR)
1462 * Rx Config Reg for channel 0 (only channel used)
1464 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1465 * normal operation (see bit fields).
1467 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1468 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1469 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1472 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1473 * '10' operate normally
1475 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1476 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1478 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1479 * '10' 12K, '11' 16K.
1481 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1482 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1483 * typical value 0x10 (about 1/2 msec)
1486 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1487 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1488 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1490 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1491 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1492 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1494 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1495 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1496 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1497 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1498 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1499 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1501 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1502 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1503 #define IWM_RX_RB_TIMEOUT (0x11)
1505 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1506 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1507 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1509 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1510 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1511 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1512 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1514 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1515 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1516 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1519 * Rx Shared Status Registers (RSSR)
1521 * After stopping Rx DMA channel (writing 0 to
1522 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1523 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1526 * 24: 1 = Channel 0 is idle
1528 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1529 * contain default values that should not be altered by the driver.
1531 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1532 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1534 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1535 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1536 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1537 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1539 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1541 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1543 /* TFDB Area - TFDs buffer table */
1544 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1545 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1546 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1547 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1548 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1551 * Transmit DMA Channel Control/Status Registers (TCSR)
1553 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1554 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1555 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1557 * To use a Tx DMA channel, driver must initialize its
1558 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1560 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1561 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1563 * All other bits should be 0.
1566 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1567 * '10' operate normally
1568 * 29- 4: Reserved, set to "0"
1569 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1570 * 2- 0: Reserved, set to "0"
1572 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1573 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1575 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1576 #define IWM_FH_TCSR_CHNL_NUM (8)
1578 /* TCSR: tx_config register values */
1579 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1580 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1581 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1582 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1583 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1584 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1586 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1587 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1589 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1590 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1592 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1593 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1594 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1596 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1597 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1598 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1600 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1601 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1602 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1604 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1605 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1606 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1608 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1609 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1612 * Tx Shared Status Registers (TSSR)
1614 * After stopping Tx DMA channel (writing 0 to
1615 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1616 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1617 * (channel's buffers empty | no pending requests).
1620 * 31-24: 1 = Channel buffers empty (channel 7:0)
1621 * 23-16: 1 = No pending requests (channel 7:0)
1623 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1624 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1626 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1629 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1630 * 31: Indicates an address error when accessed to internal memory
1631 * uCode/driver must write "1" in order to clear this flag
1632 * 30: Indicates that Host did not send the expected number of dwords to FH
1633 * uCode/driver must write "1" in order to clear this flag
1634 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1635 * command was received from the scheduler while the TRB was already full
1636 * with previous command
1637 * uCode/driver must write "1" in order to clear this flag
1638 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1639 * bit is set, it indicates that the FH has received a full indication
1640 * from the RTC TxFIFO and the current value of the TxCredit counter was
1641 * not equal to zero. This mean that the credit mechanism was not
1642 * synchronized to the TxFIFO status
1643 * uCode/driver must write "1" in order to clear this flag
1645 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1646 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1648 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1650 /* Tx service channels */
1651 #define IWM_FH_SRVC_CHNL (9)
1652 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1653 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1654 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1655 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1657 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1658 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1661 /* Instruct FH to increment the retry count of a packet when
1662 * it is brought from the memory to TX-FIFO
1664 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1666 #define IWM_RX_QUEUE_SIZE 256
1667 #define IWM_RX_QUEUE_MASK 255
1668 #define IWM_RX_QUEUE_SIZE_LOG 8
1671 * RX related structures and functions
1673 #define IWM_RX_FREE_BUFFERS 64
1674 #define IWM_RX_LOW_WATERMARK 8
1677 * struct iwm_rb_status - reseve buffer status
1678 * host memory mapped FH registers
1679 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1680 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1681 * @finished_rb_num [0:11] - Indicates the index of the current RB
1682 * in which the last frame was written to
1683 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1684 * which was transferred
1686 struct iwm_rb_status {
1687 uint16_t closed_rb_num;
1688 uint16_t closed_fr_num;
1689 uint16_t finished_rb_num;
1690 uint16_t finished_fr_nam;
1695 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1696 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1697 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1698 IWM_TFD_QUEUE_SIZE_BC_DUP)
1699 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1700 #define IWM_NUM_OF_TBS 20
1702 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1704 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1707 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1709 * This structure contains dma address and length of transmission address
1711 * @lo: low [31:0] portion of the dma address of TX buffer
1712 * every even is unaligned on 16 bit boundary
1713 * @hi_n_len 0-3 [35:32] portion of dma
1714 * 4-15 length of the tx buffer
1724 * Transmit Frame Descriptor (TFD)
1726 * @ __reserved1[3] reserved
1727 * @ num_tbs 0-4 number of active tbs
1729 * 6-7 padding (not used)
1730 * @ tbs[20] transmit frame buffer descriptors
1733 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1734 * Both driver and device share these circular buffers, each of which must be
1735 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1737 * Driver must indicate the physical address of the base of each
1738 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1740 * Each TFD contains pointer/size information for up to 20 data buffers
1741 * in host DRAM. These buffers collectively contain the (one) frame described
1742 * by the TFD. Each buffer must be a single contiguous block of memory within
1743 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1744 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1745 * Tx frame, up to 8 KBytes in size.
1747 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1750 uint8_t __reserved1[3];
1752 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1756 /* Keep Warm Size */
1757 #define IWM_KW_SIZE 0x1000 /* 4k */
1759 /* Fixed (non-configurable) rx data from phy */
1762 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1763 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1764 * @tfd_offset 0-12 - tx command byte count
1765 * 12-16 - station index
1767 struct iwm_agn_scd_bc_tbl {
1768 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1776 * BEGIN mvm/fw-api.h
1779 /* Maximum number of Tx queues. */
1780 #define IWM_MVM_MAX_QUEUES 31
1782 /* Tx queue numbers */
1784 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1785 IWM_MVM_CMD_QUEUE = 9,
1786 IWM_MVM_AUX_QUEUE = 15,
1789 enum iwm_mvm_tx_fifo {
1790 IWM_MVM_TX_FIFO_BK = 0,
1794 IWM_MVM_TX_FIFO_MCAST = 5,
1795 IWM_MVM_TX_FIFO_CMD = 7,
1798 #define IWM_MVM_STATION_COUNT 16
1802 IWM_MVM_ALIVE = 0x1,
1803 IWM_REPLY_ERROR = 0x2,
1805 IWM_INIT_COMPLETE_NOTIF = 0x4,
1807 /* PHY context commands */
1808 IWM_PHY_CONTEXT_CMD = 0x8,
1811 /* UMAC scan commands */
1812 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1813 IWM_SCAN_CFG_CMD = 0xc,
1814 IWM_SCAN_REQ_UMAC = 0xd,
1815 IWM_SCAN_ABORT_UMAC = 0xe,
1816 IWM_SCAN_COMPLETE_UMAC = 0xf,
1819 IWM_ADD_STA_KEY = 0x17,
1821 IWM_REMOVE_STA = 0x19,
1825 IWM_TXPATH_FLUSH = 0x1e,
1826 IWM_MGMT_MCAST_KEY = 0x1f,
1828 /* scheduler config */
1829 IWM_SCD_QUEUE_CFG = 0x1d,
1834 /* MAC and Binding commands */
1835 IWM_MAC_CONTEXT_CMD = 0x28,
1836 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1837 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1838 IWM_BINDING_CONTEXT_CMD = 0x2b,
1839 IWM_TIME_QUOTA_CMD = 0x2c,
1840 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1845 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1846 IWM_CALIBRATION_CFG_CMD = 0x65,
1847 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1848 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1849 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1852 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1853 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1854 IWM_HOT_SPOT_CMD = 0x53,
1855 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1856 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1857 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1858 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1859 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1862 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1863 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1864 /* IWM_PHY_DB_CMD = 0x6c, */
1866 /* Power - legacy power table command */
1867 IWM_POWER_TABLE_CMD = 0x77,
1868 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1870 /* Thermal Throttling*/
1871 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1874 IWM_SCAN_ABORT_CMD = 0x81,
1875 IWM_SCAN_START_NOTIFICATION = 0x82,
1876 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1879 IWM_NVM_ACCESS_CMD = 0x88,
1881 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1883 IWM_BEACON_NOTIFICATION = 0x90,
1884 IWM_BEACON_TEMPLATE_CMD = 0x91,
1885 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1886 IWM_BT_CONFIG = 0x9b,
1887 IWM_STATISTICS_NOTIFICATION = 0x9d,
1888 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1890 /* RF-KILL commands and notifications */
1891 IWM_CARD_STATE_CMD = 0xa0,
1892 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1894 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1896 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1898 /* Power - new power table command */
1899 IWM_MAC_PM_POWER_TABLE = 0xa9,
1901 IWM_REPLY_RX_PHY_CMD = 0xc0,
1902 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1903 IWM_BA_NOTIF = 0xc5,
1905 /* Location Aware Regulatory */
1906 IWM_MCC_UPDATE_CMD = 0xc8,
1907 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1910 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1911 IWM_BT_COEX_PROT_ENV = 0xcd,
1912 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1913 IWM_BT_COEX_CI = 0x5d,
1915 IWM_REPLY_SF_CFG_CMD = 0xd1,
1916 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1918 /* DTS measurements */
1919 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1920 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1922 IWM_REPLY_DEBUG_CMD = 0xf0,
1923 IWM_DEBUG_LOG_MSG = 0xf7,
1925 IWM_MCAST_FILTER_CMD = 0xd0,
1927 /* D3 commands/notifications */
1928 IWM_D3_CONFIG_CMD = 0xd3,
1929 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1930 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1931 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1933 /* for WoWLAN in particular */
1934 IWM_WOWLAN_PATTERNS = 0xe0,
1935 IWM_WOWLAN_CONFIGURATION = 0xe1,
1936 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1937 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1938 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1939 IWM_WOWLAN_GET_STATUSES = 0xe5,
1940 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1942 /* and for NetDetect */
1943 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1944 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1945 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1946 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1947 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1949 IWM_REPLY_MAX = 0xff,
1953 * struct iwm_cmd_response - generic response struct for most commands
1954 * @status: status of the command asked, changes for each one
1956 struct iwm_cmd_response {
1961 * struct iwm_tx_ant_cfg_cmd
1962 * @valid: valid antenna configuration
1964 struct iwm_tx_ant_cfg_cmd {
1969 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1970 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1971 * @flags: (reserved for future implementation)
1972 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1973 * @pwr_restriction: TX power restriction in dBms.
1975 struct iwm_reduce_tx_power_cmd {
1977 uint8_t mac_context_id;
1978 uint16_t pwr_restriction;
1979 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1982 * Calibration control struct.
1983 * Sent as part of the phy configuration command.
1984 * @flow_trigger: bitmap for which calibrations to perform according to
1986 * @event_trigger: bitmap for which calibrations to perform according to
1989 struct iwm_calib_ctrl {
1990 uint32_t flow_trigger;
1991 uint32_t event_trigger;
1994 /* This enum defines the bitmap of various calibrations to enable in both
1995 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1997 enum iwm_calib_cfg {
1998 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1999 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
2000 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
2001 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
2002 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
2003 IWM_CALIB_CFG_DC_IDX = (1 << 5),
2004 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
2005 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
2006 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
2007 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
2008 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
2009 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
2010 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
2011 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
2012 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
2013 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
2014 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
2015 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
2016 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
2020 * Phy configuration command.
2022 struct iwm_phy_cfg_cmd {
2024 struct iwm_calib_ctrl calib_control;
2027 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
2028 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
2029 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
2030 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
2031 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
2032 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
2033 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
2034 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
2035 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
2036 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
2039 /* Target of the IWM_NVM_ACCESS_CMD */
2041 IWM_NVM_ACCESS_TARGET_CACHE = 0,
2042 IWM_NVM_ACCESS_TARGET_OTP = 1,
2043 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
2046 /* Section types for IWM_NVM_ACCESS_CMD */
2048 IWM_NVM_SECTION_TYPE_SW = 1,
2049 IWM_NVM_SECTION_TYPE_REGULATORY = 3,
2050 IWM_NVM_SECTION_TYPE_CALIBRATION = 4,
2051 IWM_NVM_SECTION_TYPE_PRODUCTION = 5,
2052 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
2053 IWM_NVM_SECTION_TYPE_PHY_SKU = 12,
2054 IWM_NVM_MAX_NUM_SECTIONS = 13,
2058 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2059 * @op_code: 0 - read, 1 - write
2060 * @target: IWM_NVM_ACCESS_TARGET_*
2061 * @type: IWM_NVM_SECTION_TYPE_*
2062 * @offset: offset in bytes into the section
2063 * @length: in bytes, to read/write
2064 * @data: if write operation, the data to write. On read its empty
2066 struct iwm_nvm_access_cmd {
2073 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2076 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2077 * @offset: offset in bytes into the section
2078 * @length: in bytes, either how much was written or read
2079 * @type: IWM_NVM_SECTION_TYPE_*
2080 * @status: 0 for success, fail otherwise
2081 * @data: if read operation, the data returned. Empty on write.
2083 struct iwm_nvm_access_resp {
2089 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2091 /* IWM_MVM_ALIVE 0x1 */
2093 /* alive response is_valid values */
2094 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2095 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2097 /* alive response ver_type values */
2100 IWM_FW_TYPE_PROT = 1,
2102 IWM_FW_TYPE_WOWLAN = 3,
2103 IWM_FW_TYPE_TIMING = 4,
2104 IWM_FW_TYPE_WIPAN = 5
2107 /* alive response ver_subtype values */
2109 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2110 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2111 IWM_FW_SUBTYPE_REDUCED = 2,
2112 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2113 IWM_FW_SUBTYPE_WOWLAN = 4,
2114 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2115 IWM_FW_SUBTYPE_WIPAN = 6,
2116 IWM_FW_SUBTYPE_INITIALIZE = 9
2119 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2120 #define IWM_ALIVE_STATUS_OK 0xCAFE
2122 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2124 struct iwm_mvm_alive_resp_v1 {
2127 uint8_t ucode_minor;
2128 uint8_t ucode_major;
2132 uint8_t ver_subtype;
2138 uint32_t error_event_table_ptr; /* SRAM address for error log */
2139 uint32_t log_event_table_ptr; /* SRAM address for event log */
2140 uint32_t cpu_register_ptr;
2141 uint32_t dbgm_config_ptr;
2142 uint32_t alive_counter_ptr;
2143 uint32_t scd_base_ptr; /* SRAM address for SCD */
2144 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2146 struct iwm_mvm_alive_resp_v2 {
2149 uint8_t ucode_minor;
2150 uint8_t ucode_major;
2154 uint8_t ver_subtype;
2160 uint32_t error_event_table_ptr; /* SRAM address for error log */
2161 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2162 uint32_t cpu_register_ptr;
2163 uint32_t dbgm_config_ptr;
2164 uint32_t alive_counter_ptr;
2165 uint32_t scd_base_ptr; /* SRAM address for SCD */
2166 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2167 uint32_t st_fwrd_size;
2168 uint8_t umac_minor; /* UMAC version: minor */
2169 uint8_t umac_major; /* UMAC version: major */
2170 uint16_t umac_id; /* UMAC version: id */
2171 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2172 uint32_t dbg_print_buff_addr;
2173 } __packed; /* ALIVE_RES_API_S_VER_2 */
2175 struct iwm_mvm_alive_resp_v3 {
2178 uint32_t ucode_minor;
2179 uint32_t ucode_major;
2180 uint8_t ver_subtype;
2185 uint32_t error_event_table_ptr; /* SRAM address for error log */
2186 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2187 uint32_t cpu_register_ptr;
2188 uint32_t dbgm_config_ptr;
2189 uint32_t alive_counter_ptr;
2190 uint32_t scd_base_ptr; /* SRAM address for SCD */
2191 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2192 uint32_t st_fwrd_size;
2193 uint32_t umac_minor; /* UMAC version: minor */
2194 uint32_t umac_major; /* UMAC version: major */
2195 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2196 uint32_t dbg_print_buff_addr;
2197 } __packed; /* ALIVE_RES_API_S_VER_3 */
2199 /* Error response/notification */
2201 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2202 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2203 IWM_FW_ERR_SERVICE = 0x2,
2204 IWM_FW_ERR_ARC_MEMORY = 0x3,
2205 IWM_FW_ERR_ARC_CODE = 0x4,
2206 IWM_FW_ERR_WATCH_DOG = 0x5,
2207 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2208 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2209 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2210 IWM_FW_ERR_UNEXPECTED = 0xFE,
2211 IWM_FW_ERR_FATAL = 0xFF
2215 * struct iwm_error_resp - FW error indication
2216 * ( IWM_REPLY_ERROR = 0x2 )
2217 * @error_type: one of IWM_FW_ERR_*
2218 * @cmd_id: the command ID for which the error occurred
2219 * @bad_cmd_seq_num: sequence number of the erroneous command
2220 * @error_service: which service created the error, applicable only if
2221 * error_type = 2, otherwise 0
2222 * @timestamp: TSF in usecs.
2224 struct iwm_error_resp {
2225 uint32_t error_type;
2228 uint16_t bad_cmd_seq_num;
2229 uint32_t error_service;
2234 /* Common PHY, MAC and Bindings definitions */
2236 #define IWM_MAX_MACS_IN_BINDING (3)
2237 #define IWM_MAX_BINDINGS (4)
2238 #define IWM_AUX_BINDING_INDEX (3)
2239 #define IWM_MAX_PHYS (4)
2241 /* Used to extract ID and color from the context dword */
2242 #define IWM_FW_CTXT_ID_POS (0)
2243 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2244 #define IWM_FW_CTXT_COLOR_POS (8)
2245 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2246 #define IWM_FW_CTXT_INVALID (0xffffffff)
2248 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2249 (_color << IWM_FW_CTXT_COLOR_POS))
2251 /* Possible actions on PHYs, MACs and Bindings */
2253 IWM_FW_CTXT_ACTION_STUB = 0,
2254 IWM_FW_CTXT_ACTION_ADD,
2255 IWM_FW_CTXT_ACTION_MODIFY,
2256 IWM_FW_CTXT_ACTION_REMOVE,
2257 IWM_FW_CTXT_ACTION_NUM
2258 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2262 /* Time Event types, according to MAC type */
2263 enum iwm_time_event_type {
2264 /* BSS Station Events */
2265 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2266 IWM_TE_BSS_STA_ASSOC,
2267 IWM_TE_BSS_EAP_DHCP_PROT,
2268 IWM_TE_BSS_QUIET_PERIOD,
2270 /* P2P Device Events */
2271 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2272 IWM_TE_P2P_DEVICE_LISTEN,
2273 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2274 IWM_TE_P2P_DEVICE_FULL_SCAN,
2276 /* P2P Client Events */
2277 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2278 IWM_TE_P2P_CLIENT_ASSOC,
2279 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2282 IWM_TE_P2P_GO_ASSOC_PROT,
2283 IWM_TE_P2P_GO_REPETITIVE_NOA,
2284 IWM_TE_P2P_GO_CT_WINDOW,
2286 /* WiDi Sync Events */
2287 IWM_TE_WIDI_TX_SYNC,
2290 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2294 /* Time event - defines for command API v1 */
2297 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2298 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2299 * the first fragment is scheduled.
2300 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2301 * the first 2 fragments are scheduled.
2302 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2303 * number of fragments are valid.
2305 * Other than the constant defined above, specifying a fragmentation value 'x'
2306 * means that the event can be fragmented but only the first 'x' will be
2310 IWM_TE_V1_FRAG_NONE = 0,
2311 IWM_TE_V1_FRAG_SINGLE = 1,
2312 IWM_TE_V1_FRAG_DUAL = 2,
2313 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2316 /* If a Time Event can be fragmented, this is the max number of fragments */
2317 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2318 /* Repeat the time event endlessly (until removed) */
2319 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2320 /* If a Time Event has bounded repetitions, this is the maximal value */
2321 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2323 /* Time Event dependencies: none, on another TE, or in a specific time */
2325 IWM_TE_V1_INDEPENDENT = 0,
2326 IWM_TE_V1_DEP_OTHER = (1 << 0),
2327 IWM_TE_V1_DEP_TSF = (1 << 1),
2328 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2329 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2332 * @IWM_TE_V1_NOTIF_NONE: no notifications
2333 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2334 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2335 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2336 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2337 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2338 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2339 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2340 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2342 * Supported Time event notifications configuration.
2343 * A notification (both event and fragment) includes a status indicating weather
2344 * the FW was able to schedule the event or not. For fragment start/end
2345 * notification the status is always success. There is no start/end fragment
2346 * notification for monolithic events.
2349 IWM_TE_V1_NOTIF_NONE = 0,
2350 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2351 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2352 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2353 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2354 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2355 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2356 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2357 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2358 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2359 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2363 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2364 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2365 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2366 * ( IWM_TIME_EVENT_CMD = 0x29 )
2367 * @id_and_color: ID and color of the relevant MAC
2368 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2369 * @id: this field has two meanings, depending on the action:
2370 * If the action is ADD, then it means the type of event to add.
2371 * For all other actions it is the unique event ID assigned when the
2372 * event was added by the FW.
2373 * @apply_time: When to start the Time Event (in GP2)
2374 * @max_delay: maximum delay to event's start (apply time), in TU
2375 * @depends_on: the unique ID of the event we depend on (if any)
2376 * @interval: interval between repetitions, in TU
2377 * @interval_reciprocal: 2^32 / interval
2378 * @duration: duration of event in TU
2379 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2380 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2381 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2382 * @is_present: 0 or 1, are we present or absent during the Time Event
2383 * @max_frags: maximal number of fragments the Time Event can be divided to
2384 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2386 struct iwm_time_event_cmd_v1 {
2387 /* COMMON_INDEX_HDR_API_S_VER_1 */
2388 uint32_t id_and_color;
2391 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2392 uint32_t apply_time;
2394 uint32_t dep_policy;
2395 uint32_t depends_on;
2396 uint32_t is_present;
2399 uint32_t interval_reciprocal;
2403 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2406 /* Time event - defines for command API v2 */
2409 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2410 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2411 * the first fragment is scheduled.
2412 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2413 * the first 2 fragments are scheduled.
2414 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2415 * number of fragments are valid.
2417 * Other than the constant defined above, specifying a fragmentation value 'x'
2418 * means that the event can be fragmented but only the first 'x' will be
2422 IWM_TE_V2_FRAG_NONE = 0,
2423 IWM_TE_V2_FRAG_SINGLE = 1,
2424 IWM_TE_V2_FRAG_DUAL = 2,
2425 IWM_TE_V2_FRAG_MAX = 0xfe,
2426 IWM_TE_V2_FRAG_ENDLESS = 0xff
2429 /* Repeat the time event endlessly (until removed) */
2430 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2431 /* If a Time Event has bounded repetitions, this is the maximal value */
2432 #define IWM_TE_V2_REPEAT_MAX 0xfe
2434 #define IWM_TE_V2_PLACEMENT_POS 12
2435 #define IWM_TE_V2_ABSENCE_POS 15
2437 /* Time event policy values (for time event cmd api v2)
2438 * A notification (both event and fragment) includes a status indicating weather
2439 * the FW was able to schedule the event or not. For fragment start/end
2440 * notification the status is always success. There is no start/end fragment
2441 * notification for monolithic events.
2443 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2444 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2445 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2446 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2447 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2448 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2449 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2450 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2451 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2452 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2453 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2454 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2455 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2458 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2460 /* notifications (event start/stop, fragment start/stop) */
2461 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2462 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2463 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2464 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2466 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2467 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2468 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2469 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2471 IWM_TE_V2_NOTIF_MSK = 0xff,
2473 /* placement characteristics */
2474 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2475 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2476 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2478 /* are we present or absent during the Time Event. */
2479 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2483 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2484 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2485 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2486 * ( IWM_TIME_EVENT_CMD = 0x29 )
2487 * @id_and_color: ID and color of the relevant MAC
2488 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2489 * @id: this field has two meanings, depending on the action:
2490 * If the action is ADD, then it means the type of event to add.
2491 * For all other actions it is the unique event ID assigned when the
2492 * event was added by the FW.
2493 * @apply_time: When to start the Time Event (in GP2)
2494 * @max_delay: maximum delay to event's start (apply time), in TU
2495 * @depends_on: the unique ID of the event we depend on (if any)
2496 * @interval: interval between repetitions, in TU
2497 * @duration: duration of event in TU
2498 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2499 * @max_frags: maximal number of fragments the Time Event can be divided to
2500 * @policy: defines whether uCode shall notify the host or other uCode modules
2501 * on event and/or fragment start and/or end
2502 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2503 * IWM_TE_EVENT_SOCIOPATHIC
2504 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2506 struct iwm_time_event_cmd_v2 {
2507 /* COMMON_INDEX_HDR_API_S_VER_1 */
2508 uint32_t id_and_color;
2511 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2512 uint32_t apply_time;
2514 uint32_t depends_on;
2520 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2523 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2524 * @status: bit 0 indicates success, all others specify errors
2525 * @id: the Time Event type
2526 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2527 * @id_and_color: ID and color of the relevant MAC
2529 struct iwm_time_event_resp {
2533 uint32_t id_and_color;
2534 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2537 * struct iwm_time_event_notif - notifications of time event start/stop
2538 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2539 * @timestamp: action timestamp in GP2
2540 * @session_id: session's unique id
2541 * @unique_id: unique id of the Time Event itself
2542 * @id_and_color: ID and color of the relevant MAC
2543 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2544 * @status: true if scheduled, false otherwise (not executed)
2546 struct iwm_time_event_notif {
2548 uint32_t session_id;
2550 uint32_t id_and_color;
2553 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2556 /* Bindings and Time Quota */
2559 * struct iwm_binding_cmd - configuring bindings
2560 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2561 * @id_and_color: ID and color of the relevant Binding
2562 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2563 * @macs: array of MAC id and colors which belong to the binding
2564 * @phy: PHY id and color which belongs to the binding
2566 struct iwm_binding_cmd {
2567 /* COMMON_INDEX_HDR_API_S_VER_1 */
2568 uint32_t id_and_color;
2570 /* IWM_BINDING_DATA_API_S_VER_1 */
2571 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2573 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2575 /* The maximal number of fragments in the FW's schedule session */
2576 #define IWM_MVM_MAX_QUOTA 128
2579 * struct iwm_time_quota_data - configuration of time quota per binding
2580 * @id_and_color: ID and color of the relevant Binding
2581 * @quota: absolute time quota in TU. The scheduler will try to divide the
2582 * remainig quota (after Time Events) according to this quota.
2583 * @max_duration: max uninterrupted context duration in TU
2585 struct iwm_time_quota_data {
2586 uint32_t id_and_color;
2588 uint32_t max_duration;
2589 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2592 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2593 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2594 * @quotas: allocations per binding
2596 struct iwm_time_quota_cmd {
2597 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2598 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2603 /* Supported bands */
2604 #define IWM_PHY_BAND_5 (0)
2605 #define IWM_PHY_BAND_24 (1)
2607 /* Supported channel width, vary if there is VHT support */
2608 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2609 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2610 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2611 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2614 * Control channel position:
2615 * For legacy set bit means upper channel, otherwise lower.
2616 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2617 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2620 * 40Mhz |_______|_______|
2621 * 80Mhz |_______|_______|_______|_______|
2622 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2623 * code 011 010 001 000 | 100 101 110 111
2625 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2626 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2627 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2628 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2629 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2630 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2631 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2632 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2635 * @band: IWM_PHY_BAND_*
2636 * @channel: channel number
2637 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2638 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2640 struct iwm_fw_channel_info {
2647 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2648 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2649 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2650 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2651 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2652 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2653 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2654 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2655 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2656 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2657 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2658 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2659 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2660 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2661 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2662 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2663 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2664 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2665 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2666 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2667 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2669 /* TODO: fix the value, make it depend on firmware at runtime? */
2670 #define IWM_NUM_PHY_CTX 3
2672 /* TODO: complete missing documentation */
2674 * struct iwm_phy_context_cmd - config of the PHY context
2675 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2676 * @id_and_color: ID and color of the relevant Binding
2677 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2678 * @apply_time: 0 means immediate apply and context switch.
2679 * other value means apply new params after X usecs
2680 * @tx_param_color: ???
2682 * @txchain_info: ???
2683 * @rxchain_info: ???
2684 * @acquisition_data: ???
2685 * @dsp_cfg_flags: set to 0
2687 struct iwm_phy_context_cmd {
2688 /* COMMON_INDEX_HDR_API_S_VER_1 */
2689 uint32_t id_and_color;
2691 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2692 uint32_t apply_time;
2693 uint32_t tx_param_color;
2694 struct iwm_fw_channel_info ci;
2695 uint32_t txchain_info;
2696 uint32_t rxchain_info;
2697 uint32_t acquisition_data;
2698 uint32_t dsp_cfg_flags;
2699 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2701 #define IWM_RX_INFO_PHY_CNT 8
2702 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2703 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2704 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2705 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2706 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2707 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2708 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2710 #define IWM_RX_INFO_AGC_IDX 1
2711 #define IWM_RX_INFO_RSSI_AB_IDX 2
2712 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2713 #define IWM_OFDM_AGC_A_POS 0
2714 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2715 #define IWM_OFDM_AGC_B_POS 7
2716 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2717 #define IWM_OFDM_AGC_CODE_POS 20
2718 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2719 #define IWM_OFDM_RSSI_A_POS 0
2720 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2721 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2722 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2723 #define IWM_OFDM_RSSI_B_POS 16
2724 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2725 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2728 * struct iwm_rx_phy_info - phy info
2729 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2730 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2731 * @cfg_phy_cnt: configurable DSP phy data byte count
2732 * @stat_id: configurable DSP phy data set ID
2734 * @system_timestamp: GP2 at on air rise
2735 * @timestamp: TSF at on air rise
2736 * @beacon_time_stamp: beacon at on-air rise
2737 * @phy_flags: general phy flags: band, modulation, ...
2738 * @channel: channel number
2739 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2740 * @rate_n_flags: IWM_RATE_MCS_*
2741 * @byte_count: frame's byte-count
2742 * @frame_time: frame's time on the air, based on byte count and frame rate
2744 * @mac_active_msk: what MACs were active when the frame was received
2746 * Before each Rx, the device sends this data. It contains PHY information
2747 * about the reception of the packet.
2749 struct iwm_rx_phy_info {
2750 uint8_t non_cfg_phy_cnt;
2751 uint8_t cfg_phy_cnt;
2754 uint32_t system_timestamp;
2756 uint32_t beacon_time_stamp;
2758 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2760 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2764 uint32_t byte_count;
2765 uint16_t mac_active_msk;
2766 uint16_t frame_time;
2769 struct iwm_rx_mpdu_res_start {
2770 uint16_t byte_count;
2775 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2776 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2777 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2778 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2779 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2780 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2781 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2782 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2783 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2784 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2786 enum iwm_rx_phy_flags {
2787 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2788 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2789 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2790 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2791 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2792 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2793 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2794 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2795 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2796 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2800 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2801 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2802 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2803 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2804 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2805 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2806 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2807 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2809 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2810 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2811 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2812 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2813 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2814 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2815 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2816 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2817 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2818 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2819 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2820 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2821 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2822 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2823 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2824 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2825 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2826 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2827 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2828 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2829 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2831 enum iwm_mvm_rx_status {
2832 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2833 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2834 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2835 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2836 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2837 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2838 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2839 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2840 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2841 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2842 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2843 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2844 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2845 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2846 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2847 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2848 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2849 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2850 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2851 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2852 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2853 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2854 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2855 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2856 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2857 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2858 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2862 * struct iwm_radio_version_notif - information on the radio version
2863 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2868 struct iwm_radio_version_notif {
2869 uint32_t radio_flavor;
2870 uint32_t radio_step;
2871 uint32_t radio_dash;
2872 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2874 enum iwm_card_state_flags {
2875 IWM_CARD_ENABLED = 0x00,
2876 IWM_HW_CARD_DISABLED = 0x01,
2877 IWM_SW_CARD_DISABLED = 0x02,
2878 IWM_CT_KILL_CARD_DISABLED = 0x04,
2879 IWM_HALT_CARD_DISABLED = 0x08,
2880 IWM_CARD_DISABLED_MSK = 0x0f,
2881 IWM_CARD_IS_RX_ON = 0x10,
2885 * struct iwm_radio_version_notif - information on the radio version
2886 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2887 * @flags: %iwm_card_state_flags
2889 struct iwm_card_state_notif {
2891 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2894 * struct iwm_missed_beacons_notif - information on missed beacons
2895 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2896 * @mac_id: interface ID
2897 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2898 * beacons since last RX.
2899 * @consec_missed_beacons: number of consecutive missed beacons
2900 * @num_expected_beacons:
2901 * @num_recvd_beacons:
2903 struct iwm_missed_beacons_notif {
2905 uint32_t consec_missed_beacons_since_last_rx;
2906 uint32_t consec_missed_beacons;
2907 uint32_t num_expected_beacons;
2908 uint32_t num_recvd_beacons;
2909 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2912 * struct iwm_mfuart_load_notif - mfuart image version & status
2913 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2914 * @installed_ver: installed image version
2915 * @external_ver: external image version
2916 * @status: MFUART loading status
2917 * @duration: MFUART loading time
2919 struct iwm_mfuart_load_notif {
2920 uint32_t installed_ver;
2921 uint32_t external_ver;
2924 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2927 * struct iwm_set_calib_default_cmd - set default value for calibration.
2928 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2929 * @calib_index: the calibration to set value for
2931 * @data: the value to set for the calibration result
2933 struct iwm_set_calib_default_cmd {
2934 uint16_t calib_index;
2937 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2939 #define IWM_MAX_PORT_ID_NUM 2
2940 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2943 * struct iwm_mcast_filter_cmd - configure multicast filter.
2944 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2945 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2946 * to identify network interface adopted in host-device IF.
2947 * It is used by FW as index in array of addresses. This array has
2948 * IWM_MAX_PORT_ID_NUM members.
2949 * @count: Number of MAC addresses in the array
2950 * @pass_all: Set 1 to pass all multicast packets.
2951 * @bssid: current association BSSID.
2952 * @addr_list: Place holder for array of MAC addresses.
2953 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2955 struct iwm_mcast_filter_cmd {
2961 uint8_t reserved[2];
2962 uint8_t addr_list[0];
2963 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2965 struct iwm_mvm_statistics_dbg {
2966 uint32_t burst_check;
2967 uint32_t burst_count;
2968 uint32_t wait_for_silence_timeout_cnt;
2969 uint32_t reserved[3];
2970 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2972 struct iwm_mvm_statistics_div {
2976 uint32_t probe_time;
2979 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2981 struct iwm_mvm_statistics_general_common {
2982 uint32_t temperature; /* radio temperature */
2983 uint32_t temperature_m; /* radio voltage */
2984 struct iwm_mvm_statistics_dbg dbg;
2985 uint32_t sleep_time;
2987 uint32_t slots_idle;
2988 uint32_t ttl_timestamp;
2989 struct iwm_mvm_statistics_div div;
2990 uint32_t rx_enable_counter;
2992 * num_of_sos_states:
2993 * count the number of times we have to re-tune
2994 * in order to get out of bad PHY status
2996 uint32_t num_of_sos_states;
2997 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2999 struct iwm_mvm_statistics_rx_non_phy {
3000 uint32_t bogus_cts; /* CTS received when not expecting CTS */
3001 uint32_t bogus_ack; /* ACK received when not expecting ACK */
3002 uint32_t non_bssid_frames; /* number of frames with BSSID that
3003 * doesn't belong to the STA BSSID */
3004 uint32_t filtered_frames; /* count frames that were dumped in the
3005 * filtering process */
3006 uint32_t non_channel_beacons; /* beacons with our bss id but not on
3007 * our serving channel */
3008 uint32_t channel_beacons; /* beacons with our bss id and in our
3009 * serving channel */
3010 uint32_t num_missed_bcon; /* number of missed beacons */
3011 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
3012 * ADC was in saturation */
3013 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
3015 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
3016 uint32_t interference_data_flag; /* flag for interference data
3017 * availability. 1 when data is
3019 uint32_t channel_load; /* counts RX Enable time in uSec */
3020 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
3021 * and CCK) counter */
3022 uint32_t beacon_rssi_a;
3023 uint32_t beacon_rssi_b;
3024 uint32_t beacon_rssi_c;
3025 uint32_t beacon_energy_a;
3026 uint32_t beacon_energy_b;
3027 uint32_t beacon_energy_c;
3028 uint32_t num_bt_kills;
3030 uint32_t directed_data_mpdu;
3031 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
3033 struct iwm_mvm_statistics_rx_phy {
3038 uint32_t overrun_err;
3039 uint32_t early_overrun_err;
3040 uint32_t crc32_good;
3041 uint32_t false_alarm_cnt;
3042 uint32_t fina_sync_err_cnt;
3043 uint32_t sfd_timeout;
3044 uint32_t fina_timeout;
3045 uint32_t unresponded_rts;
3046 uint32_t rxe_frame_limit_overrun;
3047 uint32_t sent_ack_cnt;
3048 uint32_t sent_cts_cnt;
3049 uint32_t sent_ba_rsp_cnt;
3050 uint32_t dsp_self_kill;
3051 uint32_t mh_format_err;
3052 uint32_t re_acq_main_rssi_sum;
3054 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
3056 struct iwm_mvm_statistics_rx_ht_phy {
3058 uint32_t overrun_err;
3059 uint32_t early_overrun_err;
3060 uint32_t crc32_good;
3062 uint32_t mh_format_err;
3063 uint32_t agg_crc32_good;
3064 uint32_t agg_mpdu_cnt;
3066 uint32_t unsupport_mcs;
3067 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3069 #define IWM_MAX_CHAINS 3
3071 struct iwm_mvm_statistics_tx_non_phy_agg {
3072 uint32_t ba_timeout;
3073 uint32_t ba_reschedule_frames;
3074 uint32_t scd_query_agg_frame_cnt;
3075 uint32_t scd_query_no_agg;
3076 uint32_t scd_query_agg;
3077 uint32_t scd_query_mismatch;
3078 uint32_t frame_not_ready;
3080 uint32_t bt_prio_kill;
3081 uint32_t rx_ba_rsp_cnt;
3082 int8_t txpower[IWM_MAX_CHAINS];
3085 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3087 struct iwm_mvm_statistics_tx_channel_width {
3088 uint32_t ext_cca_narrow_ch20[1];
3089 uint32_t ext_cca_narrow_ch40[2];
3090 uint32_t ext_cca_narrow_ch80[3];
3091 uint32_t ext_cca_narrow_ch160[4];
3092 uint32_t last_tx_ch_width_indx;
3093 uint32_t rx_detected_per_ch_width[4];
3094 uint32_t success_per_ch_width[4];
3095 uint32_t fail_per_ch_width[4];
3096 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3098 struct iwm_mvm_statistics_tx {
3099 uint32_t preamble_cnt;
3100 uint32_t rx_detected_cnt;
3101 uint32_t bt_prio_defer_cnt;
3102 uint32_t bt_prio_kill_cnt;
3103 uint32_t few_bytes_cnt;
3104 uint32_t cts_timeout;
3105 uint32_t ack_timeout;
3106 uint32_t expected_ack_cnt;
3107 uint32_t actual_ack_cnt;
3108 uint32_t dump_msdu_cnt;
3109 uint32_t burst_abort_next_frame_mismatch_cnt;
3110 uint32_t burst_abort_missing_next_frame_cnt;
3111 uint32_t cts_timeout_collision;
3112 uint32_t ack_or_ba_timeout_collision;
3113 struct iwm_mvm_statistics_tx_non_phy_agg agg;
3114 struct iwm_mvm_statistics_tx_channel_width channel_width;
3115 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3118 struct iwm_mvm_statistics_bt_activity {
3119 uint32_t hi_priority_tx_req_cnt;
3120 uint32_t hi_priority_tx_denied_cnt;
3121 uint32_t lo_priority_tx_req_cnt;
3122 uint32_t lo_priority_tx_denied_cnt;
3123 uint32_t hi_priority_rx_req_cnt;
3124 uint32_t hi_priority_rx_denied_cnt;
3125 uint32_t lo_priority_rx_req_cnt;
3126 uint32_t lo_priority_rx_denied_cnt;
3127 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3129 struct iwm_mvm_statistics_general {
3130 struct iwm_mvm_statistics_general_common common;
3131 uint32_t beacon_filtered;
3132 uint32_t missed_beacons;
3133 int8_t beacon_filter_average_energy;
3134 int8_t beacon_filter_reason;
3135 int8_t beacon_filter_current_energy;
3136 int8_t beacon_filter_reserved;
3137 uint32_t beacon_filter_delta_time;
3138 struct iwm_mvm_statistics_bt_activity bt_activity;
3139 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3141 struct iwm_mvm_statistics_rx {
3142 struct iwm_mvm_statistics_rx_phy ofdm;
3143 struct iwm_mvm_statistics_rx_phy cck;
3144 struct iwm_mvm_statistics_rx_non_phy general;
3145 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
3146 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3149 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3151 * By default, uCode issues this notification after receiving a beacon
3152 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3153 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3155 * Statistics counters continue to increment beacon after beacon, but are
3156 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3157 * 0x9c with CLEAR_STATS bit set (see above).
3159 * uCode also issues this notification during scans. uCode clears statistics
3160 * appropriately so that each notification contains statistics for only the
3161 * one channel that has just been scanned.
3164 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3166 struct iwm_mvm_statistics_rx rx;
3167 struct iwm_mvm_statistics_tx tx;
3168 struct iwm_mvm_statistics_general general;
3171 /***********************************
3173 ***********************************/
3174 /* Smart Fifo state */
3176 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3180 IWM_SF_HW_NUM_STATES
3183 /* Smart Fifo possible scenario */
3184 enum iwm_sf_scenario {
3185 IWM_SF_SCENARIO_SINGLE_UNICAST,
3186 IWM_SF_SCENARIO_AGG_UNICAST,
3187 IWM_SF_SCENARIO_MULTICAST,
3188 IWM_SF_SCENARIO_BA_RESP,
3189 IWM_SF_SCENARIO_TX_RESP,
3193 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3194 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3196 /* smart FIFO default values */
3197 #define IWM_SF_W_MARK_SISO 4096
3198 #define IWM_SF_W_MARK_MIMO2 8192
3199 #define IWM_SF_W_MARK_MIMO3 6144
3200 #define IWM_SF_W_MARK_LEGACY 4096
3201 #define IWM_SF_W_MARK_SCAN 4096
3203 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3204 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3205 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3206 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3207 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3208 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3209 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3210 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3211 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3212 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3213 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3215 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3216 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3217 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3218 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3219 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3220 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3221 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3222 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3223 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3224 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3225 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3227 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3229 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3232 * Smart Fifo configuration command.
3233 * @state: smart fifo state, types listed in iwm_sf_state.
3234 * @watermark: Minimum allowed available free space in RXF for transient state.
3235 * @long_delay_timeouts: aging and idle timer values for each scenario
3236 * in long delay state.
3237 * @full_on_timeouts: timer values for each scenario in full on state.
3239 struct iwm_sf_cfg_cmd {
3241 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3242 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3243 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3244 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3251 * BEGIN mvm/fw-api-mac.h
3255 * The first MAC indices (starting from 0)
3256 * are available to the driver, AUX follows
3258 #define IWM_MAC_INDEX_AUX 4
3259 #define IWM_MAC_INDEX_MIN_DRIVER 0
3260 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3271 * enum iwm_mac_protection_flags - MAC context flags
3272 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3273 * this will require CCK RTS/CTS2self.
3274 * RTS/CTS will protect full burst time.
3275 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3276 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3277 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3279 enum iwm_mac_protection_flags {
3280 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3281 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3282 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3283 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3286 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3287 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3290 * enum iwm_mac_types - Supported MAC types
3291 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3292 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3293 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3294 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3295 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3296 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3297 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3298 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3299 * @IWM_FW_MAC_TYPE_GO: P2P GO
3300 * @IWM_FW_MAC_TYPE_TEST: ?
3301 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3303 enum iwm_mac_types {
3304 IWM_FW_MAC_TYPE_FIRST = 1,
3305 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3306 IWM_FW_MAC_TYPE_LISTENER,
3307 IWM_FW_MAC_TYPE_PIBSS,
3308 IWM_FW_MAC_TYPE_IBSS,
3309 IWM_FW_MAC_TYPE_BSS_STA,
3310 IWM_FW_MAC_TYPE_P2P_DEVICE,
3311 IWM_FW_MAC_TYPE_P2P_STA,
3313 IWM_FW_MAC_TYPE_TEST,
3314 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3315 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3318 * enum iwm_tsf_id - TSF hw timer ID
3319 * @IWM_TSF_ID_A: use TSF A
3320 * @IWM_TSF_ID_B: use TSF B
3321 * @IWM_TSF_ID_C: use TSF C
3322 * @IWM_TSF_ID_D: use TSF D
3323 * @IWM_NUM_TSF_IDS: number of TSF timers available
3330 IWM_NUM_TSF_IDS = 4,
3331 }; /* IWM_TSF_ID_API_E_VER_1 */
3334 * struct iwm_mac_data_ap - configuration data for AP MAC context
3335 * @beacon_time: beacon transmit time in system time
3336 * @beacon_tsf: beacon transmit time in TSF
3337 * @bi: beacon interval in TU
3338 * @bi_reciprocal: 2^32 / bi
3339 * @dtim_interval: dtim transmit time in TU
3340 * @dtim_reciprocal: 2^32 / dtim_interval
3341 * @mcast_qid: queue ID for multicast traffic
3342 * @beacon_template: beacon template ID
3344 struct iwm_mac_data_ap {
3345 uint32_t beacon_time;
3346 uint64_t beacon_tsf;
3348 uint32_t bi_reciprocal;
3349 uint32_t dtim_interval;
3350 uint32_t dtim_reciprocal;
3352 uint32_t beacon_template;
3353 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3356 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3357 * @beacon_time: beacon transmit time in system time
3358 * @beacon_tsf: beacon transmit time in TSF
3359 * @bi: beacon interval in TU
3360 * @bi_reciprocal: 2^32 / bi
3361 * @beacon_template: beacon template ID
3363 struct iwm_mac_data_ibss {
3364 uint32_t beacon_time;
3365 uint64_t beacon_tsf;
3367 uint32_t bi_reciprocal;
3368 uint32_t beacon_template;
3369 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3372 * struct iwm_mac_data_sta - configuration data for station MAC context
3373 * @is_assoc: 1 for associated state, 0 otherwise
3374 * @dtim_time: DTIM arrival time in system time
3375 * @dtim_tsf: DTIM arrival time in TSF
3376 * @bi: beacon interval in TU, applicable only when associated
3377 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3378 * @dtim_interval: DTIM interval in TU, applicable only when associated
3379 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3380 * @listen_interval: in beacon intervals, applicable only when associated
3381 * @assoc_id: unique ID assigned by the AP during association
3383 struct iwm_mac_data_sta {
3388 uint32_t bi_reciprocal;
3389 uint32_t dtim_interval;
3390 uint32_t dtim_reciprocal;
3391 uint32_t listen_interval;
3393 uint32_t assoc_beacon_arrive_time;
3394 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3397 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3398 * @ap: iwm_mac_data_ap struct with most config data
3399 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3400 * 0 indicates that there is no CT window.
3401 * @opp_ps_enabled: indicate that opportunistic PS allowed
3403 struct iwm_mac_data_go {
3404 struct iwm_mac_data_ap ap;
3406 uint32_t opp_ps_enabled;
3407 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3410 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3411 * @sta: iwm_mac_data_sta struct with most config data
3412 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3413 * 0 indicates that there is no CT window.
3415 struct iwm_mac_data_p2p_sta {
3416 struct iwm_mac_data_sta sta;
3418 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3421 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3422 * @stats_interval: interval in TU between statistics notifications to host.
3424 struct iwm_mac_data_pibss {
3425 uint32_t stats_interval;
3426 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3429 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3431 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3432 * other channels as well. This should be to true only in case that the
3433 * device is discoverable and there is an active GO. Note that setting this
3434 * field when not needed, will increase the number of interrupts and have
3435 * effect on the platform power, as this setting opens the Rx filters on
3438 struct iwm_mac_data_p2p_dev {
3439 uint32_t is_disc_extended;
3440 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3443 * enum iwm_mac_filter_flags - MAC context filter flags
3444 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3445 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3446 * control frames to the host
3447 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3448 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3449 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3450 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3451 * (in station mode when associated)
3452 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3453 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3454 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3456 enum iwm_mac_filter_flags {
3457 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3458 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3459 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3460 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3461 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3462 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3463 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3464 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3465 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3469 * enum iwm_mac_qos_flags - QoS flags
3470 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3471 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3472 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3475 enum iwm_mac_qos_flags {
3476 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3477 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3478 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3482 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3483 * @cw_min: Contention window, start value in numbers of slots.
3484 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3485 * @cw_max: Contention window, max value in numbers of slots.
3486 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3487 * @aifsn: Number of slots in Arbitration Interframe Space (before
3488 * performing random backoff timing prior to Tx). Device default 1.
3489 * @fifos_mask: FIFOs used by this MAC for this AC
3490 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3492 * One instance of this config struct for each of 4 EDCA access categories
3493 * in struct iwm_qosparam_cmd.
3495 * Device will automatically increase contention window by (2*CW) + 1 for each
3496 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3497 * value, to cap the CW value.
3505 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3508 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3509 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3510 * @id_and_color: ID and color of the MAC
3511 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3512 * @mac_type: one of IWM_FW_MAC_TYPE_*
3513 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3514 * @node_addr: MAC address
3515 * @bssid_addr: BSSID
3516 * @cck_rates: basic rates available for CCK
3517 * @ofdm_rates: basic rates available for OFDM
3518 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3519 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3520 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3521 * @filter_flags: combination of IWM_MAC_FILTER_*
3522 * @qos_flags: from IWM_MAC_QOS_FLG_*
3523 * @ac: one iwm_mac_qos configuration for each AC
3524 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3526 struct iwm_mac_ctx_cmd {
3527 /* COMMON_INDEX_HDR_API_S_VER_1 */
3528 uint32_t id_and_color;
3530 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3533 uint8_t node_addr[6];
3534 uint16_t reserved_for_node_addr;
3535 uint8_t bssid_addr[6];
3536 uint16_t reserved_for_bssid_addr;
3538 uint32_t ofdm_rates;
3539 uint32_t protection_flags;
3540 uint32_t cck_short_preamble;
3541 uint32_t short_slot;
3542 uint32_t filter_flags;
3543 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3545 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3546 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3548 struct iwm_mac_data_ap ap;
3549 struct iwm_mac_data_go go;
3550 struct iwm_mac_data_sta sta;
3551 struct iwm_mac_data_p2p_sta p2p_sta;
3552 struct iwm_mac_data_p2p_dev p2p_dev;
3553 struct iwm_mac_data_pibss pibss;
3554 struct iwm_mac_data_ibss ibss;
3556 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3558 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3562 return 0xFFFFFFFF / v;
3565 #define IWM_NONQOS_SEQ_GET 0x1
3566 #define IWM_NONQOS_SEQ_SET 0x2
3567 struct iwm_nonqos_seq_query_cmd {
3568 uint32_t get_set_flag;
3569 uint32_t mac_id_n_color;
3572 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3575 * END mvm/fw-api-mac.h
3579 * BEGIN mvm/fw-api-power.h
3582 /* Power Management Commands, Responses, Notifications */
3584 /* Radio LP RX Energy Threshold measured in dBm */
3585 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3586 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3587 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3590 * enum iwm_scan_flags - masks for power table command flags
3591 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3592 * receiver and transmitter. '0' - does not allow.
3593 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3594 * '1' Driver enables PM (use rest of parameters)
3595 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3596 * '1' PM could sleep over DTIM till listen Interval.
3597 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3598 * access categories are both delivery and trigger enabled.
3599 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3600 * PBW Snoozing enabled
3601 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3602 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3603 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3604 * detection enablement
3606 enum iwm_power_flags {
3607 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3608 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3609 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3610 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3611 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3612 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3613 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3614 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3617 #define IWM_POWER_VEC_SIZE 5
3620 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3621 * is used also with a new power API for device wide power settings.
3622 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3624 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3625 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3626 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3627 * set regardless of power scheme or current power state.
3628 * FW use this value also when PM is disabled.
3629 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3630 * PSM transition - legacy PM
3631 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3632 * PSM transition - legacy PM
3633 * @sleep_interval: not in use
3634 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3635 * is set. For example, if it is required to skip over
3636 * one DTIM, this value need to be set to 2 (DTIM periods).
3637 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3640 struct iwm_powertable_cmd {
3641 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3643 uint8_t keep_alive_seconds;
3644 uint8_t debug_flags;
3645 uint32_t rx_data_timeout;
3646 uint32_t tx_data_timeout;
3647 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3648 uint32_t skip_dtim_periods;
3649 uint32_t lprx_rssi_threshold;
3653 * enum iwm_device_power_flags - masks for device power command flags
3654 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3655 * receiver and transmitter. '0' - does not allow. This flag should be
3656 * always set to '1' unless one need to disable actual power down for debug
3658 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3659 * that power management is disabled. '0' Power management is enabled, one
3660 * of power schemes is applied.
3662 enum iwm_device_power_flags {
3663 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3664 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3668 * struct iwm_device_power_cmd - device wide power command.
3669 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3671 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3673 struct iwm_device_power_cmd {
3674 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3680 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3681 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3682 * @id_and_color: MAC contex identifier
3683 * @flags: Power table command flags from POWER_FLAGS_*
3684 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3685 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3686 * set regardless of power scheme or current power state.
3687 * FW use this value also when PM is disabled.
3688 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3689 * PSM transition - legacy PM
3690 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3691 * PSM transition - legacy PM
3692 * @sleep_interval: not in use
3693 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3694 * is set. For example, if it is required to skip over
3695 * one DTIM, this value need to be set to 2 (DTIM periods).
3696 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3697 * PSM transition - uAPSD
3698 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3699 * PSM transition - uAPSD
3700 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3702 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3703 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3704 * from the AP [msec]
3705 * @snooze_window: A window of time in which PBW snoozing insures that all
3706 * packets received. It is also the minimum time from last
3707 * received unicast RX packet, before client stops snoozing
3710 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3711 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3712 * each corresponding AC.
3713 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3714 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3716 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3717 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3718 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3719 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3720 * @limited_ps_threshold:
3722 struct iwm_mac_power_cmd {
3723 /* CONTEXT_DESC_API_T_VER_1 */
3724 uint32_t id_and_color;
3726 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3728 uint16_t keep_alive_seconds;
3729 uint32_t rx_data_timeout;
3730 uint32_t tx_data_timeout;
3731 uint32_t rx_data_timeout_uapsd;
3732 uint32_t tx_data_timeout_uapsd;
3733 uint8_t lprx_rssi_threshold;
3734 uint8_t skip_dtim_periods;
3735 uint16_t snooze_interval;
3736 uint16_t snooze_window;
3737 uint8_t snooze_step;
3739 uint8_t uapsd_ac_flags;
3740 uint8_t uapsd_max_sp;
3741 uint8_t heavy_tx_thld_packets;
3742 uint8_t heavy_rx_thld_packets;
3743 uint8_t heavy_tx_thld_percentage;
3744 uint8_t heavy_rx_thld_percentage;
3745 uint8_t limited_ps_threshold;
3750 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3751 * associated AP is identified as improperly implementing uAPSD protocol.
3752 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3753 * @sta_id: index of station in uCode's station table - associated AP ID in
3756 struct iwm_uapsd_misbehaving_ap_notif {
3759 uint8_t reserved[3];
3763 * struct iwm_beacon_filter_cmd
3764 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3765 * @id_and_color: MAC contex identifier
3766 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3767 * to driver if delta in Energy values calculated for this and last
3768 * passed beacon is greater than this threshold. Zero value means that
3769 * the Energy change is ignored for beacon filtering, and beacon will
3770 * not be forced to be sent to driver regardless of this delta. Typical
3772 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3773 * Send beacon to driver if delta in Energy values calculated for this
3774 * and last passed beacon is greater than this threshold. Zero value
3775 * means that the Energy change is ignored for beacon filtering while in
3776 * Roaming state, typical energy delta 1dB.
3777 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3778 * calculated for current beacon is less than the threshold, use
3779 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3780 * Threshold. Typical energy threshold is -72dBm.
3781 * @bf_temp_threshold: This threshold determines the type of temperature
3782 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3783 * If the current temperature is above this threshold - Fast filter
3784 * will be used, If the current temperature is below this threshold -
3785 * Slow filter will be used.
3786 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3787 * calculated for this and the last passed beacon is greater than this
3788 * threshold. Zero value means that the temperature change is ignored for
3789 * beacon filtering; beacons will not be forced to be sent to driver
3790 * regardless of whether its temperature has been changed.
3791 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3792 * calculated for this and the last passed beacon is greater than this
3793 * threshold. Zero value means that the temperature change is ignored for
3794 * beacon filtering; beacons will not be forced to be sent to driver
3795 * regardless of whether its temperature has been changed.
3796 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3797 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3798 * for a specific period of time. Units: Beacons.
3799 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3800 * for a longer period of time then this escape-timeout. Units: Beacons.
3801 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3803 struct iwm_beacon_filter_cmd {
3804 uint32_t bf_energy_delta;
3805 uint32_t bf_roaming_energy_delta;
3806 uint32_t bf_roaming_state;
3807 uint32_t bf_temp_threshold;
3808 uint32_t bf_temp_fast_filter;
3809 uint32_t bf_temp_slow_filter;
3810 uint32_t bf_enable_beacon_filter;
3811 uint32_t bf_debug_flag;
3812 uint32_t bf_escape_timer;
3813 uint32_t ba_escape_timer;
3814 uint32_t ba_enable_beacon_abort;
3817 /* Beacon filtering and beacon abort */
3818 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3819 #define IWM_BF_ENERGY_DELTA_MAX 255
3820 #define IWM_BF_ENERGY_DELTA_MIN 0
3822 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3823 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3824 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3826 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3827 #define IWM_BF_ROAMING_STATE_MAX 255
3828 #define IWM_BF_ROAMING_STATE_MIN 0
3830 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3831 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3832 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3834 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3835 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3836 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3838 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3839 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3840 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3842 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3844 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3846 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3847 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3848 #define IWM_BF_ESCAPE_TIMER_MIN 0
3850 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3851 #define IWM_BA_ESCAPE_TIMER_D3 9
3852 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3853 #define IWM_BA_ESCAPE_TIMER_MIN 0
3855 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3857 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3858 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3859 .bf_roaming_energy_delta = \
3860 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3861 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3862 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3863 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3864 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3865 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3866 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3867 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3870 * END mvm/fw-api-power.h
3874 * BEGIN mvm/fw-api-rs.h
3878 * These serve as indexes into
3879 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3880 * TODO: avoid overlap between legacy and HT rates
3883 IWM_RATE_1M_INDEX = 0,
3884 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3888 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3890 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3891 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3892 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3893 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3896 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3898 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3900 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3902 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3904 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3906 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3907 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3909 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3910 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3911 IWM_RATE_MCS_8_INDEX,
3912 IWM_RATE_MCS_9_INDEX,
3913 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3914 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3915 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3918 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3920 /* fw API values for legacy bit rates, both OFDM and CCK */
3922 IWM_RATE_6M_PLCP = 13,
3923 IWM_RATE_9M_PLCP = 15,
3924 IWM_RATE_12M_PLCP = 5,
3925 IWM_RATE_18M_PLCP = 7,
3926 IWM_RATE_24M_PLCP = 9,
3927 IWM_RATE_36M_PLCP = 11,
3928 IWM_RATE_48M_PLCP = 1,
3929 IWM_RATE_54M_PLCP = 3,
3930 IWM_RATE_1M_PLCP = 10,
3931 IWM_RATE_2M_PLCP = 20,
3932 IWM_RATE_5M_PLCP = 55,
3933 IWM_RATE_11M_PLCP = 110,
3934 IWM_RATE_INVM_PLCP = -1,
3938 * rate_n_flags bit fields
3940 * The 32-bit value has different layouts in the low 8 bites depending on the
3941 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3942 * for CCK and OFDM).
3944 * High-throughput (HT) rate format
3945 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3946 * Very High-throughput (VHT) rate format
3947 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3948 * Legacy OFDM rate format for bits 7:0
3949 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3950 * Legacy CCK rate format for bits 7:0:
3951 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3954 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3955 #define IWM_RATE_MCS_HT_POS 8
3956 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3958 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3959 #define IWM_RATE_MCS_CCK_POS 9
3960 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3962 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3963 #define IWM_RATE_MCS_VHT_POS 26
3964 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3968 * High-throughput (HT) rate format for bits 7:0
3970 * 2-0: MCS rate base
3979 * 4-3: 0) Single stream (SISO)
3980 * 1) Dual stream (MIMO)
3981 * 2) Triple stream (MIMO)
3982 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3983 * (bits 7-6 are zero)
3985 * Together the low 5 bits work out to the MCS index because we don't
3986 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3987 * streams and 16-23 have three streams. We could also support MCS 32
3988 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3990 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3991 #define IWM_RATE_HT_MCS_NSS_POS 3
3992 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3994 /* Bit 10: (1) Use Green Field preamble */
3995 #define IWM_RATE_HT_MCS_GF_POS 10
3996 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3998 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
4001 * Very High-throughput (VHT) rate format for bits 7:0
4003 * 3-0: VHT MCS (0-9)
4004 * 5-4: number of streams - 1:
4005 * 0) Single stream (SISO)
4006 * 1) Dual stream (MIMO)
4007 * 2) Triple stream (MIMO)
4010 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
4011 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
4012 #define IWM_RATE_VHT_MCS_NSS_POS 4
4013 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
4016 * Legacy OFDM rate format for bits 7:0
4028 * Legacy CCK rate format for bits 7:0:
4029 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
4037 #define IWM_RATE_LEGACY_RATE_MSK 0xff
4041 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
4042 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
4044 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
4045 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4046 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4047 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4048 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4049 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4051 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
4052 #define IWM_RATE_MCS_SGI_POS 13
4053 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
4055 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4056 #define IWM_RATE_MCS_ANT_POS 14
4057 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
4058 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
4059 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
4060 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
4061 IWM_RATE_MCS_ANT_B_MSK)
4062 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
4063 IWM_RATE_MCS_ANT_C_MSK)
4064 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
4065 #define IWM_RATE_MCS_ANT_NUM 3
4067 /* Bit 17-18: (0) SS, (1) SS*2 */
4068 #define IWM_RATE_MCS_STBC_POS 17
4069 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4071 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4072 #define IWM_RATE_MCS_BF_POS 19
4073 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4075 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
4076 #define IWM_RATE_MCS_ZLF_POS 20
4077 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4079 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4080 #define IWM_RATE_MCS_DUP_POS 24
4081 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
4083 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
4084 #define IWM_RATE_MCS_LDPC_POS 27
4085 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
4088 /* Link Quality definitions */
4090 /* # entries in rate scale table to support Tx retries */
4091 #define IWM_LQ_MAX_RETRY_NUM 16
4093 /* Link quality command flags bit fields */
4095 /* Bit 0: (0) Don't use RTS (1) Use RTS */
4096 #define IWM_LQ_FLAG_USE_RTS_POS 0
4097 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4099 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4100 #define IWM_LQ_FLAG_COLOR_POS 1
4101 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4103 /* Bit 4-5: Tx RTS BW Signalling
4104 * (0) No RTS BW signalling
4105 * (1) Static BW signalling
4106 * (2) Dynamic BW signalling
4108 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4109 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4110 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4111 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4113 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4114 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4116 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4117 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4120 * struct iwm_lq_cmd - link quality command
4121 * @sta_id: station to update
4122 * @control: not used
4123 * @flags: combination of IWM_LQ_FLAG_*
4124 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4126 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4127 * Should be ANT_[ABC]
4128 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4129 * @initial_rate_index: first index from rs_table per AC category
4130 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4131 * value of 100 is one usec. Range is 100 to 8000
4132 * @agg_disable_start_th: try-count threshold for starting aggregation.
4133 * If a frame has higher try-count, it should not be selected for
4134 * starting an aggregation sequence.
4135 * @agg_frame_cnt_limit: max frame count in an aggregation.
4137 * 1: no aggregation (one frame per aggregation)
4138 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4139 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4140 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4141 * @bf_params: beam forming params, currently not used
4147 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4150 uint8_t single_stream_ant_msk;
4151 uint8_t dual_stream_ant_msk;
4152 uint8_t initial_rate_index[IWM_AC_NUM];
4153 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4154 uint16_t agg_time_limit;
4155 uint8_t agg_disable_start_th;
4156 uint8_t agg_frame_cnt_limit;
4158 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4160 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4163 * END mvm/fw-api-rs.h
4167 * BEGIN mvm/fw-api-tx.h
4171 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4172 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4173 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4174 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4175 * Otherwise, use rate_n_flags from the TX command
4176 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4177 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4178 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4179 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4180 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4181 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4182 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4183 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4184 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4185 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4186 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4187 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4188 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4189 * Should be set for beacons and probe responses
4190 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4191 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4192 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4193 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4194 * Should be set for 26/30 length MAC headers
4195 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4196 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
4197 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4198 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4199 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4200 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4201 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4202 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4205 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4206 IWM_TX_CMD_FLG_ACK = (1 << 3),
4207 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4208 IWM_TX_CMD_FLG_BA = (1 << 5),
4209 IWM_TX_CMD_FLG_BAR = (1 << 6),
4210 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4211 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4212 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4213 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4214 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4215 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4216 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4217 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4218 IWM_TX_CMD_FLG_TSF = (1 << 16),
4219 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4220 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4221 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4222 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4223 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4224 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
4225 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4226 IWM_TX_CMD_FLG_DUR = (1 << 25),
4227 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4228 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4229 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4230 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4231 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4234 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4235 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4236 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4237 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4239 enum iwm_tx_pm_timeouts {
4240 IWM_PM_FRAME_NONE = 0,
4241 IWM_PM_FRAME_MGMT = 2,
4242 IWM_PM_FRAME_ASSOC = 3,
4246 * TX command security control
4248 #define IWM_TX_CMD_SEC_WEP 0x01
4249 #define IWM_TX_CMD_SEC_CCM 0x02
4250 #define IWM_TX_CMD_SEC_TKIP 0x03
4251 #define IWM_TX_CMD_SEC_EXT 0x04
4252 #define IWM_TX_CMD_SEC_MSK 0x07
4253 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4254 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4255 #define IWM_TX_CMD_SEC_KEY128 0x08
4257 /* TODO: how does these values are OK with only 16 bit variable??? */
4259 * TX command next frame info
4261 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4262 * bit 3 - immediate ACK required
4263 * bit 4 - rate is taken from STA table
4264 * bit 5 - frame belongs to BA stream
4265 * bit 6 - immediate BA response expected
4267 * bits 8:15 - Station ID
4270 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4271 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4272 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4273 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4274 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4275 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4276 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4277 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4278 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4281 * TX command Frame life time in us - to be written in pm_frame_timeout
4283 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4284 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4285 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4286 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4289 * TID for non QoS frames - to be written in tid_tspec
4291 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4294 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4296 #define IWM_DEFAULT_TX_RETRY 15
4297 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4298 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
4299 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4300 #define IWM_LOW_RETRY_LIMIT 7
4302 /* TODO: complete documentation for try_cnt and btkill_cnt */
4304 * struct iwm_tx_cmd - TX command struct to FW
4305 * ( IWM_TX_CMD = 0x1c )
4306 * @len: in bytes of the payload, see below for details
4307 * @next_frame_len: same as len, but for next frame (0 if not applicable)
4308 * Used for fragmentation and bursting, but not in 11n aggregation.
4309 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4310 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4311 * cleared. Combination of IWM_RATE_MCS_*
4312 * @sta_id: index of destination station in FW station table
4313 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4314 * @initial_rate_index: index into the rate table for initial TX attempt.
4315 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4316 * @key: security key
4317 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4318 * @life_time: frame life time (usecs??)
4319 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4320 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4321 * @dram_msb_ptr: upper bits of the scratch physical address
4322 * @rts_retry_limit: max attempts for RTS
4323 * @data_retry_limit: max attempts to send the data packet
4324 * @tid_spec: TID/tspec
4325 * @pm_frame_timeout: PM TX frame timeout
4326 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4327 * specified by HCCA protocol
4329 * The byte count (both len and next_frame_len) includes MAC header
4330 * (24/26/30/32 bytes)
4331 * + 2 bytes pad if 26/30 header size
4332 * + 8 byte IV for CCM or TKIP (not used for WEP)
4334 * + 8-byte MIC (not used for CCM/WEP)
4335 * It does not include post-MAC padding, i.e.,
4336 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4337 * Range of len: 14-2342 bytes.
4339 * After the struct fields the MAC header is placed, plus any padding,
4340 * and then the actial payload.
4344 uint16_t next_frame_len;
4350 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4351 uint32_t rate_n_flags;
4354 uint8_t initial_rate_index;
4357 uint16_t next_frame_flags;
4360 uint32_t dram_lsb_ptr;
4361 uint8_t dram_msb_ptr;
4362 uint8_t rts_retry_limit;
4363 uint8_t data_retry_limit;
4365 uint16_t pm_frame_timeout;
4366 uint16_t driver_txop;
4368 struct ieee80211_frame hdr[0];
4369 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4372 * TX response related data
4376 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4377 * @IWM_TX_STATUS_SUCCESS:
4378 * @IWM_TX_STATUS_DIRECT_DONE:
4379 * @IWM_TX_STATUS_POSTPONE_DELAY:
4380 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4381 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4382 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4383 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4384 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4385 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4386 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4387 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4388 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4389 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4390 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4391 * @IWM_TX_STATUS_FAIL_DEST_PS:
4392 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4393 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4394 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4395 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4396 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4397 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4398 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4399 * @IWM_TX_STATUS_FAIL_FW_DROP:
4400 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4402 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4404 * @IWM_TX_MODE_NO_BURST:
4405 * @IWM_TX_MODE_IN_BURST_SEQ:
4406 * @IWM_TX_MODE_FIRST_IN_BURST:
4407 * @IWM_TX_QUEUE_NUM_MSK:
4409 * Valid only if frame_count =1
4410 * TODO: complete documentation
4412 enum iwm_tx_status {
4413 IWM_TX_STATUS_MSK = 0x000000ff,
4414 IWM_TX_STATUS_SUCCESS = 0x01,
4415 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4417 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4418 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4419 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4420 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4421 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4423 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4424 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4425 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4426 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4427 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4428 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4429 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4430 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4431 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4432 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4433 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4434 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4435 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4436 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4437 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4438 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4439 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4440 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4441 IWM_TX_MODE_MSK = 0x00000f00,
4442 IWM_TX_MODE_NO_BURST = 0x00000000,
4443 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4444 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4445 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4446 IWM_TX_NARROW_BW_MSK = 0x00060000,
4447 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4448 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4449 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4453 * enum iwm_tx_agg_status - TX aggregation status
4454 * @IWM_AGG_TX_STATE_STATUS_MSK:
4455 * @IWM_AGG_TX_STATE_TRANSMITTED:
4456 * @IWM_AGG_TX_STATE_UNDERRUN:
4457 * @IWM_AGG_TX_STATE_BT_PRIO:
4458 * @IWM_AGG_TX_STATE_FEW_BYTES:
4459 * @IWM_AGG_TX_STATE_ABORT:
4460 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4461 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4462 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4463 * @IWM_AGG_TX_STATE_SCD_QUERY:
4464 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4465 * @IWM_AGG_TX_STATE_RESPONSE:
4466 * @IWM_AGG_TX_STATE_DUMP_TX:
4467 * @IWM_AGG_TX_STATE_DELAY_TX:
4468 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4469 * occur if tx failed for this frame when it was a member of a previous
4470 * aggregation block). If rate scaling is used, retry count indicates the
4471 * rate table entry used for all frames in the new agg.
4472 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4475 * TODO: complete documentation
4477 enum iwm_tx_agg_status {
4478 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4479 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4480 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4481 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4482 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4483 IWM_AGG_TX_STATE_ABORT = 0x008,
4484 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4485 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4486 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4487 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4488 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4489 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4490 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4491 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4492 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4493 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4496 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4497 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4498 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4501 * The mask below describes a status where we are absolutely sure that the MPDU
4502 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4503 * written the bytes to the TXE, but we know nothing about what the DSP did.
4505 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4506 IWM_AGG_TX_STATE_ABORT | \
4507 IWM_AGG_TX_STATE_SCD_QUERY)
4510 * IWM_REPLY_TX = 0x1c (response)
4512 * This response may be in one of two slightly different formats, indicated
4513 * by the frame_count field:
4515 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4516 * frame. Multiple attempts, at various bit rates, may have been made for
4519 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4520 * frames that used block-acknowledge. All frames were transmitted at
4521 * same rate. Rate scaling may have been used if first frame in this new
4522 * agg block failed in previous agg block(s).
4524 * Note that, for aggregation, ACK (block-ack) status is not delivered
4525 * here; block-ack has not been received by the time the device records
4527 * This status relates to reasons the tx might have been blocked or aborted
4528 * within the device, rather than whether it was received successfully by
4529 * the destination station.
4533 * struct iwm_agg_tx_status - per packet TX aggregation status
4534 * @status: enum iwm_tx_agg_status
4535 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4537 struct iwm_agg_tx_status {
4543 * definitions for initial rate index field
4544 * bits [3:0] initial rate index
4545 * bits [6:4] rate table color, used for the initial rate
4546 * bit-7 invalid rate indication
4548 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4549 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4550 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4552 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4553 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4556 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4557 * ( IWM_REPLY_TX = 0x1c )
4558 * @frame_count: 1 no aggregation, >1 aggregation
4559 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4560 * @failure_rts: num of failures due to unsuccessful RTS
4561 * @failure_frame: num failures due to no ACK (unused for agg)
4562 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4563 * Tx of all the batch. IWM_RATE_MCS_*
4564 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4565 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4567 * @pa_status: tx power info
4568 * @pa_integ_res_a: tx power info
4569 * @pa_integ_res_b: tx power info
4570 * @pa_integ_res_c: tx power info
4571 * @measurement_req_id: tx power info
4572 * @tfd_info: TFD information set by the FH
4573 * @seq_ctl: sequence control from the Tx cmd
4574 * @byte_cnt: byte count from the Tx cmd
4575 * @tlc_info: TLC rate info
4576 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4577 * @frame_ctrl: frame control
4578 * @status: for non-agg: frame status IWM_TX_STATUS_*
4579 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4580 * follow this one, up to frame_count.
4582 * After the array of statuses comes the SSN of the SCD. Look at
4583 * %iwm_mvm_get_scd_ssn for more details.
4585 struct iwm_mvm_tx_resp {
4586 uint8_t frame_count;
4587 uint8_t bt_kill_count;
4588 uint8_t failure_rts;
4589 uint8_t failure_frame;
4590 uint32_t initial_rate;
4591 uint16_t wireless_media_time;
4594 uint8_t pa_integ_res_a[3];
4595 uint8_t pa_integ_res_b[3];
4596 uint8_t pa_integ_res_c[3];
4597 uint16_t measurement_req_id;
4605 uint16_t frame_ctrl;
4607 struct iwm_agg_tx_status status;
4608 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4611 * struct iwm_mvm_ba_notif - notifies about reception of BA
4612 * ( IWM_BA_NOTIF = 0xc5 )
4613 * @sta_addr_lo32: lower 32 bits of the MAC address
4614 * @sta_addr_hi16: upper 16 bits of the MAC address
4615 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4616 * @tid: tid of the session
4618 * @bitmap: the bitmap of the BA notification as seen in the air
4619 * @scd_flow: the tx queue this BA relates to
4620 * @scd_ssn: the index of the last contiguously sent packet
4621 * @txed: number of Txed frames in this batch
4622 * @txed_2_done: number of Acked frames in this batch
4624 struct iwm_mvm_ba_notif {
4625 uint32_t sta_addr_lo32;
4626 uint16_t sta_addr_hi16;
4636 uint8_t txed_2_done;
4641 * struct iwm_mac_beacon_cmd - beacon template command
4642 * @tx: the tx commands associated with the beacon frame
4643 * @template_id: currently equal to the mac context id of the coresponding
4645 * @tim_idx: the offset of the tim IE in the beacon
4646 * @tim_size: the length of the tim IE
4647 * @frame: the template of the beacon frame
4649 struct iwm_mac_beacon_cmd {
4650 struct iwm_tx_cmd tx;
4651 uint32_t template_id;
4654 struct ieee80211_frame frame[0];
4657 struct iwm_beacon_notif {
4658 struct iwm_mvm_tx_resp beacon_notify_hdr;
4660 uint32_t ibss_mgr_status;
4664 * enum iwm_dump_control - dump (flush) control flags
4665 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4666 * and the TFD queues are empty.
4668 enum iwm_dump_control {
4669 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4673 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4674 * @queues_ctl: bitmap of queues to flush
4675 * @flush_ctl: control flags
4676 * @reserved: reserved
4678 struct iwm_tx_path_flush_cmd {
4679 uint32_t queues_ctl;
4682 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4685 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4686 * @tx_resp: the Tx response from the fw (agg or non-agg)
4688 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4689 * it can't know that everything will go well until the end of the AMPDU, it
4690 * can't know in advance the number of MPDUs that will be sent in the current
4691 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4692 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4693 * of the batch. This is why the SSN of the SCD is written at the end of the
4694 * whole struct at a variable offset. This function knows how to cope with the
4695 * variable offset and returns the SSN of the SCD.
4697 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4699 return le32_to_cpup((uint32_t *)&tx_resp->status +
4700 tx_resp->frame_count) & 0xfff;
4704 * END mvm/fw-api-tx.h
4708 * BEGIN mvm/fw-api-scan.h
4712 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4714 * @sta_id: station id
4716 * @scd_queue: scheduler queue to confiug
4717 * @enable: 1 queue enable, 0 queue disable
4718 * @aggregate: 1 aggregated queue, 0 otherwise
4719 * @tx_fifo: %enum iwm_mvm_tx_fifo
4720 * @window: BA window size
4721 * @ssn: SSN for the BA agreement
4723 struct iwm_scd_txq_cfg_cmd {
4734 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4737 * struct iwm_scd_txq_cfg_rsp
4738 * @token: taken from the command
4739 * @sta_id: station id from the command
4740 * @tid: tid from the command
4741 * @scd_queue: scd_queue from the command
4743 struct iwm_scd_txq_cfg_rsp {
4748 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4751 /* Scan Commands, Responses, Notifications */
4753 /* Masks for iwm_scan_channel.type flags */
4754 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4755 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1)
4757 /* Max number of IEs for direct SSID scans in a command */
4758 #define IWM_PROBE_OPTION_MAX 20
4761 * struct iwm_ssid_ie - directed scan network information element
4763 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4764 * selected by "type" bit field in struct iwm_scan_channel;
4765 * each channel may select different ssids from among the 20 entries.
4766 * SSID IEs get transmitted in reverse order of entry.
4768 struct iwm_ssid_ie {
4771 uint8_t ssid[IEEE80211_NWID_LEN];
4772 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4775 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4776 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4777 #define IWM_SCAN_MAX_PROFILES 11
4778 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4780 /* Default watchdog (in MS) for scheduled scan iteration */
4781 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4783 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4784 #define IWM_CAN_ABORT_STATUS 1
4786 #define IWM_FULL_SCAN_MULTIPLIER 5
4787 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4788 #define IWM_MAX_SCHED_SCAN_PLANS 2
4791 * iwm_scan_schedule_lmac - schedule of scan offload
4792 * @delay: delay between iterations, in seconds.
4793 * @iterations: num of scan iterations
4794 * @full_scan_mul: number of partial scans before each full scan
4796 struct iwm_scan_schedule_lmac {
4799 uint8_t full_scan_mul;
4800 } __packed; /* SCAN_SCHEDULE_API_S */
4803 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
4804 * @tx_flags: combination of TX_CMD_FLG_*
4805 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
4806 * cleared. Combination of RATE_MCS_*
4807 * @sta_id: index of destination station in FW station table
4808 * @reserved: for alignment and future use
4810 struct iwm_scan_req_tx_cmd {
4812 uint32_t rate_n_flags;
4814 uint8_t reserved[3];
4817 enum iwm_scan_channel_flags_lmac {
4818 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
4819 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
4823 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
4824 * @flags: bits 1-20: directed scan to i'th ssid
4825 * other bits &enum iwm_scan_channel_flags_lmac
4826 * @channel_number: channel number 1-13 etc
4827 * @iter_count: scan iteration on this channel
4828 * @iter_interval: interval in seconds between iterations on one channel
4830 struct iwm_scan_channel_cfg_lmac {
4832 uint16_t channel_num;
4833 uint16_t iter_count;
4834 uint32_t iter_interval;
4838 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
4839 * @offset: offset in the data block
4840 * @len: length of the segment
4842 struct iwm_scan_probe_segment {
4847 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
4848 * @mac_header: first (and common) part of the probe
4849 * @band_data: band specific data
4850 * @common_data: last (and common) part of the probe
4851 * @buf: raw data block
4853 struct iwm_scan_probe_req {
4854 struct iwm_scan_probe_segment mac_header;
4855 struct iwm_scan_probe_segment band_data[2];
4856 struct iwm_scan_probe_segment common_data;
4857 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
4860 enum iwm_scan_channel_flags {
4861 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
4862 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
4863 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
4866 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
4867 * @flags: enum iwm_scan_channel_flags
4868 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
4870 * 1 - EBS is disabled.
4871 * 2 - every second scan will be full scan(and so on).
4873 struct iwm_scan_channel_opt {
4875 uint16_t non_ebs_ratio;
4879 * iwm_mvm_lmac_scan_flags
4880 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
4881 * without filtering.
4882 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
4883 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
4884 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
4885 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
4886 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
4887 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
4888 * and DS parameter set IEs into probe requests.
4889 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
4891 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
4893 enum iwm_mvm_lmac_scan_flags {
4894 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
4895 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
4896 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
4897 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
4898 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
4899 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
4900 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
4901 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
4902 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
4905 enum iwm_scan_priority {
4906 IWM_SCAN_PRIORITY_LOW,
4907 IWM_SCAN_PRIORITY_MEDIUM,
4908 IWM_SCAN_PRIORITY_HIGH,
4912 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
4913 * @reserved1: for alignment and future use
4914 * @channel_num: num of channels to scan
4915 * @active-dwell: dwell time for active channels
4916 * @passive-dwell: dwell time for passive channels
4917 * @fragmented-dwell: dwell time for fragmented passive scan
4918 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
4919 * @reserved2: for alignment and future use
4920 * @rx_chain_selct: PHY_RX_CHAIN_* flags
4921 * @scan_flags: &enum iwm_mvm_lmac_scan_flags
4922 * @max_out_time: max time (in TU) to be out of associated channel
4923 * @suspend_time: pause scan this long (TUs) when returning to service channel
4924 * @flags: RXON flags
4925 * @filter_flags: RXON filter
4926 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
4927 * @direct_scan: list of SSIDs for directed active scan
4928 * @scan_prio: enum iwm_scan_priority
4929 * @iter_num: number of scan iterations
4930 * @delay: delay in seconds before first iteration
4931 * @schedule: two scheduling plans. The first one is finite, the second one can
4933 * @channel_opt: channel optimization options, for full and partial scan
4934 * @data: channel configuration and probe request packet.
4936 struct iwm_scan_req_lmac {
4937 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
4940 uint8_t active_dwell;
4941 uint8_t passive_dwell;
4942 uint8_t fragmented_dwell;
4943 uint8_t extended_dwell;
4945 uint16_t rx_chain_select;
4946 uint32_t scan_flags;
4947 uint32_t max_out_time;
4948 uint32_t suspend_time;
4949 /* RX_ON_FLAGS_API_S_VER_1 */
4951 uint32_t filter_flags;
4952 struct iwm_scan_req_tx_cmd tx_cmd[2];
4953 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4955 /* SCAN_REQ_PERIODIC_PARAMS_API_S */
4958 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
4959 struct iwm_scan_channel_opt channel_opt[2];
4964 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
4965 * @last_schedule_line: last schedule line executed (fast or regular)
4966 * @last_schedule_iteration: last scan iteration executed before scan abort
4967 * @status: enum iwm_scan_offload_complete_status
4968 * @ebs_status: EBS success status &enum iwm_scan_ebs_status
4969 * @time_after_last_iter; time in seconds elapsed after last iteration
4971 struct iwm_periodic_scan_complete {
4972 uint8_t last_schedule_line;
4973 uint8_t last_schedule_iteration;
4976 uint32_t time_after_last_iter;
4980 /* How many statistics are gathered for each channel */
4981 #define IWM_SCAN_RESULTS_STATISTICS 1
4984 * enum iwm_scan_complete_status - status codes for scan complete notifications
4985 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4986 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4987 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4988 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4989 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4990 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4991 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4992 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4993 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4994 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4996 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4998 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
5000 enum iwm_scan_complete_status {
5001 IWM_SCAN_COMP_STATUS_OK = 0x1,
5002 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
5003 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
5004 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
5005 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
5006 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
5007 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
5008 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
5009 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
5010 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
5011 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
5012 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
5016 * struct iwm_scan_results_notif - scan results for one channel
5017 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
5018 * @channel: which channel the results are from
5019 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
5020 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
5021 * @num_probe_not_sent: # of request that weren't sent due to not enough time
5022 * @duration: duration spent in channel, in usecs
5023 * @statistics: statistics gathered for this channel
5025 struct iwm_scan_results_notif {
5028 uint8_t probe_status;
5029 uint8_t num_probe_not_sent;
5031 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
5032 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
5034 enum iwm_scan_framework_client {
5035 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
5036 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
5037 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
5041 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
5042 * @ssid: MAC address to filter out
5043 * @reported_rssi: AP rssi reported to the host
5044 * @client_bitmap: clients ignore this entry - enum scan_framework_client
5046 struct iwm_scan_offload_blacklist {
5047 uint8_t ssid[IEEE80211_ADDR_LEN];
5048 uint8_t reported_rssi;
5049 uint8_t client_bitmap;
5052 enum iwm_scan_offload_network_type {
5053 IWM_NETWORK_TYPE_BSS = 1,
5054 IWM_NETWORK_TYPE_IBSS = 2,
5055 IWM_NETWORK_TYPE_ANY = 3,
5058 enum iwm_scan_offload_band_selection {
5059 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
5060 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
5061 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
5065 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
5066 * @ssid_index: index to ssid list in fixed part
5067 * @unicast_cipher: encryption olgorithm to match - bitmap
5068 * @aut_alg: authentication olgorithm to match - bitmap
5069 * @network_type: enum iwm_scan_offload_network_type
5070 * @band_selection: enum iwm_scan_offload_band_selection
5071 * @client_bitmap: clients waiting for match - enum scan_framework_client
5073 struct iwm_scan_offload_profile {
5075 uint8_t unicast_cipher;
5077 uint8_t network_type;
5078 uint8_t band_selection;
5079 uint8_t client_bitmap;
5080 uint8_t reserved[2];
5084 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
5085 * @blaclist: AP list to filter off from scan results
5086 * @profiles: profiles to search for match
5087 * @blacklist_len: length of blacklist
5088 * @num_profiles: num of profiles in the list
5089 * @match_notify: clients waiting for match found notification
5090 * @pass_match: clients waiting for the results
5091 * @active_clients: active clients bitmap - enum scan_framework_client
5092 * @any_beacon_notify: clients waiting for match notification without match
5094 struct iwm_scan_offload_profile_cfg {
5095 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
5096 uint8_t blacklist_len;
5097 uint8_t num_profiles;
5098 uint8_t match_notify;
5100 uint8_t active_clients;
5101 uint8_t any_beacon_notify;
5102 uint8_t reserved[2];
5105 enum iwm_scan_offload_complete_status {
5106 IWM_SCAN_OFFLOAD_COMPLETED = 1,
5107 IWM_SCAN_OFFLOAD_ABORTED = 2,
5111 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5112 * SCAN_COMPLETE_NTF_API_S_VER_3
5113 * @scanned_channels: number of channels scanned (and number of valid results)
5114 * @status: one of SCAN_COMP_STATUS_*
5115 * @bt_status: BT on/off status
5116 * @last_channel: last channel that was scanned
5117 * @tsf_low: TSF timer (lower half) in usecs
5118 * @tsf_high: TSF timer (higher half) in usecs
5119 * @results: an array of scan results, only "scanned_channels" of them are valid
5121 struct iwm_lmac_scan_complete_notif {
5122 uint8_t scanned_channels;
5125 uint8_t last_channel;
5128 struct iwm_scan_results_notif results[];
5133 * END mvm/fw-api-scan.h
5137 * BEGIN mvm/fw-api-sta.h
5142 /* The maximum of either of these cannot exceed 8, because we use an
5143 * 8-bit mask (see IWM_MVM_SCAN_MASK).
5145 #define IWM_MVM_MAX_UMAC_SCANS 8
5146 #define IWM_MVM_MAX_LMAC_SCANS 1
5148 enum iwm_scan_config_flags {
5149 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5150 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5151 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5152 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5153 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5154 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5155 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5156 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5157 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5158 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5159 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5160 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5161 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5162 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5163 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5164 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5165 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5166 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5168 /* Bits 26-31 are for num of channels in channel_array */
5169 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5172 enum iwm_scan_config_rates {
5173 /* OFDM basic rates */
5174 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5175 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5176 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5177 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5178 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5179 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5180 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5181 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5182 /* CCK basic rates */
5183 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5184 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5185 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5186 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5188 /* Bits 16-27 are for supported rates */
5189 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5192 enum iwm_channel_flags {
5193 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5194 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5195 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5196 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5200 * struct iwm_scan_config
5201 * @flags: enum scan_config_flags
5202 * @tx_chains: valid_tx antenna - ANT_* definitions
5203 * @rx_chains: valid_rx antenna - ANT_* definitions
5204 * @legacy_rates: default legacy rates - enum scan_config_rates
5205 * @out_of_channel_time: default max out of serving channel time
5206 * @suspend_time: default max suspend time
5207 * @dwell_active: default dwell time for active scan
5208 * @dwell_passive: default dwell time for passive scan
5209 * @dwell_fragmented: default dwell time for fragmented scan
5210 * @dwell_extended: default dwell time for channels 1, 6 and 11
5211 * @mac_addr: default mac address to be used in probes
5212 * @bcast_sta_id: the index of the station in the fw
5213 * @channel_flags: default channel flags - enum iwm_channel_flags
5214 * scan_config_channel_flag
5215 * @channel_array: default supported channels
5217 struct iwm_scan_config {
5221 uint32_t legacy_rates;
5222 uint32_t out_of_channel_time;
5223 uint32_t suspend_time;
5224 uint8_t dwell_active;
5225 uint8_t dwell_passive;
5226 uint8_t dwell_fragmented;
5227 uint8_t dwell_extended;
5228 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5229 uint8_t bcast_sta_id;
5230 uint8_t channel_flags;
5231 uint8_t channel_array[];
5232 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5235 * iwm_umac_scan_flags
5236 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5237 * can be preempted by other scan requests with higher priority.
5238 * The low priority scan will be resumed when the higher proirity scan is
5240 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5243 enum iwm_umac_scan_flags {
5244 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5245 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5248 enum iwm_umac_scan_uid_offsets {
5249 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5250 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5253 enum iwm_umac_scan_general_flags {
5254 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5255 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5256 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5257 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5258 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5259 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5260 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5261 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5262 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5263 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5264 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5268 * struct iwm_scan_channel_cfg_umac
5269 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5270 * @channel_num: channel number 1-13 etc.
5271 * @iter_count: repetition count for the channel.
5272 * @iter_interval: interval between two scan iterations on one channel.
5274 struct iwm_scan_channel_cfg_umac {
5276 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5278 uint8_t channel_num;
5280 uint16_t iter_interval;
5281 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5284 * struct iwm_scan_umac_schedule
5285 * @interval: interval in seconds between scan iterations
5286 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5287 * @reserved: for alignment and future use
5289 struct iwm_scan_umac_schedule {
5293 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5296 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5297 * parameters following channels configuration array.
5298 * @schedule: two scheduling plans.
5299 * @delay: delay in TUs before starting the first scan iteration
5300 * @reserved: for future use and alignment
5301 * @preq: probe request with IEs blocks
5302 * @direct_scan: list of SSIDs for directed active scan
5304 struct iwm_scan_req_umac_tail {
5305 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5306 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5309 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5310 struct iwm_scan_probe_req preq;
5311 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5315 * struct iwm_scan_req_umac
5316 * @flags: &enum iwm_umac_scan_flags
5317 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5318 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5319 * @general_flags: &enum iwm_umac_scan_general_flags
5320 * @extended_dwell: dwell time for channels 1, 6 and 11
5321 * @active_dwell: dwell time for active scan
5322 * @passive_dwell: dwell time for passive scan
5323 * @fragmented_dwell: dwell time for fragmented passive scan
5324 * @max_out_time: max out of serving channel time
5325 * @suspend_time: max suspend time
5326 * @scan_priority: scan internal prioritization &enum iwm_scan_priority
5327 * @channel_flags: &enum iwm_scan_channel_flags
5328 * @n_channels: num of channels in scan request
5329 * @reserved: for future use and alignment
5330 * @data: &struct iwm_scan_channel_cfg_umac and
5331 * &struct iwm_scan_req_umac_tail
5333 struct iwm_scan_req_umac {
5336 uint32_t ooc_priority;
5337 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5338 uint32_t general_flags;
5339 uint8_t extended_dwell;
5340 uint8_t active_dwell;
5341 uint8_t passive_dwell;
5342 uint8_t fragmented_dwell;
5343 uint32_t max_out_time;
5344 uint32_t suspend_time;
5345 uint32_t scan_priority;
5346 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5347 uint8_t channel_flags;
5351 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5354 * struct iwm_umac_scan_abort
5355 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5358 struct iwm_umac_scan_abort {
5361 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5364 * struct iwm_umac_scan_complete
5365 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5366 * @last_schedule: last scheduling line
5367 * @last_iter: last scan iteration number
5368 * @scan status: &enum iwm_scan_offload_complete_status
5369 * @ebs_status: &enum iwm_scan_ebs_status
5370 * @time_from_last_iter: time elapsed from last iteration
5371 * @reserved: for future use
5373 struct iwm_umac_scan_complete {
5375 uint8_t last_schedule;
5379 uint32_t time_from_last_iter;
5381 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5383 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5385 * struct iwm_scan_offload_profile_match - match information
5386 * @bssid: matched bssid
5387 * @channel: channel where the match occurred
5389 * @matching_feature:
5390 * @matching_channels: bitmap of channels that matched, referencing
5391 * the channels passed in tue scan offload request
5393 struct iwm_scan_offload_profile_match {
5394 uint8_t bssid[IEEE80211_ADDR_LEN];
5398 uint8_t matching_feature;
5399 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5400 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5403 * struct iwm_scan_offload_profiles_query - match results query response
5404 * @matched_profiles: bitmap of matched profiles, referencing the
5405 * matches passed in the scan offload request
5406 * @last_scan_age: age of the last offloaded scan
5407 * @n_scans_done: number of offloaded scans done
5408 * @gp2_d0u: GP2 when D0U occurred
5409 * @gp2_invoked: GP2 when scan offload was invoked
5410 * @resume_while_scanning: not used
5411 * @self_recovery: obsolete
5412 * @reserved: reserved
5413 * @matches: array of match information, one for each match
5415 struct iwm_scan_offload_profiles_query {
5416 uint32_t matched_profiles;
5417 uint32_t last_scan_age;
5418 uint32_t n_scans_done;
5420 uint32_t gp2_invoked;
5421 uint8_t resume_while_scanning;
5422 uint8_t self_recovery;
5424 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5425 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5428 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5429 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5430 * @scanned_channels: number of channels scanned and number of valid elements in
5432 * @status: one of SCAN_COMP_STATUS_*
5433 * @bt_status: BT on/off status
5434 * @last_channel: last channel that was scanned
5435 * @tsf_low: TSF timer (lower half) in usecs
5436 * @tsf_high: TSF timer (higher half) in usecs
5437 * @results: array of scan results, only "scanned_channels" of them are valid
5439 struct iwm_umac_scan_iter_complete_notif {
5441 uint8_t scanned_channels;
5444 uint8_t last_channel;
5447 struct iwm_scan_results_notif results[];
5448 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5450 /* Please keep this enum *SORTED* by hex value.
5451 * Needed for binary search, otherwise a warning will be triggered.
5453 enum iwm_scan_subcmd_ids {
5454 IWM_GSCAN_START_CMD = 0x0,
5455 IWM_GSCAN_STOP_CMD = 0x1,
5456 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5457 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5458 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5459 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5460 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5461 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5462 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5468 * enum iwm_sta_flags - flags for the ADD_STA host command
5469 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5470 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5471 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5472 * @IWM_STA_FLG_PS: set if STA is in Power Save
5473 * @IWM_STA_FLG_INVALID: set if STA is invalid
5474 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5475 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5476 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5477 * @IWM_STA_FLG_PAN: STA is for PAN interface
5478 * @IWM_STA_FLG_CLASS_AUTH:
5479 * @IWM_STA_FLG_CLASS_ASSOC:
5480 * @IWM_STA_FLG_CLASS_MIMO_PROT:
5481 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5482 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5483 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5484 * initialised by driver and can be updated by fw upon reception of
5485 * action frames that can change the channel width. When cleared the fw
5486 * will send all the frames in 20MHz even when FAT channel is requested.
5487 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5488 * driver and can be updated by fw upon reception of action frames.
5489 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5491 enum iwm_sta_flags {
5492 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5493 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
5495 IWM_STA_FLG_DISABLE_TX = (1 << 4),
5497 IWM_STA_FLG_PS = (1 << 8),
5498 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5499 IWM_STA_FLG_PAN = (1 << 13),
5500 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5501 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5502 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
5504 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5505 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5506 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5507 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5508 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5509 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5510 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5511 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5512 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5513 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5515 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5516 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5517 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5518 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5519 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5520 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5522 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5523 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5524 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5525 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5526 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
5528 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5529 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5530 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5531 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5535 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
5536 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5537 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5538 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5539 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5540 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5541 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5542 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5543 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5544 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5545 * station info array (1 - n 1X mode)
5546 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5547 * @IWM_STA_KEY_NOT_VALID: key is invalid
5548 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5549 * @IWM_STA_KEY_MULTICAST: set for multical key
5550 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5552 enum iwm_sta_key_flag {
5553 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5554 IWM_STA_KEY_FLG_WEP = (1 << 0),
5555 IWM_STA_KEY_FLG_CCM = (2 << 0),
5556 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5557 IWM_STA_KEY_FLG_EXT = (4 << 0),
5558 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5559 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5560 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
5562 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5563 IWM_STA_KEY_FLG_KEYID_POS = 8,
5564 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5565 IWM_STA_KEY_NOT_VALID = (1 << 11),
5566 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5567 IWM_STA_KEY_MULTICAST = (1 << 14),
5568 IWM_STA_KEY_MFP = (1 << 15),
5572 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5573 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5574 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5575 * @IWM_STA_MODIFY_TX_RATE: unused
5576 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5577 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5578 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5579 * @IWM_STA_MODIFY_PROT_TH:
5580 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5582 enum iwm_sta_modify_flag {
5583 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5584 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5585 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5586 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5587 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5588 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5589 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5590 IWM_STA_MODIFY_QUEUES = (1 << 7),
5593 #define IWM_STA_MODE_MODIFY 1
5596 * enum iwm_sta_sleep_flag - type of sleep of the station
5597 * @IWM_STA_SLEEP_STATE_AWAKE:
5598 * @IWM_STA_SLEEP_STATE_PS_POLL:
5599 * @IWM_STA_SLEEP_STATE_UAPSD:
5600 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5601 * (last) released frame
5603 enum iwm_sta_sleep_flag {
5604 IWM_STA_SLEEP_STATE_AWAKE = 0,
5605 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5606 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5607 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5610 /* STA ID and color bits definitions */
5611 #define IWM_STA_ID_SEED (0x0f)
5612 #define IWM_STA_ID_POS (0)
5613 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5615 #define IWM_STA_COLOR_SEED (0x7)
5616 #define IWM_STA_COLOR_POS (4)
5617 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5619 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5620 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5621 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5622 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5624 #define IWM_STA_KEY_MAX_NUM (16)
5625 #define IWM_STA_KEY_IDX_INVALID (0xff)
5626 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5627 #define IWM_MAX_GLOBAL_KEYS (4)
5628 #define IWM_STA_KEY_LEN_WEP40 (5)
5629 #define IWM_STA_KEY_LEN_WEP104 (13)
5632 * struct iwm_mvm_keyinfo - key information
5633 * @key_flags: type %iwm_sta_key_flag
5634 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5635 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5636 * @key_offset: key offset in the fw's key table
5637 * @key: 16-byte unicast decryption key
5638 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5639 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5640 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5642 struct iwm_mvm_keyinfo {
5644 uint8_t tkip_rx_tsc_byte2;
5646 uint16_t tkip_rx_ttak[5];
5650 uint64_t tx_secur_seq_cnt;
5651 uint64_t hw_tkip_mic_rx_key;
5652 uint64_t hw_tkip_mic_tx_key;
5655 #define IWM_ADD_STA_STATUS_MASK 0xFF
5656 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5657 #define IWM_ADD_STA_BAID_MASK 0x7F00
5658 #define IWM_ADD_STA_BAID_SHIFT 8
5661 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
5662 * ( REPLY_ADD_STA = 0x18 )
5663 * @add_modify: 1: modify existing, 0: add new station
5665 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5666 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5667 * @mac_id_n_color: the Mac context this station belongs to
5668 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5669 * @sta_id: index of station in uCode's station table
5670 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5671 * alone. 1 - modify, 0 - don't change.
5672 * @station_flags: look at %iwm_sta_flags
5673 * @station_flags_msk: what of %station_flags have changed
5674 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5675 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5676 * add_immediate_ba_ssn.
5677 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5678 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5679 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5680 * add_immediate_ba_tid.
5681 * @sleep_tx_count: number of packets to transmit to station even though it is
5682 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5683 * keeps track of STA sleep state.
5684 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5685 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5687 * @beamform_flags: beam forming controls
5688 * @tfd_queue_msk: tfd queues used by this station
5690 * The device contains an internal table of per-station information, with info
5691 * on security keys, aggregation parameters, and Tx rates for initial Tx
5692 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5694 * ADD_STA sets up the table entry for one station, either creating a new
5695 * entry, or modifying a pre-existing one.
5697 struct iwm_mvm_add_sta_cmd_v7 {
5700 uint16_t tid_disable_tx;
5701 uint32_t mac_id_n_color;
5702 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5705 uint8_t modify_mask;
5707 uint32_t station_flags;
5708 uint32_t station_flags_msk;
5709 uint8_t add_immediate_ba_tid;
5710 uint8_t remove_immediate_ba_tid;
5711 uint16_t add_immediate_ba_ssn;
5712 uint16_t sleep_tx_count;
5713 uint16_t sleep_state_flags;
5715 uint16_t beamform_flags;
5716 uint32_t tfd_queue_msk;
5717 } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5720 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5721 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5722 * @sta_id: index of station in uCode's station table
5723 * @key_offset: key offset in key storage
5724 * @key_flags: type %iwm_sta_key_flag
5725 * @key: key material data
5726 * @key2: key material data
5727 * @rx_secur_seq_cnt: RX security sequence counter for the key
5728 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5729 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5731 struct iwm_mvm_add_sta_key_cmd {
5737 uint8_t rx_secur_seq_cnt[16];
5738 uint8_t tkip_rx_tsc_byte2;
5740 uint16_t tkip_rx_ttak[5];
5741 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5744 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5745 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5746 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5747 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5748 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5749 * that doesn't exist.
5751 enum iwm_mvm_add_sta_rsp_status {
5752 IWM_ADD_STA_SUCCESS = 0x1,
5753 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5754 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5755 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5759 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5760 * ( IWM_REMOVE_STA = 0x19 )
5761 * @sta_id: the station id of the station to be removed
5763 struct iwm_mvm_rm_sta_cmd {
5765 uint8_t reserved[3];
5766 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5769 * struct iwm_mvm_mgmt_mcast_key_cmd
5770 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5771 * @ctrl_flags: %iwm_sta_key_flag
5773 * @K1: IGTK master key
5775 * @sta_id: station ID that support IGTK
5777 * @receive_seq_cnt: initial RSC/PN needed for replay check
5779 struct iwm_mvm_mgmt_mcast_key_cmd {
5780 uint32_t ctrl_flags;
5786 uint64_t receive_seq_cnt;
5787 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5789 struct iwm_mvm_wep_key {
5794 uint8_t reserved2[3];
5798 struct iwm_mvm_wep_key_cmd {
5799 uint32_t mac_id_n_color;
5801 uint8_t decryption_type;
5804 struct iwm_mvm_wep_key wep_key[0];
5805 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5808 * END mvm/fw-api-sta.h
5815 enum iwm_bt_coex_mode {
5816 IWM_BT_COEX_DISABLE = 0x0,
5817 IWM_BT_COEX_NW = 0x1,
5818 IWM_BT_COEX_BT = 0x2,
5819 IWM_BT_COEX_WIFI = 0x3,
5820 }; /* BT_COEX_MODES_E */
5822 enum iwm_bt_coex_enabled_modules {
5823 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
5824 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
5825 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
5826 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
5827 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
5828 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
5831 * struct iwm_bt_coex_cmd - bt coex configuration command
5832 * @mode: enum %iwm_bt_coex_mode
5833 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
5835 * The structure is used for the BT_COEX command.
5837 struct iwm_bt_coex_cmd {
5839 uint32_t enabled_modules;
5840 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
5844 * Location Aware Regulatory (LAR) API - MCC updates
5848 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
5849 * regulatory profile according to the given MCC (Mobile Country Code).
5850 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5851 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5852 * MCC in the cmd response will be the relevant MCC in the NVM.
5853 * @mcc: given mobile country code
5854 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5855 * @reserved: reserved for alignment
5857 struct iwm_mcc_update_cmd_v1 {
5861 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
5864 * struct iwm_mcc_update_cmd - Request the device to update geographic
5865 * regulatory profile according to the given MCC (Mobile Country Code).
5866 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5867 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5868 * MCC in the cmd response will be the relevant MCC in the NVM.
5869 * @mcc: given mobile country code
5870 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5871 * @reserved: reserved for alignment
5872 * @key: integrity key for MCC API OEM testing
5873 * @reserved2: reserved
5875 struct iwm_mcc_update_cmd {
5880 uint32_t reserved2[5];
5881 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
5884 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
5885 * Contains the new channel control profile map, if changed, and the new MCC
5886 * (mobile country code).
5887 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5888 * @status: see &enum iwm_mcc_update_status
5889 * @mcc: the new applied MCC
5890 * @cap: capabilities for all channels which matches the MCC
5891 * @source_id: the MCC source, see iwm_mcc_source
5892 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5893 * channels, depending on platform)
5894 * @channels: channel control data map, DWORD for each channel. Only the first
5897 struct iwm_mcc_update_resp_v1 {
5902 uint32_t n_channels;
5903 uint32_t channels[0];
5904 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
5907 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
5908 * Contains the new channel control profile map, if changed, and the new MCC
5909 * (mobile country code).
5910 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5911 * @status: see &enum iwm_mcc_update_status
5912 * @mcc: the new applied MCC
5913 * @cap: capabilities for all channels which matches the MCC
5914 * @source_id: the MCC source, see iwm_mcc_source
5915 * @time: time elapsed from the MCC test start (in 30 seconds TU)
5916 * @reserved: reserved.
5917 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5918 * channels, depending on platform)
5919 * @channels: channel control data map, DWORD for each channel. Only the first
5922 struct iwm_mcc_update_resp {
5929 uint32_t n_channels;
5930 uint32_t channels[0];
5931 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
5934 * struct iwm_mcc_chub_notif - chub notifies of mcc change
5935 * (MCC_CHUB_UPDATE_CMD = 0xc9)
5936 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
5937 * the cellular and connectivity cores that gets updates of the mcc, and
5938 * notifies the ucode directly of any mcc change.
5939 * The ucode requests the driver to request the device to update geographic
5940 * regulatory profile according to the given MCC (Mobile Country Code).
5941 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5942 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5943 * MCC in the cmd response will be the relevant MCC in the NVM.
5944 * @mcc: given mobile country code
5945 * @source_id: identity of the change originator, see iwm_mcc_source
5946 * @reserved1: reserved for alignment
5948 struct iwm_mcc_chub_notif {
5952 } __packed; /* LAR_MCC_NOTIFY_S */
5954 enum iwm_mcc_update_status {
5955 IWM_MCC_RESP_NEW_CHAN_PROFILE,
5956 IWM_MCC_RESP_SAME_CHAN_PROFILE,
5957 IWM_MCC_RESP_INVALID,
5958 IWM_MCC_RESP_NVM_DISABLED,
5959 IWM_MCC_RESP_ILLEGAL,
5960 IWM_MCC_RESP_LOW_PRIORITY,
5961 IWM_MCC_RESP_TEST_MODE_ACTIVE,
5962 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
5963 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
5966 enum iwm_mcc_source {
5967 IWM_MCC_SOURCE_OLD_FW = 0,
5968 IWM_MCC_SOURCE_ME = 1,
5969 IWM_MCC_SOURCE_BIOS = 2,
5970 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
5971 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
5972 IWM_MCC_SOURCE_WIFI = 5,
5973 IWM_MCC_SOURCE_RESERVED = 6,
5974 IWM_MCC_SOURCE_DEFAULT = 7,
5975 IWM_MCC_SOURCE_UNINITIALIZED = 8,
5976 IWM_MCC_SOURCE_MCC_API = 9,
5977 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
5978 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
5982 * Some cherry-picked definitions
5985 #define IWM_FRAME_LIMIT 64
5988 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
5989 * As the firmware is slowly running out of command IDs and grouping of
5990 * commands is desirable anyway, the firmware is extending the command
5991 * header from 4 bytes to 8 bytes to introduce a group (in place of the
5992 * former flags field, since that's always 0 on commands and thus can
5993 * be easily used to distinguish between the two).
5995 * These functions retrieve specific information from the id field in
5996 * the iwm_host_cmd struct which contains the command id, the group id,
5997 * and the version of the command.
5999 static inline uint8_t
6000 iwm_cmd_opcode(uint32_t cmdid)
6002 return cmdid & 0xff;
6005 static inline uint8_t
6006 iwm_cmd_groupid(uint32_t cmdid)
6008 return ((cmdid & 0Xff00) >> 8);
6011 static inline uint8_t
6012 iwm_cmd_version(uint32_t cmdid)
6014 return ((cmdid & 0xff0000) >> 16);
6017 static inline uint32_t
6018 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
6020 return opcode + (groupid << 8) + (version << 16);
6023 /* make uint16_t wide id out of uint8_t group and opcode */
6024 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
6026 /* due to the conversion, this group is special */
6027 #define IWM_ALWAYS_LONG_GROUP 1
6029 struct iwm_cmd_header {
6036 struct iwm_cmd_header_wide {
6046 enum iwm_power_scheme {
6047 IWM_POWER_SCHEME_CAM = 1,
6048 IWM_POWER_SCHEME_BPS,
6052 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
6053 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6054 #define IWM_CMD_FAILED_MSK 0x40
6057 * struct iwm_device_cmd
6059 * For allocation of the command and tx queues, this establishes the overall
6060 * size of the largest command we send to uCode, except for commands that
6061 * aren't fully copied and use other TFD space.
6063 struct iwm_device_cmd {
6066 struct iwm_cmd_header hdr;
6067 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
6070 struct iwm_cmd_header_wide hdr_wide;
6071 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
6072 sizeof(struct iwm_cmd_header_wide) +
6073 sizeof(struct iwm_cmd_header)];
6078 struct iwm_rx_packet {
6080 * The first 4 bytes of the RX frame header contain both the RX frame
6081 * size and some flags.
6083 * 31: flag flush RB request
6084 * 30: flag ignore TC (terminal counter) request
6085 * 29: flag fast IRQ request
6087 * 13-00: RX frame size
6089 uint32_t len_n_flags;
6090 struct iwm_cmd_header hdr;
6094 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6096 static inline uint32_t
6097 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6100 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6103 static inline uint32_t
6104 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
6107 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6111 #define IWM_MIN_DBM -100
6112 #define IWM_MAX_DBM -33 /* realistic guess */
6114 #define IWM_READ(sc, reg) \
6115 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6117 #define IWM_WRITE(sc, reg, val) \
6118 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6120 #define IWM_WRITE_1(sc, reg, val) \
6121 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6123 #define IWM_SETBITS(sc, reg, mask) \
6124 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
6126 #define IWM_CLRBITS(sc, reg, mask) \
6127 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
6129 #define IWM_BARRIER_WRITE(sc) \
6130 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6131 BUS_SPACE_BARRIER_WRITE)
6133 #define IWM_BARRIER_READ_WRITE(sc) \
6134 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6135 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
6137 #endif /* __IF_IWM_REG_H__ */