1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
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63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
77 * CSR (control and status registers)
79 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * whenever platform supplies power to device, even when device is in
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
84 * Use iwl_write32() and iwl_read32() family to access these registers;
85 * these provide simple PCI bus access, without waking up the MAC.
86 * Do not use iwl_write_direct32() family for these registers;
87 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
88 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
91 * NOTE: Device does need to be awake in order to read this memory
92 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101 #define IWM_CSR_GP_CNTRL (0x024)
103 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
104 #define IWM_CSR_INT_PERIODIC_REG (0x005)
107 * Hardware revision info
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
114 #define IWM_CSR_HW_REV (0x028)
117 * EEPROM and OTP (one-time-programmable) memory reads
119 * NOTE: Device must be awake, initialized via apm_ops.init(),
122 #define IWM_CSR_EEPROM_REG (0x02c)
123 #define IWM_CSR_EEPROM_GP (0x030)
124 #define IWM_CSR_OTP_GP_REG (0x034)
126 #define IWM_CSR_GIO_REG (0x03C)
127 #define IWM_CSR_GP_UCODE_REG (0x048)
128 #define IWM_CSR_GP_DRIVER_REG (0x050)
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
132 * SET/CLR registers set/clear bit(s) if "1" is written.
134 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
139 #define IWM_CSR_MBOX_SET_REG (0x088)
140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
142 #define IWM_CSR_LED_REG (0x094)
143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
147 /* GIO Chicken Bits (PCI Express bus link power management) */
148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
150 /* Analog phase-lock-loop configuration */
151 #define IWM_CSR_ANA_PLL_CFG (0x20c)
154 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
155 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
156 * See also IWM_CSR_HW_REV register.
158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
159 * 1-0: "Dash" (-) value, as in C-1, etc.
161 #define IWM_CSR_HW_REV_WA_REG (0x22C)
163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
166 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
178 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
179 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
180 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
181 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
194 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
195 * acknowledged (reset) by host writing "1" to flagged bits. */
196 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
197 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
198 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
200 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
201 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
202 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
203 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
204 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
205 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
208 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
209 IWM_CSR_INT_BIT_HW_ERR | \
210 IWM_CSR_INT_BIT_FH_TX | \
211 IWM_CSR_INT_BIT_SW_ERR | \
212 IWM_CSR_INT_BIT_RF_KILL | \
213 IWM_CSR_INT_BIT_SW_RX | \
214 IWM_CSR_INT_BIT_WAKEUP | \
215 IWM_CSR_INT_BIT_ALIVE | \
216 IWM_CSR_INT_BIT_RX_PERIODIC)
218 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
219 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
220 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
221 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
223 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
226 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
227 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
228 IWM_CSR_FH_INT_BIT_RX_CHNL0)
230 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
231 IWM_CSR_FH_INT_BIT_TX_CHNL0)
234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
247 * GP (general purpose) CONTROL REGISTER
250 * Indicates state of (platform's) hardware RF-Kill switch
251 * 26-24: POWER_SAVE_TYPE
252 * Indicates current power-saving mode:
253 * 000 -- No power saving
254 * 001 -- MAC power-down
255 * 010 -- PHY (radio) power-down
258 * Indicates current system configuration, reflecting pins on chip
259 * as forced high/low by device circuit board.
261 * Indicates MAC is entering a power-saving sleep power-down.
262 * Not a good time to access device-internal resources.
264 * Host sets this to request and maintain MAC wakeup, to allow host
265 * access to device-internal resources. Host must wait for
266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
269 * Host sets this to put device into fully operational D0 power mode.
270 * Host resets this after SW_RESET to put device into low power mode.
272 * Indicates MAC (ucode processor, etc.) is powered up and can run.
273 * Internal resources are accessible.
274 * NOTE: This does not indicate that the processor is actually running.
275 * NOTE: This does not indicate that device has completed
276 * init or post-power-down restore of internal SRAM memory.
277 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
278 * SRAM is restored and uCode is in normal operation mode.
279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
280 * do not need to save/restore it.
281 * NOTE: After device reset, this bit remains "0" until host sets
284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
292 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
304 IWM_SILICON_A_STEP = 0,
310 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
311 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
312 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
313 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
314 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
315 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
316 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
317 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
318 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
319 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
320 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
321 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
322 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
323 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
324 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
325 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
326 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
327 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
330 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
331 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
332 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
333 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
336 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
337 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
338 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
339 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
341 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
343 /* One-time-programmable memory general purpose reg */
344 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
345 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
346 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
347 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
350 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
351 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
352 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
353 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
354 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
358 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
361 * UCODE-DRIVER GP (general purpose) mailbox register 1
362 * Host driver and uCode write and/or read this register to communicate with
366 * Host sets this to request permanent halt of uCode, same as
367 * sending CARD_STATE command with "halt" bit set.
369 * Host sets this to request exit from CT_KILL state, i.e. host thinks
370 * device temperature is low enough to continue normal operation.
372 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
373 * to release uCode to clear all Tx and command queues, enter
374 * unassociated mode, and power down.
375 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
377 * Host sets this when issuing CARD_STATE command to request
380 * uCode sets this when preparing a power-saving power-down.
381 * uCode resets this when power-up is complete and SRAM is sane.
382 * NOTE: device saves internal SRAM data to host when powering down,
383 * and must restore this data after powering back up.
384 * MAC_SLEEP is the best indication that restore is complete.
385 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
386 * do not need to save/restore it.
388 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
389 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
390 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
391 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
392 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
399 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
400 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
402 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
404 /* GIO Chicken Bits (PCI Express bus link power management) */
405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
406 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
409 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
410 #define IWM_CSR_LED_REG_TURN_ON (0x60)
411 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
414 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
417 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
420 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
421 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
422 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
424 /* SECURE boot registers */
425 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
426 enum iwm_secure_boot_config_reg {
427 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
428 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
431 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
432 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
433 enum iwm_secure_boot_status_reg {
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
435 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
436 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
437 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
438 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
441 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
442 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
444 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
445 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
447 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
448 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
450 #define IWM_CSR_SECURE_TIME_OUT (100)
452 /* extended range in FW SRAM */
453 #define IWM_FW_MEM_EXTENDED_START 0x40000
454 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
456 /* FW chicken bits */
457 #define IWM_LMPM_CHICK 0xa01ff8
458 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
460 #define IWM_FH_TCSR_0_REG0 (0x1D00)
463 * HBUS (Host-side Bus)
465 * HBUS registers are mapped directly into PCI bus space, but are used
466 * to indirectly access device's internal memory or registers that
467 * may be powered-down.
469 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
470 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
471 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
472 * internal resources.
474 * Do not use iwl_write32()/iwl_read32() family to access these registers;
475 * these provide only simple PCI bus access, without waking up the MAC.
477 #define IWM_HBUS_BASE (0x400)
480 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
481 * structures, error log, event log, verifying uCode load).
482 * First write to address register, then read from or write to data register
483 * to complete the job. Once the address register is set up, accesses to
484 * data registers auto-increment the address by one dword.
485 * Bit usage for address registers (read or write):
486 * 0-31: memory address within device
488 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
489 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
490 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
491 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
493 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
494 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
495 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
498 * Registers for accessing device's internal peripheral registers
499 * (e.g. SCD, BSM, etc.). First write to address register,
500 * then read from or write to data register to complete the job.
501 * Bit usage for address registers (read or write):
502 * 0-15: register address (offset) within device
503 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
505 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
506 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
507 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
508 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
510 /* enable the ID buf for read */
511 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
512 #define IWM_WFMP_MAC_ADDR_0 0xa03080
513 #define IWM_WFMP_MAC_ADDR_1 0xa03084
514 #define IWM_LMPM_PMG_EN 0xa01cec
515 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
516 #define IWM_RFIC_REG_RD 0xad0470
517 #define IWM_WFPM_CTRL_REG 0xa03030
518 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
519 #define IWM_ENABLE_WFPM 0x80000000
521 #define IWM_AUX_MISC_REG 0xa200b0
522 #define IWM_HW_STEP_LOCATION_BITS 24
524 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
525 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
526 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
527 #define IWM_RSA_ENABLE 0xa24b08
528 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
529 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
530 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
531 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
532 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
533 #define IWM_SB_CPU_1_STATUS 0xa01e30
534 #define IWM_SB_CPU_2_STATUS 0Xa01e34
536 /* Used to enable DBGM */
537 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
540 * Per-Tx-queue write pointer (index, really!)
541 * Indicates index to next TFD that driver will fill (1 past latest filled).
543 * 0-7: queue write index
544 * 11-8: queue selector
546 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
548 /**********************************************************
550 **********************************************************/
552 * host interrupt timeout value
553 * used with setting interrupt coalescing timer
554 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
556 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
558 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
559 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
560 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
561 #define IWM_HOST_INT_OPER_MODE (1 << 31)
563 /*****************************************************************************
564 * 7000/3000 series SHR DTS addresses *
565 *****************************************************************************/
567 /* Diode Results Register Structure: */
568 enum iwm_dtd_diode_reg {
569 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
570 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
571 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
572 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
573 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
574 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
575 /* Those are the masks INSIDE the flags bit-field: */
576 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
577 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
578 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
579 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
591 * enum iwm_ucode_tlv_flag - ucode API flags
592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
593 * was a separate TLV but moved here to save space.
594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
595 * treats good CRC threshold as a boolean
596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
597 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
598 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
599 * offload profile config command.
600 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
601 * (rather than two) IPv6 addresses
602 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
603 * from the probe request template.
604 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
605 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
606 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
607 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
608 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
609 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
611 enum iwm_ucode_tlv_flag {
612 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
613 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
614 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
615 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
616 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
617 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
618 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
619 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
620 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
621 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
622 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
623 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
626 #define IWM_UCODE_TLV_FLAG_BITS \
627 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
628 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
629 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
630 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
633 * enum iwm_ucode_tlv_api - ucode api
634 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
635 * longer than the passive one, which is essential for fragmented scan.
636 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
637 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
639 * @IWM_NUM_UCODE_TLV_API: number of bits used
641 enum iwm_ucode_tlv_api {
642 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = 8,
643 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = 9,
644 IWM_UCODE_TLV_API_LQ_SS_PARAMS = 18,
646 IWM_NUM_UCODE_TLV_API = 32
649 #define IWM_UCODE_TLV_API_BITS \
650 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
653 * enum iwm_ucode_tlv_capa - ucode capabilities
654 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
655 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
656 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
657 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
658 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
659 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
660 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
661 * tx power value into TPC Report action frame and Link Measurement Report
663 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
664 * channel in DS parameter set element in probe requests.
665 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
667 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
668 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
669 * which also implies support for the scheduler configuration command
670 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
671 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
672 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
673 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
674 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
675 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
676 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
677 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
678 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
679 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
680 * sources for the MCC. This TLV bit is a future replacement to
681 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
683 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
684 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
685 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
686 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
688 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
689 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
690 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
691 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
692 * antenna the beacon should be transmitted
693 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
694 * from AP and will send it upon d0i3 exit.
695 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
696 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
697 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
698 * thresholds reporting
699 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
700 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
702 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
703 * memory addresses from the firmware.
704 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
705 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
708 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
710 enum iwm_ucode_tlv_capa {
711 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
712 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
713 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
714 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
715 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
716 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
717 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
718 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
719 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
720 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
721 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
722 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
723 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
724 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
725 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
726 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
727 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
728 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
729 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
730 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
731 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
732 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
733 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
734 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
735 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
736 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
737 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
738 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
739 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
740 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
741 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
742 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
743 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
744 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
745 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
746 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
747 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79,
748 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
749 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
751 IWM_NUM_UCODE_TLV_CAPA = 128
754 /* The default calibrate table size if not specified by firmware file */
755 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
756 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
757 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
759 /* The default max probe length if not specified by the firmware file */
760 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
763 * enumeration of ucode section.
764 * This enumeration is used directly for older firmware (before 16.0).
765 * For new firmware, there can be up to 4 sections (see below) but the
766 * first one packaged into the firmware file is the DATA section and
767 * some debugging code accesses that.
770 IWM_UCODE_SECTION_DATA,
771 IWM_UCODE_SECTION_INST,
774 * For 16.0 uCode and above, there is no differentiation between sections,
775 * just an offset to the HW address.
777 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
778 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
780 /* uCode version contains 4 values: Major/Minor/API/Serial */
781 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
782 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
783 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
784 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
787 * Calibration control struct.
788 * Sent as part of the phy configuration command.
789 * @flow_trigger: bitmap for which calibrations to perform according to
791 * @event_trigger: bitmap for which calibrations to perform according to
794 struct iwm_tlv_calib_ctrl {
795 uint32_t flow_trigger;
796 uint32_t event_trigger;
799 enum iwm_fw_phy_cfg {
800 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
801 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
802 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
803 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
804 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
805 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
806 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
807 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
808 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
809 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
812 #define IWM_UCODE_MAX_CS 1
815 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
816 * @cipher: a cipher suite selector
817 * @flags: cipher scheme flags (currently reserved for a future use)
818 * @hdr_len: a size of MPDU security header
819 * @pn_len: a size of PN
820 * @pn_off: an offset of pn from the beginning of the security header
821 * @key_idx_off: an offset of key index byte in the security header
822 * @key_idx_mask: a bit mask of key_idx bits
823 * @key_idx_shift: bit shift needed to get key_idx
824 * @mic_len: mic length in bytes
825 * @hw_cipher: a HW cipher index used in host commands
827 struct iwm_fw_cipher_scheme {
834 uint8_t key_idx_mask;
835 uint8_t key_idx_shift;
841 * struct iwm_fw_cscheme_list - a cipher scheme list
842 * @size: a number of entries
843 * @cs: cipher scheme entries
845 struct iwm_fw_cscheme_list {
847 struct iwm_fw_cipher_scheme cs[];
855 * BEGIN iwl-fw-file.h
858 /* v1/v2 uCode file layout */
859 struct iwm_ucode_header {
860 uint32_t ver; /* major/minor/API/serial */
863 uint32_t inst_size; /* bytes of runtime code */
864 uint32_t data_size; /* bytes of runtime data */
865 uint32_t init_size; /* bytes of init code */
866 uint32_t init_data_size; /* bytes of init data */
867 uint32_t boot_size; /* bytes of bootstrap code */
868 uint8_t data[0]; /* in same order as sizes */
871 uint32_t build; /* build number */
872 uint32_t inst_size; /* bytes of runtime code */
873 uint32_t data_size; /* bytes of runtime data */
874 uint32_t init_size; /* bytes of init code */
875 uint32_t init_data_size; /* bytes of init data */
876 uint32_t boot_size; /* bytes of bootstrap code */
877 uint8_t data[0]; /* in same order as sizes */
883 * new TLV uCode file layout
885 * The new TLV file format contains TLVs, that each specify
886 * some piece of data.
889 enum iwm_ucode_tlv_type {
890 IWM_UCODE_TLV_INVALID = 0, /* unused */
891 IWM_UCODE_TLV_INST = 1,
892 IWM_UCODE_TLV_DATA = 2,
893 IWM_UCODE_TLV_INIT = 3,
894 IWM_UCODE_TLV_INIT_DATA = 4,
895 IWM_UCODE_TLV_BOOT = 5,
896 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
897 IWM_UCODE_TLV_PAN = 7,
898 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
899 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
900 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
901 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
902 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
903 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
904 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
905 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
906 IWM_UCODE_TLV_WOWLAN_INST = 16,
907 IWM_UCODE_TLV_WOWLAN_DATA = 17,
908 IWM_UCODE_TLV_FLAGS = 18,
909 IWM_UCODE_TLV_SEC_RT = 19,
910 IWM_UCODE_TLV_SEC_INIT = 20,
911 IWM_UCODE_TLV_SEC_WOWLAN = 21,
912 IWM_UCODE_TLV_DEF_CALIB = 22,
913 IWM_UCODE_TLV_PHY_SKU = 23,
914 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
915 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
916 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
917 IWM_UCODE_TLV_NUM_OF_CPU = 27,
918 IWM_UCODE_TLV_CSCHEME = 28,
921 * Following two are not in our base tag, but allow
922 * handling ucode version 9.
924 IWM_UCODE_TLV_API_CHANGES_SET = 29,
925 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
927 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
928 IWM_UCODE_TLV_PAGING = 32,
929 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
930 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
931 IWM_UCODE_TLV_FW_VERSION = 36,
932 IWM_UCODE_TLV_FW_DBG_DEST = 38,
933 IWM_UCODE_TLV_FW_DBG_CONF = 39,
934 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
935 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
936 IWM_UCODE_TLV_FW_MEM_SEG = 51,
939 struct iwm_ucode_tlv {
940 uint32_t type; /* see above */
941 uint32_t length; /* not including type/length fields */
945 struct iwm_ucode_api {
950 struct iwm_ucode_capa {
955 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
957 struct iwm_tlv_ucode_header {
959 * The TLV style ucode header is distinguished from
960 * the v1/v2 style header by first four bytes being
961 * zero, as such is an invalid combination of
962 * major/minor/API/serial versions.
966 uint8_t human_readable[64];
967 uint32_t ver; /* major/minor/API/serial */
971 * The data contained herein has a TLV layout,
972 * see above for the TLV header and types.
973 * Note that each TLV is padded to a length
974 * that is a multiple of 4 for alignment.
988 * Registers in this file are internal, not PCI bus memory mapped.
989 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
991 #define IWM_PRPH_BASE (0x00000)
992 #define IWM_PRPH_END (0xFFFFF)
994 /* APMG (power management) constants */
995 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
996 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
997 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
998 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
999 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1000 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1001 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1002 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1003 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1004 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1005 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1007 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1008 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1009 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1011 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1012 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1013 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1014 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1015 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1016 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1017 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1019 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1021 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1023 /* Device system time */
1024 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1026 /* Device NMI register */
1027 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1028 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1029 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1030 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1031 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1034 * Device reset for family 8000
1035 * write to bit 24 in order to reset the CPU
1037 #define IWM_RELEASE_CPU_RESET 0x300c
1038 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1041 /*****************************************************************************
1042 * 7000/3000 series SHR DTS addresses *
1043 *****************************************************************************/
1045 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1046 #define IWM_DTSC_CFG_MODE (0x00a10604)
1047 #define IWM_DTSC_VREF_AVG (0x00a10648)
1048 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1049 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1050 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1056 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1057 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1058 * host DRAM. It steers each frame's Tx command (which contains the frame
1059 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1060 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1061 * but one DMA channel may take input from several queues.
1063 * Tx DMA FIFOs have dedicated purposes.
1065 * For 5000 series and up, they are used differently
1066 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1068 * 0 -- EDCA BK (background) frames, lowest priority
1069 * 1 -- EDCA BE (best effort) frames, normal priority
1070 * 2 -- EDCA VI (video) frames, higher priority
1071 * 3 -- EDCA VO (voice) and management frames, highest priority
1077 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1078 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1079 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1081 * The driver sets up each queue to work in one of two modes:
1083 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1084 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1085 * contains TFDs for a unique combination of Recipient Address (RA)
1086 * and Traffic Identifier (TID), that is, traffic of a given
1087 * Quality-Of-Service (QOS) priority, destined for a single station.
1089 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1090 * each frame within the BA window, including whether it's been transmitted,
1091 * and whether it's been acknowledged by the receiving station. The device
1092 * automatically processes block-acks received from the receiving STA,
1093 * and reschedules un-acked frames to be retransmitted (successful
1094 * Tx completion may end up being out-of-order).
1096 * The driver must maintain the queue's Byte Count table in host DRAM
1098 * This mode does not support fragmentation.
1100 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1101 * The device may automatically retry Tx, but will retry only one frame
1102 * at a time, until receiving ACK from receiving station, or reaching
1103 * retry limit and giving up.
1105 * The command queue (#4/#9) must use this mode!
1106 * This mode does not require use of the Byte Count table in host DRAM.
1108 * Driver controls scheduler operation via 3 means:
1109 * 1) Scheduler registers
1110 * 2) Shared scheduler data base in internal SRAM
1111 * 3) Shared data in host DRAM
1115 * When loading, driver should allocate memory for:
1116 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1117 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1118 * (1024 bytes for each queue).
1120 * After receiving "Alive" response from uCode, driver must initialize
1121 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1122 * the driver can't issue commands!):
1124 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1127 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1128 * can keep track of at one time when creating block-ack chains of frames.
1129 * Note that "64" matches the number of ack bits in a block-ack packet.
1131 #define IWM_SCD_WIN_SIZE 64
1132 #define IWM_SCD_FRAME_LIMIT 64
1134 #define IWM_SCD_TXFIFO_POS_TID (0)
1135 #define IWM_SCD_TXFIFO_POS_RA (4)
1136 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1139 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1140 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1141 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1142 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1143 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1145 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1146 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1147 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1148 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1149 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1150 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1151 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1152 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1153 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1154 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1157 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1158 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1161 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1162 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1164 /* Translation Data */
1165 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1166 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1168 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1169 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1171 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1172 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1174 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1175 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1177 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1179 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1180 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1181 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1182 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1183 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1184 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1185 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1186 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1187 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1188 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1189 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1191 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1194 return IWM_SCD_BASE + 0x18 + chnl * 4;
1195 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1198 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1201 return IWM_SCD_BASE + 0x68 + chnl * 4;
1202 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1205 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1208 return IWM_SCD_BASE + 0x10c + chnl * 4;
1209 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1212 /*********************** END TX SCHEDULER *************************************/
1214 /* Oscillator clock */
1215 #define IWM_OSC_CLK (0xa04068)
1216 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1226 /****************************/
1227 /* Flow Handler Definitions */
1228 /****************************/
1231 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1232 * Addresses are offsets from device's PCI hardware base address.
1234 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1235 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1238 * Keep-Warm (KW) buffer base address.
1240 * Driver must allocate a 4KByte buffer that is for keeping the
1241 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1242 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1243 * from going into a power-savings mode that would cause higher DRAM latency,
1244 * and possible data over/under-runs, before all Tx/Rx is complete.
1246 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1247 * of the buffer, which must be 4K aligned. Once this is set up, the device
1248 * automatically invokes keep-warm accesses when normal accesses might not
1249 * be sufficient to maintain fast DRAM response.
1252 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1254 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1258 * TFD Circular Buffers Base (CBBC) addresses
1260 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1261 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1262 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1263 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1264 * aligned (address bits 0-7 must be 0).
1265 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1266 * for them are in different places.
1268 * Bit fields in each pointer register:
1269 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1271 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1272 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1273 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1274 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1275 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1276 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1278 /* Find TFD CB base pointer for given queue */
1279 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1282 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1284 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1285 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1290 * Rx SRAM Control and Status Registers (RSCSR)
1292 * These registers provide handshake between driver and device for the Rx queue
1293 * (this queue handles *all* command responses, notifications, Rx data, etc.
1294 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1295 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1296 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1297 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1298 * mapping between RBDs and RBs.
1300 * Driver must allocate host DRAM memory for the following, and set the
1301 * physical address of each into device registers:
1303 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1304 * entries (although any power of 2, up to 4096, is selectable by driver).
1305 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1306 * (typically 4K, although 8K or 16K are also selectable by driver).
1307 * Driver sets up RB size and number of RBDs in the CB via Rx config
1308 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1310 * Bit fields within one RBD:
1311 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1313 * Driver sets physical address [35:8] of base of RBD circular buffer
1314 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1316 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1317 * (RBs) have been filled, via a "write pointer", actually the index of
1318 * the RB's corresponding RBD within the circular buffer. Driver sets
1319 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1321 * Bit fields in lower dword of Rx status buffer (upper dword not used
1323 * 31-12: Not used by driver
1324 * 11- 0: Index of last filled Rx buffer descriptor
1325 * (device writes, driver reads this value)
1327 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1328 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1329 * and update the device's "write" index register,
1330 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1332 * This "write" index corresponds to the *next* RBD that the driver will make
1333 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1334 * the circular buffer. This value should initially be 0 (before preparing any
1335 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1336 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1337 * "read" index has advanced past 1! See below).
1338 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1340 * As the device fills RBs (referenced from contiguous RBDs within the circular
1341 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1342 * to tell the driver the index of the latest filled RBD. The driver must
1343 * read this "read" index from DRAM after receiving an Rx interrupt from device
1345 * The driver must also internally keep track of a third index, which is the
1346 * next RBD to process. When receiving an Rx interrupt, driver should process
1347 * all filled but unprocessed RBs up to, but not including, the RB
1348 * corresponding to the "read" index. For example, if "read" index becomes "1",
1349 * driver may process the RB pointed to by RBD 0. Depending on volume of
1350 * traffic, there may be many RBs to process.
1352 * If read index == write index, device thinks there is no room to put new data.
1353 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1354 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1355 * and "read" indexes; that is, make sure that there are no more than 254
1356 * buffers waiting to be filled.
1358 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1359 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1360 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1363 * Physical base address of 8-byte Rx Status buffer.
1365 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1367 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1370 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1372 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1374 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1377 * Rx write pointer (index, really!).
1379 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1380 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1382 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1383 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1385 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1386 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1389 * Rx Config/Status Registers (RCSR)
1390 * Rx Config Reg for channel 0 (only channel used)
1392 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1393 * normal operation (see bit fields).
1395 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1396 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1397 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1400 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1401 * '10' operate normally
1403 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1404 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1406 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1407 * '10' 12K, '11' 16K.
1409 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1410 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1411 * typical value 0x10 (about 1/2 msec)
1414 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1415 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1416 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1418 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1419 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1420 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1422 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1423 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1424 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1425 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1426 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1427 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1429 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1430 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1431 #define IWM_RX_RB_TIMEOUT (0x11)
1433 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1434 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1435 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1437 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1438 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1439 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1440 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1442 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1443 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1444 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1447 * Rx Shared Status Registers (RSSR)
1449 * After stopping Rx DMA channel (writing 0 to
1450 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1451 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1454 * 24: 1 = Channel 0 is idle
1456 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1457 * contain default values that should not be altered by the driver.
1459 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1460 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1462 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1463 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1464 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1465 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1467 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1469 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1471 /* TFDB Area - TFDs buffer table */
1472 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1473 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1474 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1475 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1476 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1479 * Transmit DMA Channel Control/Status Registers (TCSR)
1481 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1482 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1483 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1485 * To use a Tx DMA channel, driver must initialize its
1486 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1488 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1489 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1491 * All other bits should be 0.
1494 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1495 * '10' operate normally
1496 * 29- 4: Reserved, set to "0"
1497 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1498 * 2- 0: Reserved, set to "0"
1500 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1501 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1503 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1504 #define IWM_FH_TCSR_CHNL_NUM (8)
1506 /* TCSR: tx_config register values */
1507 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1508 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1509 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1510 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1511 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1512 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1514 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1515 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1517 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1518 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1520 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1521 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1522 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1524 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1525 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1526 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1528 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1529 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1530 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1532 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1533 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1534 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1536 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1537 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1540 * Tx Shared Status Registers (TSSR)
1542 * After stopping Tx DMA channel (writing 0 to
1543 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1544 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1545 * (channel's buffers empty | no pending requests).
1548 * 31-24: 1 = Channel buffers empty (channel 7:0)
1549 * 23-16: 1 = No pending requests (channel 7:0)
1551 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1552 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1554 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1557 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1558 * 31: Indicates an address error when accessed to internal memory
1559 * uCode/driver must write "1" in order to clear this flag
1560 * 30: Indicates that Host did not send the expected number of dwords to FH
1561 * uCode/driver must write "1" in order to clear this flag
1562 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1563 * command was received from the scheduler while the TRB was already full
1564 * with previous command
1565 * uCode/driver must write "1" in order to clear this flag
1566 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1567 * bit is set, it indicates that the FH has received a full indication
1568 * from the RTC TxFIFO and the current value of the TxCredit counter was
1569 * not equal to zero. This mean that the credit mechanism was not
1570 * synchronized to the TxFIFO status
1571 * uCode/driver must write "1" in order to clear this flag
1573 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1574 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1576 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1578 /* Tx service channels */
1579 #define IWM_FH_SRVC_CHNL (9)
1580 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1581 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1582 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1583 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1585 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1586 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1589 /* Instruct FH to increment the retry count of a packet when
1590 * it is brought from the memory to TX-FIFO
1592 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1594 #define IWM_RX_QUEUE_SIZE 256
1595 #define IWM_RX_QUEUE_MASK 255
1596 #define IWM_RX_QUEUE_SIZE_LOG 8
1599 * RX related structures and functions
1601 #define IWM_RX_FREE_BUFFERS 64
1602 #define IWM_RX_LOW_WATERMARK 8
1605 * struct iwm_rb_status - reseve buffer status
1606 * host memory mapped FH registers
1607 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1608 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1609 * @finished_rb_num [0:11] - Indicates the index of the current RB
1610 * in which the last frame was written to
1611 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1612 * which was transferred
1614 struct iwm_rb_status {
1615 uint16_t closed_rb_num;
1616 uint16_t closed_fr_num;
1617 uint16_t finished_rb_num;
1618 uint16_t finished_fr_nam;
1623 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1624 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1625 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1626 IWM_TFD_QUEUE_SIZE_BC_DUP)
1627 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1628 #define IWM_NUM_OF_TBS 20
1630 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1632 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1635 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1637 * This structure contains dma address and length of transmission address
1639 * @lo: low [31:0] portion of the dma address of TX buffer
1640 * every even is unaligned on 16 bit boundary
1641 * @hi_n_len 0-3 [35:32] portion of dma
1642 * 4-15 length of the tx buffer
1652 * Transmit Frame Descriptor (TFD)
1654 * @ __reserved1[3] reserved
1655 * @ num_tbs 0-4 number of active tbs
1657 * 6-7 padding (not used)
1658 * @ tbs[20] transmit frame buffer descriptors
1661 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1662 * Both driver and device share these circular buffers, each of which must be
1663 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1665 * Driver must indicate the physical address of the base of each
1666 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1668 * Each TFD contains pointer/size information for up to 20 data buffers
1669 * in host DRAM. These buffers collectively contain the (one) frame described
1670 * by the TFD. Each buffer must be a single contiguous block of memory within
1671 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1672 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1673 * Tx frame, up to 8 KBytes in size.
1675 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1678 uint8_t __reserved1[3];
1680 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1684 /* Keep Warm Size */
1685 #define IWM_KW_SIZE 0x1000 /* 4k */
1687 /* Fixed (non-configurable) rx data from phy */
1690 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1691 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1692 * @tfd_offset 0-12 - tx command byte count
1693 * 12-16 - station index
1695 struct iwm_agn_scd_bc_tbl {
1696 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1704 * BEGIN mvm/fw-api.h
1707 /* Maximum number of Tx queues. */
1708 #define IWM_MVM_MAX_QUEUES 31
1710 /* Tx queue numbers */
1712 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1713 IWM_MVM_CMD_QUEUE = 9,
1714 IWM_MVM_AUX_QUEUE = 15,
1717 enum iwm_mvm_tx_fifo {
1718 IWM_MVM_TX_FIFO_BK = 0,
1722 IWM_MVM_TX_FIFO_MCAST = 5,
1723 IWM_MVM_TX_FIFO_CMD = 7,
1726 #define IWM_MVM_STATION_COUNT 16
1730 IWM_MVM_ALIVE = 0x1,
1731 IWM_REPLY_ERROR = 0x2,
1733 IWM_INIT_COMPLETE_NOTIF = 0x4,
1735 /* PHY context commands */
1736 IWM_PHY_CONTEXT_CMD = 0x8,
1739 /* UMAC scan commands */
1740 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1741 IWM_SCAN_CFG_CMD = 0xc,
1742 IWM_SCAN_REQ_UMAC = 0xd,
1743 IWM_SCAN_ABORT_UMAC = 0xe,
1744 IWM_SCAN_COMPLETE_UMAC = 0xf,
1747 IWM_ADD_STA_KEY = 0x17,
1749 IWM_REMOVE_STA = 0x19,
1753 IWM_TXPATH_FLUSH = 0x1e,
1754 IWM_MGMT_MCAST_KEY = 0x1f,
1756 /* scheduler config */
1757 IWM_SCD_QUEUE_CFG = 0x1d,
1762 /* MAC and Binding commands */
1763 IWM_MAC_CONTEXT_CMD = 0x28,
1764 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1765 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1766 IWM_BINDING_CONTEXT_CMD = 0x2b,
1767 IWM_TIME_QUOTA_CMD = 0x2c,
1768 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1772 /* paging block to FW cpu2 */
1773 IWM_FW_PAGING_BLOCK_CMD = 0x4f,
1776 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1777 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1778 IWM_HOT_SPOT_CMD = 0x53,
1779 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1780 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1781 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1782 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1783 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1786 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1787 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1788 IWM_PHY_DB_CMD = 0x6c,
1790 /* Power - legacy power table command */
1791 IWM_POWER_TABLE_CMD = 0x77,
1792 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1794 /* Thermal Throttling*/
1795 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1798 IWM_SCAN_ABORT_CMD = 0x81,
1799 IWM_SCAN_START_NOTIFICATION = 0x82,
1800 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1803 IWM_NVM_ACCESS_CMD = 0x88,
1805 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1807 IWM_BEACON_NOTIFICATION = 0x90,
1808 IWM_BEACON_TEMPLATE_CMD = 0x91,
1809 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1810 IWM_BT_CONFIG = 0x9b,
1811 IWM_STATISTICS_NOTIFICATION = 0x9d,
1812 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1814 /* RF-KILL commands and notifications */
1815 IWM_CARD_STATE_CMD = 0xa0,
1816 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1818 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1820 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1822 /* Power - new power table command */
1823 IWM_MAC_PM_POWER_TABLE = 0xa9,
1825 IWM_REPLY_RX_PHY_CMD = 0xc0,
1826 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1827 IWM_BA_NOTIF = 0xc5,
1829 /* Location Aware Regulatory */
1830 IWM_MCC_UPDATE_CMD = 0xc8,
1831 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1834 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1835 IWM_BT_COEX_PROT_ENV = 0xcd,
1836 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1837 IWM_BT_COEX_CI = 0x5d,
1839 IWM_REPLY_SF_CFG_CMD = 0xd1,
1840 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1842 /* DTS measurements */
1843 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1844 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1846 IWM_REPLY_DEBUG_CMD = 0xf0,
1847 IWM_DEBUG_LOG_MSG = 0xf7,
1849 IWM_MCAST_FILTER_CMD = 0xd0,
1851 /* D3 commands/notifications */
1852 IWM_D3_CONFIG_CMD = 0xd3,
1853 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1854 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1855 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1857 /* for WoWLAN in particular */
1858 IWM_WOWLAN_PATTERNS = 0xe0,
1859 IWM_WOWLAN_CONFIGURATION = 0xe1,
1860 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1861 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1862 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1863 IWM_WOWLAN_GET_STATUSES = 0xe5,
1864 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1866 /* and for NetDetect */
1867 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1868 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1869 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1870 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1871 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1873 IWM_REPLY_MAX = 0xff,
1876 enum iwm_phy_ops_subcmd_ids {
1877 IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE = 0x0,
1878 IWM_CTDP_CONFIG_CMD = 0x03,
1879 IWM_TEMP_REPORTING_THRESHOLDS_CMD = 0x04,
1880 IWM_CT_KILL_NOTIFICATION = 0xFE,
1881 IWM_DTS_MEASUREMENT_NOTIF_WIDE = 0xFF,
1884 /* command groups */
1886 IWM_LEGACY_GROUP = 0x0,
1887 IWM_LONG_GROUP = 0x1,
1888 IWM_SYSTEM_GROUP = 0x2,
1889 IWM_MAC_CONF_GROUP = 0x3,
1890 IWM_PHY_OPS_GROUP = 0x4,
1891 IWM_DATA_PATH_GROUP = 0x5,
1892 IWM_PROT_OFFLOAD_GROUP = 0xb,
1896 * struct iwm_cmd_response - generic response struct for most commands
1897 * @status: status of the command asked, changes for each one
1899 struct iwm_cmd_response {
1904 * struct iwm_tx_ant_cfg_cmd
1905 * @valid: valid antenna configuration
1907 struct iwm_tx_ant_cfg_cmd {
1912 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1913 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1914 * @flags: (reserved for future implementation)
1915 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1916 * @pwr_restriction: TX power restriction in dBms.
1918 struct iwm_reduce_tx_power_cmd {
1920 uint8_t mac_context_id;
1921 uint16_t pwr_restriction;
1922 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1925 * Calibration control struct.
1926 * Sent as part of the phy configuration command.
1927 * @flow_trigger: bitmap for which calibrations to perform according to
1929 * @event_trigger: bitmap for which calibrations to perform according to
1932 struct iwm_calib_ctrl {
1933 uint32_t flow_trigger;
1934 uint32_t event_trigger;
1937 /* This enum defines the bitmap of various calibrations to enable in both
1938 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1940 enum iwm_calib_cfg {
1941 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1942 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1943 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1944 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1945 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1946 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1947 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1948 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1949 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1950 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1951 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1952 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1953 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1954 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1955 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1956 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1957 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1958 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1959 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1963 * Phy configuration command.
1965 struct iwm_phy_cfg_cmd {
1967 struct iwm_calib_ctrl calib_control;
1970 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1971 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1972 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1973 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1974 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1975 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1976 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1977 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1978 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1979 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1982 /* Target of the IWM_NVM_ACCESS_CMD */
1984 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1985 IWM_NVM_ACCESS_TARGET_OTP = 1,
1986 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1989 /* Section types for IWM_NVM_ACCESS_CMD */
1991 IWM_NVM_SECTION_TYPE_SW = 1,
1992 IWM_NVM_SECTION_TYPE_REGULATORY = 3,
1993 IWM_NVM_SECTION_TYPE_CALIBRATION = 4,
1994 IWM_NVM_SECTION_TYPE_PRODUCTION = 5,
1995 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE = 11,
1996 IWM_NVM_SECTION_TYPE_PHY_SKU = 12,
1997 IWM_NVM_MAX_NUM_SECTIONS = 13,
2001 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2002 * @op_code: 0 - read, 1 - write
2003 * @target: IWM_NVM_ACCESS_TARGET_*
2004 * @type: IWM_NVM_SECTION_TYPE_*
2005 * @offset: offset in bytes into the section
2006 * @length: in bytes, to read/write
2007 * @data: if write operation, the data to write. On read its empty
2009 struct iwm_nvm_access_cmd {
2016 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2018 #define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */
2021 * struct iwm_fw_paging_cmd - paging layout
2023 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f)
2025 * Send to FW the paging layout in the driver.
2027 * @flags: various flags for the command
2028 * @block_size: the block size in powers of 2
2029 * @block_num: number of blocks specified in the command.
2030 * @device_phy_addr: virtual addresses from device side
2032 struct iwm_fw_paging_cmd {
2034 uint32_t block_size;
2036 uint32_t device_phy_addr[IWM_NUM_OF_FW_PAGING_BLOCKS];
2037 } __packed; /* IWM_FW_PAGING_BLOCK_CMD_API_S_VER_1 */
2042 * @IWM_FW_ITEM_ID_PAGING: Address of the pages that the FW will upload
2045 enum iwm_fw_item_id {
2046 IWM_FW_ITEM_ID_PAGING = 3,
2050 * struct iwm_fw_get_item_cmd - get an item from the fw
2052 struct iwm_fw_get_item_cmd {
2054 } __packed; /* IWM_FW_GET_ITEM_CMD_API_S_VER_1 */
2057 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2058 * @offset: offset in bytes into the section
2059 * @length: in bytes, either how much was written or read
2060 * @type: IWM_NVM_SECTION_TYPE_*
2061 * @status: 0 for success, fail otherwise
2062 * @data: if read operation, the data returned. Empty on write.
2064 struct iwm_nvm_access_resp {
2070 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2072 /* IWM_MVM_ALIVE 0x1 */
2074 /* alive response is_valid values */
2075 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2076 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2078 /* alive response ver_type values */
2081 IWM_FW_TYPE_PROT = 1,
2083 IWM_FW_TYPE_WOWLAN = 3,
2084 IWM_FW_TYPE_TIMING = 4,
2085 IWM_FW_TYPE_WIPAN = 5
2088 /* alive response ver_subtype values */
2090 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2091 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2092 IWM_FW_SUBTYPE_REDUCED = 2,
2093 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2094 IWM_FW_SUBTYPE_WOWLAN = 4,
2095 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2096 IWM_FW_SUBTYPE_WIPAN = 6,
2097 IWM_FW_SUBTYPE_INITIALIZE = 9
2100 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2101 #define IWM_ALIVE_STATUS_OK 0xCAFE
2103 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2105 struct iwm_mvm_alive_resp_ver1 {
2108 uint8_t ucode_minor;
2109 uint8_t ucode_major;
2113 uint8_t ver_subtype;
2119 uint32_t error_event_table_ptr; /* SRAM address for error log */
2120 uint32_t log_event_table_ptr; /* SRAM address for event log */
2121 uint32_t cpu_register_ptr;
2122 uint32_t dbgm_config_ptr;
2123 uint32_t alive_counter_ptr;
2124 uint32_t scd_base_ptr; /* SRAM address for SCD */
2125 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2127 struct iwm_mvm_alive_resp_ver2 {
2130 uint8_t ucode_minor;
2131 uint8_t ucode_major;
2135 uint8_t ver_subtype;
2141 uint32_t error_event_table_ptr; /* SRAM address for error log */
2142 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2143 uint32_t cpu_register_ptr;
2144 uint32_t dbgm_config_ptr;
2145 uint32_t alive_counter_ptr;
2146 uint32_t scd_base_ptr; /* SRAM address for SCD */
2147 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2148 uint32_t st_fwrd_size;
2149 uint8_t umac_minor; /* UMAC version: minor */
2150 uint8_t umac_major; /* UMAC version: major */
2151 uint16_t umac_id; /* UMAC version: id */
2152 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2153 uint32_t dbg_print_buff_addr;
2154 } __packed; /* ALIVE_RES_API_S_VER_2 */
2156 struct iwm_mvm_alive_resp {
2159 uint32_t ucode_minor;
2160 uint32_t ucode_major;
2161 uint8_t ver_subtype;
2166 uint32_t error_event_table_ptr; /* SRAM address for error log */
2167 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2168 uint32_t cpu_register_ptr;
2169 uint32_t dbgm_config_ptr;
2170 uint32_t alive_counter_ptr;
2171 uint32_t scd_base_ptr; /* SRAM address for SCD */
2172 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2173 uint32_t st_fwrd_size;
2174 uint32_t umac_minor; /* UMAC version: minor */
2175 uint32_t umac_major; /* UMAC version: major */
2176 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2177 uint32_t dbg_print_buff_addr;
2178 } __packed; /* ALIVE_RES_API_S_VER_3 */
2180 /* Error response/notification */
2182 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2183 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2184 IWM_FW_ERR_SERVICE = 0x2,
2185 IWM_FW_ERR_ARC_MEMORY = 0x3,
2186 IWM_FW_ERR_ARC_CODE = 0x4,
2187 IWM_FW_ERR_WATCH_DOG = 0x5,
2188 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2189 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2190 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2191 IWM_FW_ERR_UNEXPECTED = 0xFE,
2192 IWM_FW_ERR_FATAL = 0xFF
2196 * struct iwm_error_resp - FW error indication
2197 * ( IWM_REPLY_ERROR = 0x2 )
2198 * @error_type: one of IWM_FW_ERR_*
2199 * @cmd_id: the command ID for which the error occurred
2200 * @bad_cmd_seq_num: sequence number of the erroneous command
2201 * @error_service: which service created the error, applicable only if
2202 * error_type = 2, otherwise 0
2203 * @timestamp: TSF in usecs.
2205 struct iwm_error_resp {
2206 uint32_t error_type;
2209 uint16_t bad_cmd_seq_num;
2210 uint32_t error_service;
2215 /* Common PHY, MAC and Bindings definitions */
2217 #define IWM_MAX_MACS_IN_BINDING (3)
2218 #define IWM_MAX_BINDINGS (4)
2219 #define IWM_AUX_BINDING_INDEX (3)
2220 #define IWM_MAX_PHYS (4)
2222 /* Used to extract ID and color from the context dword */
2223 #define IWM_FW_CTXT_ID_POS (0)
2224 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2225 #define IWM_FW_CTXT_COLOR_POS (8)
2226 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2227 #define IWM_FW_CTXT_INVALID (0xffffffff)
2229 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2230 (_color << IWM_FW_CTXT_COLOR_POS))
2232 /* Possible actions on PHYs, MACs and Bindings */
2234 IWM_FW_CTXT_ACTION_STUB = 0,
2235 IWM_FW_CTXT_ACTION_ADD,
2236 IWM_FW_CTXT_ACTION_MODIFY,
2237 IWM_FW_CTXT_ACTION_REMOVE,
2238 IWM_FW_CTXT_ACTION_NUM
2239 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2243 /* Time Event types, according to MAC type */
2244 enum iwm_time_event_type {
2245 /* BSS Station Events */
2246 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2247 IWM_TE_BSS_STA_ASSOC,
2248 IWM_TE_BSS_EAP_DHCP_PROT,
2249 IWM_TE_BSS_QUIET_PERIOD,
2251 /* P2P Device Events */
2252 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2253 IWM_TE_P2P_DEVICE_LISTEN,
2254 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2255 IWM_TE_P2P_DEVICE_FULL_SCAN,
2257 /* P2P Client Events */
2258 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2259 IWM_TE_P2P_CLIENT_ASSOC,
2260 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2263 IWM_TE_P2P_GO_ASSOC_PROT,
2264 IWM_TE_P2P_GO_REPETITIVE_NOA,
2265 IWM_TE_P2P_GO_CT_WINDOW,
2267 /* WiDi Sync Events */
2268 IWM_TE_WIDI_TX_SYNC,
2271 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2275 /* Time event - defines for command API v1 */
2278 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2279 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2280 * the first fragment is scheduled.
2281 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2282 * the first 2 fragments are scheduled.
2283 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2284 * number of fragments are valid.
2286 * Other than the constant defined above, specifying a fragmentation value 'x'
2287 * means that the event can be fragmented but only the first 'x' will be
2291 IWM_TE_V1_FRAG_NONE = 0,
2292 IWM_TE_V1_FRAG_SINGLE = 1,
2293 IWM_TE_V1_FRAG_DUAL = 2,
2294 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2297 /* If a Time Event can be fragmented, this is the max number of fragments */
2298 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2299 /* Repeat the time event endlessly (until removed) */
2300 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2301 /* If a Time Event has bounded repetitions, this is the maximal value */
2302 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2304 /* Time Event dependencies: none, on another TE, or in a specific time */
2306 IWM_TE_V1_INDEPENDENT = 0,
2307 IWM_TE_V1_DEP_OTHER = (1 << 0),
2308 IWM_TE_V1_DEP_TSF = (1 << 1),
2309 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2310 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2313 * @IWM_TE_V1_NOTIF_NONE: no notifications
2314 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2315 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2316 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2317 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2318 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2319 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2320 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2321 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2323 * Supported Time event notifications configuration.
2324 * A notification (both event and fragment) includes a status indicating weather
2325 * the FW was able to schedule the event or not. For fragment start/end
2326 * notification the status is always success. There is no start/end fragment
2327 * notification for monolithic events.
2330 IWM_TE_V1_NOTIF_NONE = 0,
2331 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2332 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2333 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2334 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2335 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2336 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2337 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2338 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2339 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2340 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2342 /* Time event - defines for command API */
2345 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2346 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2347 * the first fragment is scheduled.
2348 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2349 * the first 2 fragments are scheduled.
2350 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2351 * number of fragments are valid.
2353 * Other than the constant defined above, specifying a fragmentation value 'x'
2354 * means that the event can be fragmented but only the first 'x' will be
2358 IWM_TE_V2_FRAG_NONE = 0,
2359 IWM_TE_V2_FRAG_SINGLE = 1,
2360 IWM_TE_V2_FRAG_DUAL = 2,
2361 IWM_TE_V2_FRAG_MAX = 0xfe,
2362 IWM_TE_V2_FRAG_ENDLESS = 0xff
2365 /* Repeat the time event endlessly (until removed) */
2366 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2367 /* If a Time Event has bounded repetitions, this is the maximal value */
2368 #define IWM_TE_V2_REPEAT_MAX 0xfe
2370 #define IWM_TE_V2_PLACEMENT_POS 12
2371 #define IWM_TE_V2_ABSENCE_POS 15
2373 /* Time event policy values
2374 * A notification (both event and fragment) includes a status indicating weather
2375 * the FW was able to schedule the event or not. For fragment start/end
2376 * notification the status is always success. There is no start/end fragment
2377 * notification for monolithic events.
2379 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2380 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2381 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2382 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2383 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2384 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2385 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2386 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2387 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2388 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2389 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2390 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2391 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2394 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2396 /* notifications (event start/stop, fragment start/stop) */
2397 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2398 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2399 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2400 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2402 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2403 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2404 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2405 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2407 IWM_TE_V2_NOTIF_MSK = 0xff,
2409 /* placement characteristics */
2410 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2411 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2412 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2414 /* are we present or absent during the Time Event. */
2415 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2419 * struct iwm_time_event_cmd_api - configuring Time Events
2420 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2421 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2422 * ( IWM_TIME_EVENT_CMD = 0x29 )
2423 * @id_and_color: ID and color of the relevant MAC
2424 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2425 * @id: this field has two meanings, depending on the action:
2426 * If the action is ADD, then it means the type of event to add.
2427 * For all other actions it is the unique event ID assigned when the
2428 * event was added by the FW.
2429 * @apply_time: When to start the Time Event (in GP2)
2430 * @max_delay: maximum delay to event's start (apply time), in TU
2431 * @depends_on: the unique ID of the event we depend on (if any)
2432 * @interval: interval between repetitions, in TU
2433 * @duration: duration of event in TU
2434 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2435 * @max_frags: maximal number of fragments the Time Event can be divided to
2436 * @policy: defines whether uCode shall notify the host or other uCode modules
2437 * on event and/or fragment start and/or end
2438 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2439 * IWM_TE_EVENT_SOCIOPATHIC
2440 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2442 struct iwm_time_event_cmd {
2443 /* COMMON_INDEX_HDR_API_S_VER_1 */
2444 uint32_t id_and_color;
2447 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2448 uint32_t apply_time;
2450 uint32_t depends_on;
2456 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2459 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2460 * @status: bit 0 indicates success, all others specify errors
2461 * @id: the Time Event type
2462 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2463 * @id_and_color: ID and color of the relevant MAC
2465 struct iwm_time_event_resp {
2469 uint32_t id_and_color;
2470 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2473 * struct iwm_time_event_notif - notifications of time event start/stop
2474 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2475 * @timestamp: action timestamp in GP2
2476 * @session_id: session's unique id
2477 * @unique_id: unique id of the Time Event itself
2478 * @id_and_color: ID and color of the relevant MAC
2479 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2480 * @status: true if scheduled, false otherwise (not executed)
2482 struct iwm_time_event_notif {
2484 uint32_t session_id;
2486 uint32_t id_and_color;
2489 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2492 /* Bindings and Time Quota */
2495 * struct iwm_binding_cmd - configuring bindings
2496 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2497 * @id_and_color: ID and color of the relevant Binding
2498 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2499 * @macs: array of MAC id and colors which belong to the binding
2500 * @phy: PHY id and color which belongs to the binding
2502 struct iwm_binding_cmd {
2503 /* COMMON_INDEX_HDR_API_S_VER_1 */
2504 uint32_t id_and_color;
2506 /* IWM_BINDING_DATA_API_S_VER_1 */
2507 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2509 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2511 /* The maximal number of fragments in the FW's schedule session */
2512 #define IWM_MVM_MAX_QUOTA 128
2515 * struct iwm_time_quota_data - configuration of time quota per binding
2516 * @id_and_color: ID and color of the relevant Binding
2517 * @quota: absolute time quota in TU. The scheduler will try to divide the
2518 * remainig quota (after Time Events) according to this quota.
2519 * @max_duration: max uninterrupted context duration in TU
2521 struct iwm_time_quota_data {
2522 uint32_t id_and_color;
2524 uint32_t max_duration;
2525 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2528 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2529 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2530 * @quotas: allocations per binding
2532 struct iwm_time_quota_cmd {
2533 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2534 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2539 /* Supported bands */
2540 #define IWM_PHY_BAND_5 (0)
2541 #define IWM_PHY_BAND_24 (1)
2543 /* Supported channel width, vary if there is VHT support */
2544 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2545 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2546 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2547 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2550 * Control channel position:
2551 * For legacy set bit means upper channel, otherwise lower.
2552 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2553 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2556 * 40Mhz |_______|_______|
2557 * 80Mhz |_______|_______|_______|_______|
2558 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2559 * code 011 010 001 000 | 100 101 110 111
2561 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2562 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2563 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2564 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2565 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2566 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2567 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2568 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2571 * @band: IWM_PHY_BAND_*
2572 * @channel: channel number
2573 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2574 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2576 struct iwm_fw_channel_info {
2583 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2584 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2585 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2586 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2587 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2588 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2589 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2590 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2591 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2592 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2593 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2594 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2595 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2596 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2597 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2598 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2599 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2600 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2601 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2602 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2603 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2605 /* TODO: fix the value, make it depend on firmware at runtime? */
2606 #define IWM_NUM_PHY_CTX 3
2608 /* TODO: complete missing documentation */
2610 * struct iwm_phy_context_cmd - config of the PHY context
2611 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2612 * @id_and_color: ID and color of the relevant Binding
2613 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2614 * @apply_time: 0 means immediate apply and context switch.
2615 * other value means apply new params after X usecs
2616 * @tx_param_color: ???
2618 * @txchain_info: ???
2619 * @rxchain_info: ???
2620 * @acquisition_data: ???
2621 * @dsp_cfg_flags: set to 0
2623 struct iwm_phy_context_cmd {
2624 /* COMMON_INDEX_HDR_API_S_VER_1 */
2625 uint32_t id_and_color;
2627 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2628 uint32_t apply_time;
2629 uint32_t tx_param_color;
2630 struct iwm_fw_channel_info ci;
2631 uint32_t txchain_info;
2632 uint32_t rxchain_info;
2633 uint32_t acquisition_data;
2634 uint32_t dsp_cfg_flags;
2635 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2637 #define IWM_RX_INFO_PHY_CNT 8
2638 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2639 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2640 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2641 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2642 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2643 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2644 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2646 #define IWM_RX_INFO_AGC_IDX 1
2647 #define IWM_RX_INFO_RSSI_AB_IDX 2
2648 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2649 #define IWM_OFDM_AGC_A_POS 0
2650 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2651 #define IWM_OFDM_AGC_B_POS 7
2652 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2653 #define IWM_OFDM_AGC_CODE_POS 20
2654 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2655 #define IWM_OFDM_RSSI_A_POS 0
2656 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2657 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2658 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2659 #define IWM_OFDM_RSSI_B_POS 16
2660 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2661 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2664 * struct iwm_rx_phy_info - phy info
2665 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2666 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2667 * @cfg_phy_cnt: configurable DSP phy data byte count
2668 * @stat_id: configurable DSP phy data set ID
2670 * @system_timestamp: GP2 at on air rise
2671 * @timestamp: TSF at on air rise
2672 * @beacon_time_stamp: beacon at on-air rise
2673 * @phy_flags: general phy flags: band, modulation, ...
2674 * @channel: channel number
2675 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2676 * @rate_n_flags: IWM_RATE_MCS_*
2677 * @byte_count: frame's byte-count
2678 * @frame_time: frame's time on the air, based on byte count and frame rate
2680 * @mac_active_msk: what MACs were active when the frame was received
2682 * Before each Rx, the device sends this data. It contains PHY information
2683 * about the reception of the packet.
2685 struct iwm_rx_phy_info {
2686 uint8_t non_cfg_phy_cnt;
2687 uint8_t cfg_phy_cnt;
2690 uint32_t system_timestamp;
2692 uint32_t beacon_time_stamp;
2694 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2696 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2700 uint32_t byte_count;
2701 uint16_t mac_active_msk;
2702 uint16_t frame_time;
2705 struct iwm_rx_mpdu_res_start {
2706 uint16_t byte_count;
2711 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2712 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2713 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2714 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2715 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2716 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2717 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2718 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2719 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2720 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2722 enum iwm_rx_phy_flags {
2723 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2724 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2725 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2726 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2727 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2728 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2729 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2730 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2731 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2732 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2736 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2737 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2738 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2739 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2740 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2741 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2742 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2743 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2745 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2746 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2747 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2748 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2749 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2750 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2751 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2752 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2753 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2754 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2755 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2756 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2757 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2758 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2759 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2760 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2761 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2762 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2763 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2764 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2765 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2767 enum iwm_mvm_rx_status {
2768 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2769 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2770 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2771 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2772 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2773 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2774 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2775 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2776 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2777 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2778 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2779 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2780 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2781 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2782 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2783 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2784 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2785 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2786 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2787 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2788 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2789 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2790 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2791 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2792 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2793 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2794 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2798 * struct iwm_radio_version_notif - information on the radio version
2799 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2804 struct iwm_radio_version_notif {
2805 uint32_t radio_flavor;
2806 uint32_t radio_step;
2807 uint32_t radio_dash;
2808 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2810 enum iwm_card_state_flags {
2811 IWM_CARD_ENABLED = 0x00,
2812 IWM_HW_CARD_DISABLED = 0x01,
2813 IWM_SW_CARD_DISABLED = 0x02,
2814 IWM_CT_KILL_CARD_DISABLED = 0x04,
2815 IWM_HALT_CARD_DISABLED = 0x08,
2816 IWM_CARD_DISABLED_MSK = 0x0f,
2817 IWM_CARD_IS_RX_ON = 0x10,
2821 * struct iwm_radio_version_notif - information on the radio version
2822 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2823 * @flags: %iwm_card_state_flags
2825 struct iwm_card_state_notif {
2827 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2830 * struct iwm_missed_beacons_notif - information on missed beacons
2831 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2832 * @mac_id: interface ID
2833 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2834 * beacons since last RX.
2835 * @consec_missed_beacons: number of consecutive missed beacons
2836 * @num_expected_beacons:
2837 * @num_recvd_beacons:
2839 struct iwm_missed_beacons_notif {
2841 uint32_t consec_missed_beacons_since_last_rx;
2842 uint32_t consec_missed_beacons;
2843 uint32_t num_expected_beacons;
2844 uint32_t num_recvd_beacons;
2845 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2848 * struct iwm_mfuart_load_notif - mfuart image version & status
2849 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2850 * @installed_ver: installed image version
2851 * @external_ver: external image version
2852 * @status: MFUART loading status
2853 * @duration: MFUART loading time
2855 struct iwm_mfuart_load_notif {
2856 uint32_t installed_ver;
2857 uint32_t external_ver;
2860 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2863 * struct iwm_set_calib_default_cmd - set default value for calibration.
2864 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2865 * @calib_index: the calibration to set value for
2867 * @data: the value to set for the calibration result
2869 struct iwm_set_calib_default_cmd {
2870 uint16_t calib_index;
2873 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2875 #define IWM_MAX_PORT_ID_NUM 2
2876 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2879 * struct iwm_mcast_filter_cmd - configure multicast filter.
2880 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2881 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2882 * to identify network interface adopted in host-device IF.
2883 * It is used by FW as index in array of addresses. This array has
2884 * IWM_MAX_PORT_ID_NUM members.
2885 * @count: Number of MAC addresses in the array
2886 * @pass_all: Set 1 to pass all multicast packets.
2887 * @bssid: current association BSSID.
2888 * @addr_list: Place holder for array of MAC addresses.
2889 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2891 struct iwm_mcast_filter_cmd {
2897 uint8_t reserved[2];
2898 uint8_t addr_list[0];
2899 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2901 struct iwm_mvm_statistics_dbg {
2902 uint32_t burst_check;
2903 uint32_t burst_count;
2904 uint32_t wait_for_silence_timeout_cnt;
2905 uint32_t reserved[3];
2906 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2908 struct iwm_mvm_statistics_div {
2912 uint32_t probe_time;
2915 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2917 struct iwm_mvm_statistics_general_common {
2918 uint32_t temperature; /* radio temperature */
2919 uint32_t temperature_m; /* radio voltage */
2920 struct iwm_mvm_statistics_dbg dbg;
2921 uint32_t sleep_time;
2923 uint32_t slots_idle;
2924 uint32_t ttl_timestamp;
2925 struct iwm_mvm_statistics_div div;
2926 uint32_t rx_enable_counter;
2928 * num_of_sos_states:
2929 * count the number of times we have to re-tune
2930 * in order to get out of bad PHY status
2932 uint32_t num_of_sos_states;
2933 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2935 struct iwm_mvm_statistics_rx_non_phy {
2936 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2937 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2938 uint32_t non_bssid_frames; /* number of frames with BSSID that
2939 * doesn't belong to the STA BSSID */
2940 uint32_t filtered_frames; /* count frames that were dumped in the
2941 * filtering process */
2942 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2943 * our serving channel */
2944 uint32_t channel_beacons; /* beacons with our bss id and in our
2945 * serving channel */
2946 uint32_t num_missed_bcon; /* number of missed beacons */
2947 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2948 * ADC was in saturation */
2949 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2951 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2952 uint32_t interference_data_flag; /* flag for interference data
2953 * availability. 1 when data is
2955 uint32_t channel_load; /* counts RX Enable time in uSec */
2956 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2957 * and CCK) counter */
2958 uint32_t beacon_rssi_a;
2959 uint32_t beacon_rssi_b;
2960 uint32_t beacon_rssi_c;
2961 uint32_t beacon_energy_a;
2962 uint32_t beacon_energy_b;
2963 uint32_t beacon_energy_c;
2964 uint32_t num_bt_kills;
2966 uint32_t directed_data_mpdu;
2967 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2969 struct iwm_mvm_statistics_rx_phy {
2974 uint32_t overrun_err;
2975 uint32_t early_overrun_err;
2976 uint32_t crc32_good;
2977 uint32_t false_alarm_cnt;
2978 uint32_t fina_sync_err_cnt;
2979 uint32_t sfd_timeout;
2980 uint32_t fina_timeout;
2981 uint32_t unresponded_rts;
2982 uint32_t rxe_frame_limit_overrun;
2983 uint32_t sent_ack_cnt;
2984 uint32_t sent_cts_cnt;
2985 uint32_t sent_ba_rsp_cnt;
2986 uint32_t dsp_self_kill;
2987 uint32_t mh_format_err;
2988 uint32_t re_acq_main_rssi_sum;
2990 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2992 struct iwm_mvm_statistics_rx_ht_phy {
2994 uint32_t overrun_err;
2995 uint32_t early_overrun_err;
2996 uint32_t crc32_good;
2998 uint32_t mh_format_err;
2999 uint32_t agg_crc32_good;
3000 uint32_t agg_mpdu_cnt;
3002 uint32_t unsupport_mcs;
3003 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3005 #define IWM_MAX_CHAINS 3
3007 struct iwm_mvm_statistics_tx_non_phy_agg {
3008 uint32_t ba_timeout;
3009 uint32_t ba_reschedule_frames;
3010 uint32_t scd_query_agg_frame_cnt;
3011 uint32_t scd_query_no_agg;
3012 uint32_t scd_query_agg;
3013 uint32_t scd_query_mismatch;
3014 uint32_t frame_not_ready;
3016 uint32_t bt_prio_kill;
3017 uint32_t rx_ba_rsp_cnt;
3018 int8_t txpower[IWM_MAX_CHAINS];
3021 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3023 struct iwm_mvm_statistics_tx_channel_width {
3024 uint32_t ext_cca_narrow_ch20[1];
3025 uint32_t ext_cca_narrow_ch40[2];
3026 uint32_t ext_cca_narrow_ch80[3];
3027 uint32_t ext_cca_narrow_ch160[4];
3028 uint32_t last_tx_ch_width_indx;
3029 uint32_t rx_detected_per_ch_width[4];
3030 uint32_t success_per_ch_width[4];
3031 uint32_t fail_per_ch_width[4];
3032 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3034 struct iwm_mvm_statistics_tx {
3035 uint32_t preamble_cnt;
3036 uint32_t rx_detected_cnt;
3037 uint32_t bt_prio_defer_cnt;
3038 uint32_t bt_prio_kill_cnt;
3039 uint32_t few_bytes_cnt;
3040 uint32_t cts_timeout;
3041 uint32_t ack_timeout;
3042 uint32_t expected_ack_cnt;
3043 uint32_t actual_ack_cnt;
3044 uint32_t dump_msdu_cnt;
3045 uint32_t burst_abort_next_frame_mismatch_cnt;
3046 uint32_t burst_abort_missing_next_frame_cnt;
3047 uint32_t cts_timeout_collision;
3048 uint32_t ack_or_ba_timeout_collision;
3049 struct iwm_mvm_statistics_tx_non_phy_agg agg;
3050 struct iwm_mvm_statistics_tx_channel_width channel_width;
3051 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3054 struct iwm_mvm_statistics_bt_activity {
3055 uint32_t hi_priority_tx_req_cnt;
3056 uint32_t hi_priority_tx_denied_cnt;
3057 uint32_t lo_priority_tx_req_cnt;
3058 uint32_t lo_priority_tx_denied_cnt;
3059 uint32_t hi_priority_rx_req_cnt;
3060 uint32_t hi_priority_rx_denied_cnt;
3061 uint32_t lo_priority_rx_req_cnt;
3062 uint32_t lo_priority_rx_denied_cnt;
3063 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3065 struct iwm_mvm_statistics_general {
3066 struct iwm_mvm_statistics_general_common common;
3067 uint32_t beacon_filtered;
3068 uint32_t missed_beacons;
3069 int8_t beacon_filter_average_energy;
3070 int8_t beacon_filter_reason;
3071 int8_t beacon_filter_current_energy;
3072 int8_t beacon_filter_reserved;
3073 uint32_t beacon_filter_delta_time;
3074 struct iwm_mvm_statistics_bt_activity bt_activity;
3075 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3077 struct iwm_mvm_statistics_rx {
3078 struct iwm_mvm_statistics_rx_phy ofdm;
3079 struct iwm_mvm_statistics_rx_phy cck;
3080 struct iwm_mvm_statistics_rx_non_phy general;
3081 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
3082 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3085 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3087 * By default, uCode issues this notification after receiving a beacon
3088 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3089 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3091 * Statistics counters continue to increment beacon after beacon, but are
3092 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3093 * 0x9c with CLEAR_STATS bit set (see above).
3095 * uCode also issues this notification during scans. uCode clears statistics
3096 * appropriately so that each notification contains statistics for only the
3097 * one channel that has just been scanned.
3100 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3102 struct iwm_mvm_statistics_rx rx;
3103 struct iwm_mvm_statistics_tx tx;
3104 struct iwm_mvm_statistics_general general;
3107 /***********************************
3109 ***********************************/
3110 /* Smart Fifo state */
3112 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3116 IWM_SF_HW_NUM_STATES
3119 /* Smart Fifo possible scenario */
3120 enum iwm_sf_scenario {
3121 IWM_SF_SCENARIO_SINGLE_UNICAST,
3122 IWM_SF_SCENARIO_AGG_UNICAST,
3123 IWM_SF_SCENARIO_MULTICAST,
3124 IWM_SF_SCENARIO_BA_RESP,
3125 IWM_SF_SCENARIO_TX_RESP,
3129 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3130 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3132 /* smart FIFO default values */
3133 #define IWM_SF_W_MARK_SISO 4096
3134 #define IWM_SF_W_MARK_MIMO2 8192
3135 #define IWM_SF_W_MARK_MIMO3 6144
3136 #define IWM_SF_W_MARK_LEGACY 4096
3137 #define IWM_SF_W_MARK_SCAN 4096
3139 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3140 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3141 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3142 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3143 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3144 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3145 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3146 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3147 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3148 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3149 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3151 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3152 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3153 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3154 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3155 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3156 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3157 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3158 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3159 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3160 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3161 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3163 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3165 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3168 * Smart Fifo configuration command.
3169 * @state: smart fifo state, types listed in iwm_sf_state.
3170 * @watermark: Minimum allowed available free space in RXF for transient state.
3171 * @long_delay_timeouts: aging and idle timer values for each scenario
3172 * in long delay state.
3173 * @full_on_timeouts: timer values for each scenario in full on state.
3175 struct iwm_sf_cfg_cmd {
3177 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3178 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3179 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3180 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3187 * BEGIN mvm/fw-api-mac.h
3191 * The first MAC indices (starting from 0)
3192 * are available to the driver, AUX follows
3194 #define IWM_MAC_INDEX_AUX 4
3195 #define IWM_MAC_INDEX_MIN_DRIVER 0
3196 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3207 * enum iwm_mac_protection_flags - MAC context flags
3208 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3209 * this will require CCK RTS/CTS2self.
3210 * RTS/CTS will protect full burst time.
3211 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3212 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3213 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3215 enum iwm_mac_protection_flags {
3216 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3217 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3218 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3219 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3222 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3223 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3226 * enum iwm_mac_types - Supported MAC types
3227 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3228 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3229 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3230 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3231 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3232 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3233 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3234 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3235 * @IWM_FW_MAC_TYPE_GO: P2P GO
3236 * @IWM_FW_MAC_TYPE_TEST: ?
3237 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3239 enum iwm_mac_types {
3240 IWM_FW_MAC_TYPE_FIRST = 1,
3241 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3242 IWM_FW_MAC_TYPE_LISTENER,
3243 IWM_FW_MAC_TYPE_PIBSS,
3244 IWM_FW_MAC_TYPE_IBSS,
3245 IWM_FW_MAC_TYPE_BSS_STA,
3246 IWM_FW_MAC_TYPE_P2P_DEVICE,
3247 IWM_FW_MAC_TYPE_P2P_STA,
3249 IWM_FW_MAC_TYPE_TEST,
3250 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3251 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3254 * enum iwm_tsf_id - TSF hw timer ID
3255 * @IWM_TSF_ID_A: use TSF A
3256 * @IWM_TSF_ID_B: use TSF B
3257 * @IWM_TSF_ID_C: use TSF C
3258 * @IWM_TSF_ID_D: use TSF D
3259 * @IWM_NUM_TSF_IDS: number of TSF timers available
3266 IWM_NUM_TSF_IDS = 4,
3267 }; /* IWM_TSF_ID_API_E_VER_1 */
3270 * struct iwm_mac_data_ap - configuration data for AP MAC context
3271 * @beacon_time: beacon transmit time in system time
3272 * @beacon_tsf: beacon transmit time in TSF
3273 * @bi: beacon interval in TU
3274 * @bi_reciprocal: 2^32 / bi
3275 * @dtim_interval: dtim transmit time in TU
3276 * @dtim_reciprocal: 2^32 / dtim_interval
3277 * @mcast_qid: queue ID for multicast traffic
3278 * @beacon_template: beacon template ID
3280 struct iwm_mac_data_ap {
3281 uint32_t beacon_time;
3282 uint64_t beacon_tsf;
3284 uint32_t bi_reciprocal;
3285 uint32_t dtim_interval;
3286 uint32_t dtim_reciprocal;
3288 uint32_t beacon_template;
3289 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3292 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3293 * @beacon_time: beacon transmit time in system time
3294 * @beacon_tsf: beacon transmit time in TSF
3295 * @bi: beacon interval in TU
3296 * @bi_reciprocal: 2^32 / bi
3297 * @beacon_template: beacon template ID
3299 struct iwm_mac_data_ibss {
3300 uint32_t beacon_time;
3301 uint64_t beacon_tsf;
3303 uint32_t bi_reciprocal;
3304 uint32_t beacon_template;
3305 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3308 * struct iwm_mac_data_sta - configuration data for station MAC context
3309 * @is_assoc: 1 for associated state, 0 otherwise
3310 * @dtim_time: DTIM arrival time in system time
3311 * @dtim_tsf: DTIM arrival time in TSF
3312 * @bi: beacon interval in TU, applicable only when associated
3313 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3314 * @dtim_interval: DTIM interval in TU, applicable only when associated
3315 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3316 * @listen_interval: in beacon intervals, applicable only when associated
3317 * @assoc_id: unique ID assigned by the AP during association
3319 struct iwm_mac_data_sta {
3324 uint32_t bi_reciprocal;
3325 uint32_t dtim_interval;
3326 uint32_t dtim_reciprocal;
3327 uint32_t listen_interval;
3329 uint32_t assoc_beacon_arrive_time;
3330 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3333 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3334 * @ap: iwm_mac_data_ap struct with most config data
3335 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3336 * 0 indicates that there is no CT window.
3337 * @opp_ps_enabled: indicate that opportunistic PS allowed
3339 struct iwm_mac_data_go {
3340 struct iwm_mac_data_ap ap;
3342 uint32_t opp_ps_enabled;
3343 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3346 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3347 * @sta: iwm_mac_data_sta struct with most config data
3348 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3349 * 0 indicates that there is no CT window.
3351 struct iwm_mac_data_p2p_sta {
3352 struct iwm_mac_data_sta sta;
3354 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3357 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3358 * @stats_interval: interval in TU between statistics notifications to host.
3360 struct iwm_mac_data_pibss {
3361 uint32_t stats_interval;
3362 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3365 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3367 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3368 * other channels as well. This should be to true only in case that the
3369 * device is discoverable and there is an active GO. Note that setting this
3370 * field when not needed, will increase the number of interrupts and have
3371 * effect on the platform power, as this setting opens the Rx filters on
3374 struct iwm_mac_data_p2p_dev {
3375 uint32_t is_disc_extended;
3376 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3379 * enum iwm_mac_filter_flags - MAC context filter flags
3380 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3381 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3382 * control frames to the host
3383 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3384 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3385 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3386 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3387 * (in station mode when associated)
3388 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3389 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3390 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3392 enum iwm_mac_filter_flags {
3393 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3394 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3395 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3396 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3397 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3398 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3399 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3400 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3401 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3405 * enum iwm_mac_qos_flags - QoS flags
3406 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3407 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3408 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3411 enum iwm_mac_qos_flags {
3412 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3413 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3414 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3418 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3419 * @cw_min: Contention window, start value in numbers of slots.
3420 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3421 * @cw_max: Contention window, max value in numbers of slots.
3422 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3423 * @aifsn: Number of slots in Arbitration Interframe Space (before
3424 * performing random backoff timing prior to Tx). Device default 1.
3425 * @fifos_mask: FIFOs used by this MAC for this AC
3426 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3428 * One instance of this config struct for each of 4 EDCA access categories
3429 * in struct iwm_qosparam_cmd.
3431 * Device will automatically increase contention window by (2*CW) + 1 for each
3432 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3433 * value, to cap the CW value.
3441 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3444 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3445 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3446 * @id_and_color: ID and color of the MAC
3447 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3448 * @mac_type: one of IWM_FW_MAC_TYPE_*
3449 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3450 * @node_addr: MAC address
3451 * @bssid_addr: BSSID
3452 * @cck_rates: basic rates available for CCK
3453 * @ofdm_rates: basic rates available for OFDM
3454 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3455 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3456 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3457 * @filter_flags: combination of IWM_MAC_FILTER_*
3458 * @qos_flags: from IWM_MAC_QOS_FLG_*
3459 * @ac: one iwm_mac_qos configuration for each AC
3460 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3462 struct iwm_mac_ctx_cmd {
3463 /* COMMON_INDEX_HDR_API_S_VER_1 */
3464 uint32_t id_and_color;
3466 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3469 uint8_t node_addr[6];
3470 uint16_t reserved_for_node_addr;
3471 uint8_t bssid_addr[6];
3472 uint16_t reserved_for_bssid_addr;
3474 uint32_t ofdm_rates;
3475 uint32_t protection_flags;
3476 uint32_t cck_short_preamble;
3477 uint32_t short_slot;
3478 uint32_t filter_flags;
3479 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3481 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3482 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3484 struct iwm_mac_data_ap ap;
3485 struct iwm_mac_data_go go;
3486 struct iwm_mac_data_sta sta;
3487 struct iwm_mac_data_p2p_sta p2p_sta;
3488 struct iwm_mac_data_p2p_dev p2p_dev;
3489 struct iwm_mac_data_pibss pibss;
3490 struct iwm_mac_data_ibss ibss;
3492 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3494 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3498 return 0xFFFFFFFF / v;
3501 #define IWM_NONQOS_SEQ_GET 0x1
3502 #define IWM_NONQOS_SEQ_SET 0x2
3503 struct iwm_nonqos_seq_query_cmd {
3504 uint32_t get_set_flag;
3505 uint32_t mac_id_n_color;
3508 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3511 * END mvm/fw-api-mac.h
3515 * BEGIN mvm/fw-api-power.h
3518 /* Power Management Commands, Responses, Notifications */
3520 /* Radio LP RX Energy Threshold measured in dBm */
3521 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3522 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3523 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3526 * enum iwm_scan_flags - masks for power table command flags
3527 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3528 * receiver and transmitter. '0' - does not allow.
3529 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3530 * '1' Driver enables PM (use rest of parameters)
3531 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3532 * '1' PM could sleep over DTIM till listen Interval.
3533 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3534 * access categories are both delivery and trigger enabled.
3535 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3536 * PBW Snoozing enabled
3537 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3538 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3539 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3540 * detection enablement
3542 enum iwm_power_flags {
3543 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3544 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3545 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3546 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3547 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3548 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3549 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3550 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3553 #define IWM_POWER_VEC_SIZE 5
3556 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3557 * is used also with a new power API for device wide power settings.
3558 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3560 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3561 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3562 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3563 * set regardless of power scheme or current power state.
3564 * FW use this value also when PM is disabled.
3565 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3566 * PSM transition - legacy PM
3567 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3568 * PSM transition - legacy PM
3569 * @sleep_interval: not in use
3570 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3571 * is set. For example, if it is required to skip over
3572 * one DTIM, this value need to be set to 2 (DTIM periods).
3573 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3576 struct iwm_powertable_cmd {
3577 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3579 uint8_t keep_alive_seconds;
3580 uint8_t debug_flags;
3581 uint32_t rx_data_timeout;
3582 uint32_t tx_data_timeout;
3583 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3584 uint32_t skip_dtim_periods;
3585 uint32_t lprx_rssi_threshold;
3589 * enum iwm_device_power_flags - masks for device power command flags
3590 * @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3591 * receiver and transmitter. '0' - does not allow.
3593 enum iwm_device_power_flags {
3594 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3598 * struct iwm_device_power_cmd - device wide power command.
3599 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3601 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3603 struct iwm_device_power_cmd {
3604 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3610 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3611 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3612 * @id_and_color: MAC contex identifier
3613 * @flags: Power table command flags from POWER_FLAGS_*
3614 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3615 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3616 * set regardless of power scheme or current power state.
3617 * FW use this value also when PM is disabled.
3618 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3619 * PSM transition - legacy PM
3620 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3621 * PSM transition - legacy PM
3622 * @sleep_interval: not in use
3623 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3624 * is set. For example, if it is required to skip over
3625 * one DTIM, this value need to be set to 2 (DTIM periods).
3626 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3627 * PSM transition - uAPSD
3628 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3629 * PSM transition - uAPSD
3630 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3632 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3633 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3634 * from the AP [msec]
3635 * @snooze_window: A window of time in which PBW snoozing insures that all
3636 * packets received. It is also the minimum time from last
3637 * received unicast RX packet, before client stops snoozing
3640 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3641 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3642 * each corresponding AC.
3643 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3644 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3646 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3647 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3648 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3649 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3650 * @limited_ps_threshold:
3652 struct iwm_mac_power_cmd {
3653 /* CONTEXT_DESC_API_T_VER_1 */
3654 uint32_t id_and_color;
3656 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3658 uint16_t keep_alive_seconds;
3659 uint32_t rx_data_timeout;
3660 uint32_t tx_data_timeout;
3661 uint32_t rx_data_timeout_uapsd;
3662 uint32_t tx_data_timeout_uapsd;
3663 uint8_t lprx_rssi_threshold;
3664 uint8_t skip_dtim_periods;
3665 uint16_t snooze_interval;
3666 uint16_t snooze_window;
3667 uint8_t snooze_step;
3669 uint8_t uapsd_ac_flags;
3670 uint8_t uapsd_max_sp;
3671 uint8_t heavy_tx_thld_packets;
3672 uint8_t heavy_rx_thld_packets;
3673 uint8_t heavy_tx_thld_percentage;
3674 uint8_t heavy_rx_thld_percentage;
3675 uint8_t limited_ps_threshold;
3680 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3681 * associated AP is identified as improperly implementing uAPSD protocol.
3682 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3683 * @sta_id: index of station in uCode's station table - associated AP ID in
3686 struct iwm_uapsd_misbehaving_ap_notif {
3689 uint8_t reserved[3];
3693 * struct iwm_beacon_filter_cmd
3694 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3695 * @id_and_color: MAC contex identifier
3696 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3697 * to driver if delta in Energy values calculated for this and last
3698 * passed beacon is greater than this threshold. Zero value means that
3699 * the Energy change is ignored for beacon filtering, and beacon will
3700 * not be forced to be sent to driver regardless of this delta. Typical
3702 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3703 * Send beacon to driver if delta in Energy values calculated for this
3704 * and last passed beacon is greater than this threshold. Zero value
3705 * means that the Energy change is ignored for beacon filtering while in
3706 * Roaming state, typical energy delta 1dB.
3707 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3708 * calculated for current beacon is less than the threshold, use
3709 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3710 * Threshold. Typical energy threshold is -72dBm.
3711 * @bf_temp_threshold: This threshold determines the type of temperature
3712 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3713 * If the current temperature is above this threshold - Fast filter
3714 * will be used, If the current temperature is below this threshold -
3715 * Slow filter will be used.
3716 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3717 * calculated for this and the last passed beacon is greater than this
3718 * threshold. Zero value means that the temperature change is ignored for
3719 * beacon filtering; beacons will not be forced to be sent to driver
3720 * regardless of whether its temperature has been changed.
3721 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3722 * calculated for this and the last passed beacon is greater than this
3723 * threshold. Zero value means that the temperature change is ignored for
3724 * beacon filtering; beacons will not be forced to be sent to driver
3725 * regardless of whether its temperature has been changed.
3726 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3727 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3728 * for a specific period of time. Units: Beacons.
3729 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3730 * for a longer period of time then this escape-timeout. Units: Beacons.
3731 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3733 struct iwm_beacon_filter_cmd {
3734 uint32_t bf_energy_delta;
3735 uint32_t bf_roaming_energy_delta;
3736 uint32_t bf_roaming_state;
3737 uint32_t bf_temp_threshold;
3738 uint32_t bf_temp_fast_filter;
3739 uint32_t bf_temp_slow_filter;
3740 uint32_t bf_enable_beacon_filter;
3741 uint32_t bf_debug_flag;
3742 uint32_t bf_escape_timer;
3743 uint32_t ba_escape_timer;
3744 uint32_t ba_enable_beacon_abort;
3747 /* Beacon filtering and beacon abort */
3748 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3749 #define IWM_BF_ENERGY_DELTA_MAX 255
3750 #define IWM_BF_ENERGY_DELTA_MIN 0
3752 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3753 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3754 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3756 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3757 #define IWM_BF_ROAMING_STATE_MAX 255
3758 #define IWM_BF_ROAMING_STATE_MIN 0
3760 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3761 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3762 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3764 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3765 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3766 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3768 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3769 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3770 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3772 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3774 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3776 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3777 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3778 #define IWM_BF_ESCAPE_TIMER_MIN 0
3780 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3781 #define IWM_BA_ESCAPE_TIMER_D3 9
3782 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3783 #define IWM_BA_ESCAPE_TIMER_MIN 0
3785 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3787 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3788 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3789 .bf_roaming_energy_delta = \
3790 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3791 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3792 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3793 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3794 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3795 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3796 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3797 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3800 * END mvm/fw-api-power.h
3804 * BEGIN mvm/fw-api-rs.h
3808 * These serve as indexes into
3809 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3810 * TODO: avoid overlap between legacy and HT rates
3813 IWM_RATE_1M_INDEX = 0,
3814 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3818 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3820 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3821 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3822 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3823 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3826 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3828 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3830 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3832 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3834 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3836 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3837 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3839 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3840 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3841 IWM_RATE_MCS_8_INDEX,
3842 IWM_RATE_MCS_9_INDEX,
3843 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3844 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3845 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3848 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3850 /* fw API values for legacy bit rates, both OFDM and CCK */
3852 IWM_RATE_6M_PLCP = 13,
3853 IWM_RATE_9M_PLCP = 15,
3854 IWM_RATE_12M_PLCP = 5,
3855 IWM_RATE_18M_PLCP = 7,
3856 IWM_RATE_24M_PLCP = 9,
3857 IWM_RATE_36M_PLCP = 11,
3858 IWM_RATE_48M_PLCP = 1,
3859 IWM_RATE_54M_PLCP = 3,
3860 IWM_RATE_1M_PLCP = 10,
3861 IWM_RATE_2M_PLCP = 20,
3862 IWM_RATE_5M_PLCP = 55,
3863 IWM_RATE_11M_PLCP = 110,
3864 IWM_RATE_INVM_PLCP = -1,
3868 * rate_n_flags bit fields
3870 * The 32-bit value has different layouts in the low 8 bites depending on the
3871 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3872 * for CCK and OFDM).
3874 * High-throughput (HT) rate format
3875 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3876 * Very High-throughput (VHT) rate format
3877 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3878 * Legacy OFDM rate format for bits 7:0
3879 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3880 * Legacy CCK rate format for bits 7:0:
3881 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3884 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3885 #define IWM_RATE_MCS_HT_POS 8
3886 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3888 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3889 #define IWM_RATE_MCS_CCK_POS 9
3890 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3892 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3893 #define IWM_RATE_MCS_VHT_POS 26
3894 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3898 * High-throughput (HT) rate format for bits 7:0
3900 * 2-0: MCS rate base
3909 * 4-3: 0) Single stream (SISO)
3910 * 1) Dual stream (MIMO)
3911 * 2) Triple stream (MIMO)
3912 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3913 * (bits 7-6 are zero)
3915 * Together the low 5 bits work out to the MCS index because we don't
3916 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3917 * streams and 16-23 have three streams. We could also support MCS 32
3918 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3920 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3921 #define IWM_RATE_HT_MCS_NSS_POS 3
3922 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3924 /* Bit 10: (1) Use Green Field preamble */
3925 #define IWM_RATE_HT_MCS_GF_POS 10
3926 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3928 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3931 * Very High-throughput (VHT) rate format for bits 7:0
3933 * 3-0: VHT MCS (0-9)
3934 * 5-4: number of streams - 1:
3935 * 0) Single stream (SISO)
3936 * 1) Dual stream (MIMO)
3937 * 2) Triple stream (MIMO)
3940 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3941 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3942 #define IWM_RATE_VHT_MCS_NSS_POS 4
3943 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3946 * Legacy OFDM rate format for bits 7:0
3958 * Legacy CCK rate format for bits 7:0:
3959 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3967 #define IWM_RATE_LEGACY_RATE_MSK 0xff
3971 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3972 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3974 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3975 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3976 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3977 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3978 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3979 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3981 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3982 #define IWM_RATE_MCS_SGI_POS 13
3983 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3985 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3986 #define IWM_RATE_MCS_ANT_POS 14
3987 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3988 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3989 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3990 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3991 IWM_RATE_MCS_ANT_B_MSK)
3992 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3993 IWM_RATE_MCS_ANT_C_MSK)
3994 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3995 #define IWM_RATE_MCS_ANT_NUM 3
3997 /* Bit 17-18: (0) SS, (1) SS*2 */
3998 #define IWM_RATE_MCS_STBC_POS 17
3999 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4001 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4002 #define IWM_RATE_MCS_BF_POS 19
4003 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4005 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
4006 #define IWM_RATE_MCS_ZLF_POS 20
4007 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4009 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4010 #define IWM_RATE_MCS_DUP_POS 24
4011 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
4013 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
4014 #define IWM_RATE_MCS_LDPC_POS 27
4015 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
4018 /* Link Quality definitions */
4020 /* # entries in rate scale table to support Tx retries */
4021 #define IWM_LQ_MAX_RETRY_NUM 16
4023 /* Link quality command flags bit fields */
4025 /* Bit 0: (0) Don't use RTS (1) Use RTS */
4026 #define IWM_LQ_FLAG_USE_RTS_POS 0
4027 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4029 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4030 #define IWM_LQ_FLAG_COLOR_POS 1
4031 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4033 /* Bit 4-5: Tx RTS BW Signalling
4034 * (0) No RTS BW signalling
4035 * (1) Static BW signalling
4036 * (2) Dynamic BW signalling
4038 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4039 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4040 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4041 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4043 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4044 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4046 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4047 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4050 * struct iwm_lq_cmd - link quality command
4051 * @sta_id: station to update
4052 * @control: not used
4053 * @flags: combination of IWM_LQ_FLAG_*
4054 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4056 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4057 * Should be ANT_[ABC]
4058 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4059 * @initial_rate_index: first index from rs_table per AC category
4060 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4061 * value of 100 is one usec. Range is 100 to 8000
4062 * @agg_disable_start_th: try-count threshold for starting aggregation.
4063 * If a frame has higher try-count, it should not be selected for
4064 * starting an aggregation sequence.
4065 * @agg_frame_cnt_limit: max frame count in an aggregation.
4067 * 1: no aggregation (one frame per aggregation)
4068 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4069 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4070 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4071 * @bf_params: beam forming params, currently not used
4077 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4080 uint8_t single_stream_ant_msk;
4081 uint8_t dual_stream_ant_msk;
4082 uint8_t initial_rate_index[IWM_AC_NUM];
4083 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4084 uint16_t agg_time_limit;
4085 uint8_t agg_disable_start_th;
4086 uint8_t agg_frame_cnt_limit;
4088 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4090 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4093 * END mvm/fw-api-rs.h
4097 * BEGIN mvm/fw-api-tx.h
4101 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4102 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4103 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4104 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4105 * Otherwise, use rate_n_flags from the TX command
4106 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4107 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4108 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4109 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4110 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4111 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4112 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4113 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4114 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4115 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4116 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4117 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4118 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4119 * Should be set for beacons and probe responses
4120 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4121 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4122 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4123 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4124 * Should be set for 26/30 length MAC headers
4125 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4126 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4127 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4128 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4129 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4130 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4131 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4134 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4135 IWM_TX_CMD_FLG_ACK = (1 << 3),
4136 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4137 IWM_TX_CMD_FLG_BA = (1 << 5),
4138 IWM_TX_CMD_FLG_BAR = (1 << 6),
4139 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4140 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4141 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4142 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4143 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4144 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4145 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4146 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4147 IWM_TX_CMD_FLG_TSF = (1 << 16),
4148 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4149 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4150 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4151 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4152 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4153 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4154 IWM_TX_CMD_FLG_DUR = (1 << 25),
4155 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4156 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4157 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4158 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4159 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4162 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4163 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4164 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4165 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4167 enum iwm_tx_pm_timeouts {
4168 IWM_PM_FRAME_NONE = 0,
4169 IWM_PM_FRAME_MGMT = 2,
4170 IWM_PM_FRAME_ASSOC = 3,
4174 * TX command security control
4176 #define IWM_TX_CMD_SEC_WEP 0x01
4177 #define IWM_TX_CMD_SEC_CCM 0x02
4178 #define IWM_TX_CMD_SEC_TKIP 0x03
4179 #define IWM_TX_CMD_SEC_EXT 0x04
4180 #define IWM_TX_CMD_SEC_MSK 0x07
4181 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4182 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4183 #define IWM_TX_CMD_SEC_KEY128 0x08
4185 /* TODO: how does these values are OK with only 16 bit variable??? */
4187 * TX command next frame info
4189 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4190 * bit 3 - immediate ACK required
4191 * bit 4 - rate is taken from STA table
4192 * bit 5 - frame belongs to BA stream
4193 * bit 6 - immediate BA response expected
4195 * bits 8:15 - Station ID
4198 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4199 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4200 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4201 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4202 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4203 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4204 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4205 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4206 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4209 * TX command Frame life time in us - to be written in pm_frame_timeout
4211 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4212 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4213 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4214 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4217 * TID for non QoS frames - to be written in tid_tspec
4219 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4222 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4224 #define IWM_DEFAULT_TX_RETRY 15
4225 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4226 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
4227 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4228 #define IWM_LOW_RETRY_LIMIT 7
4230 /* TODO: complete documentation for try_cnt and btkill_cnt */
4232 * struct iwm_tx_cmd - TX command struct to FW
4233 * ( IWM_TX_CMD = 0x1c )
4234 * @len: in bytes of the payload, see below for details
4235 * @next_frame_len: same as len, but for next frame (0 if not applicable)
4236 * Used for fragmentation and bursting, but not in 11n aggregation.
4237 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4238 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4239 * cleared. Combination of IWM_RATE_MCS_*
4240 * @sta_id: index of destination station in FW station table
4241 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4242 * @initial_rate_index: index into the rate table for initial TX attempt.
4243 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4244 * @key: security key
4245 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4246 * @life_time: frame life time (usecs??)
4247 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4248 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4249 * @dram_msb_ptr: upper bits of the scratch physical address
4250 * @rts_retry_limit: max attempts for RTS
4251 * @data_retry_limit: max attempts to send the data packet
4252 * @tid_spec: TID/tspec
4253 * @pm_frame_timeout: PM TX frame timeout
4254 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4255 * specified by HCCA protocol
4257 * The byte count (both len and next_frame_len) includes MAC header
4258 * (24/26/30/32 bytes)
4259 * + 2 bytes pad if 26/30 header size
4260 * + 8 byte IV for CCM or TKIP (not used for WEP)
4262 * + 8-byte MIC (not used for CCM/WEP)
4263 * It does not include post-MAC padding, i.e.,
4264 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4265 * Range of len: 14-2342 bytes.
4267 * After the struct fields the MAC header is placed, plus any padding,
4268 * and then the actial payload.
4272 uint16_t next_frame_len;
4278 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4279 uint32_t rate_n_flags;
4282 uint8_t initial_rate_index;
4285 uint16_t next_frame_flags;
4288 uint32_t dram_lsb_ptr;
4289 uint8_t dram_msb_ptr;
4290 uint8_t rts_retry_limit;
4291 uint8_t data_retry_limit;
4293 uint16_t pm_frame_timeout;
4294 uint16_t driver_txop;
4296 struct ieee80211_frame hdr[0];
4297 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4300 * TX response related data
4304 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4305 * @IWM_TX_STATUS_SUCCESS:
4306 * @IWM_TX_STATUS_DIRECT_DONE:
4307 * @IWM_TX_STATUS_POSTPONE_DELAY:
4308 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4309 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4310 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4311 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4312 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4313 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4314 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4315 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4316 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4317 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4318 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4319 * @IWM_TX_STATUS_FAIL_DEST_PS:
4320 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4321 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4322 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4323 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4324 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4325 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4326 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4327 * @IWM_TX_STATUS_FAIL_FW_DROP:
4328 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4330 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4332 * @IWM_TX_MODE_NO_BURST:
4333 * @IWM_TX_MODE_IN_BURST_SEQ:
4334 * @IWM_TX_MODE_FIRST_IN_BURST:
4335 * @IWM_TX_QUEUE_NUM_MSK:
4337 * Valid only if frame_count =1
4338 * TODO: complete documentation
4340 enum iwm_tx_status {
4341 IWM_TX_STATUS_MSK = 0x000000ff,
4342 IWM_TX_STATUS_SUCCESS = 0x01,
4343 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4345 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4346 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4347 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4348 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4349 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4351 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4352 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4353 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4354 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4355 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4356 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4357 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4358 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4359 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4360 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4361 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4362 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4363 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4364 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4365 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4366 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4367 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4368 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4369 IWM_TX_MODE_MSK = 0x00000f00,
4370 IWM_TX_MODE_NO_BURST = 0x00000000,
4371 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4372 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4373 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4374 IWM_TX_NARROW_BW_MSK = 0x00060000,
4375 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4376 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4377 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4381 * enum iwm_tx_agg_status - TX aggregation status
4382 * @IWM_AGG_TX_STATE_STATUS_MSK:
4383 * @IWM_AGG_TX_STATE_TRANSMITTED:
4384 * @IWM_AGG_TX_STATE_UNDERRUN:
4385 * @IWM_AGG_TX_STATE_BT_PRIO:
4386 * @IWM_AGG_TX_STATE_FEW_BYTES:
4387 * @IWM_AGG_TX_STATE_ABORT:
4388 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4389 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4390 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4391 * @IWM_AGG_TX_STATE_SCD_QUERY:
4392 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4393 * @IWM_AGG_TX_STATE_RESPONSE:
4394 * @IWM_AGG_TX_STATE_DUMP_TX:
4395 * @IWM_AGG_TX_STATE_DELAY_TX:
4396 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4397 * occur if tx failed for this frame when it was a member of a previous
4398 * aggregation block). If rate scaling is used, retry count indicates the
4399 * rate table entry used for all frames in the new agg.
4400 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4403 * TODO: complete documentation
4405 enum iwm_tx_agg_status {
4406 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4407 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4408 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4409 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4410 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4411 IWM_AGG_TX_STATE_ABORT = 0x008,
4412 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4413 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4414 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4415 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4416 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4417 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4418 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4419 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4420 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4421 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4424 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4425 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4426 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4429 * The mask below describes a status where we are absolutely sure that the MPDU
4430 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4431 * written the bytes to the TXE, but we know nothing about what the DSP did.
4433 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4434 IWM_AGG_TX_STATE_ABORT | \
4435 IWM_AGG_TX_STATE_SCD_QUERY)
4438 * IWM_REPLY_TX = 0x1c (response)
4440 * This response may be in one of two slightly different formats, indicated
4441 * by the frame_count field:
4443 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4444 * frame. Multiple attempts, at various bit rates, may have been made for
4447 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4448 * frames that used block-acknowledge. All frames were transmitted at
4449 * same rate. Rate scaling may have been used if first frame in this new
4450 * agg block failed in previous agg block(s).
4452 * Note that, for aggregation, ACK (block-ack) status is not delivered
4453 * here; block-ack has not been received by the time the device records
4455 * This status relates to reasons the tx might have been blocked or aborted
4456 * within the device, rather than whether it was received successfully by
4457 * the destination station.
4461 * struct iwm_agg_tx_status - per packet TX aggregation status
4462 * @status: enum iwm_tx_agg_status
4463 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4465 struct iwm_agg_tx_status {
4471 * definitions for initial rate index field
4472 * bits [3:0] initial rate index
4473 * bits [6:4] rate table color, used for the initial rate
4474 * bit-7 invalid rate indication
4476 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4477 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4478 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4480 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4481 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4484 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4485 * ( IWM_REPLY_TX = 0x1c )
4486 * @frame_count: 1 no aggregation, >1 aggregation
4487 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4488 * @failure_rts: num of failures due to unsuccessful RTS
4489 * @failure_frame: num failures due to no ACK (unused for agg)
4490 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4491 * Tx of all the batch. IWM_RATE_MCS_*
4492 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4493 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4495 * @pa_status: tx power info
4496 * @pa_integ_res_a: tx power info
4497 * @pa_integ_res_b: tx power info
4498 * @pa_integ_res_c: tx power info
4499 * @measurement_req_id: tx power info
4500 * @tfd_info: TFD information set by the FH
4501 * @seq_ctl: sequence control from the Tx cmd
4502 * @byte_cnt: byte count from the Tx cmd
4503 * @tlc_info: TLC rate info
4504 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4505 * @frame_ctrl: frame control
4506 * @status: for non-agg: frame status IWM_TX_STATUS_*
4507 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4508 * follow this one, up to frame_count.
4510 * After the array of statuses comes the SSN of the SCD. Look at
4511 * %iwm_mvm_get_scd_ssn for more details.
4513 struct iwm_mvm_tx_resp {
4514 uint8_t frame_count;
4515 uint8_t bt_kill_count;
4516 uint8_t failure_rts;
4517 uint8_t failure_frame;
4518 uint32_t initial_rate;
4519 uint16_t wireless_media_time;
4522 uint8_t pa_integ_res_a[3];
4523 uint8_t pa_integ_res_b[3];
4524 uint8_t pa_integ_res_c[3];
4525 uint16_t measurement_req_id;
4533 uint16_t frame_ctrl;
4535 struct iwm_agg_tx_status status;
4536 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4539 * struct iwm_mvm_ba_notif - notifies about reception of BA
4540 * ( IWM_BA_NOTIF = 0xc5 )
4541 * @sta_addr_lo32: lower 32 bits of the MAC address
4542 * @sta_addr_hi16: upper 16 bits of the MAC address
4543 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4544 * @tid: tid of the session
4546 * @bitmap: the bitmap of the BA notification as seen in the air
4547 * @scd_flow: the tx queue this BA relates to
4548 * @scd_ssn: the index of the last contiguously sent packet
4549 * @txed: number of Txed frames in this batch
4550 * @txed_2_done: number of Acked frames in this batch
4552 struct iwm_mvm_ba_notif {
4553 uint32_t sta_addr_lo32;
4554 uint16_t sta_addr_hi16;
4564 uint8_t txed_2_done;
4569 * struct iwm_mac_beacon_cmd - beacon template command
4570 * @tx: the tx commands associated with the beacon frame
4571 * @template_id: currently equal to the mac context id of the coresponding
4573 * @tim_idx: the offset of the tim IE in the beacon
4574 * @tim_size: the length of the tim IE
4575 * @frame: the template of the beacon frame
4577 struct iwm_mac_beacon_cmd {
4578 struct iwm_tx_cmd tx;
4579 uint32_t template_id;
4582 struct ieee80211_frame frame[0];
4585 struct iwm_beacon_notif {
4586 struct iwm_mvm_tx_resp beacon_notify_hdr;
4588 uint32_t ibss_mgr_status;
4592 * enum iwm_dump_control - dump (flush) control flags
4593 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4594 * and the TFD queues are empty.
4596 enum iwm_dump_control {
4597 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4601 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4602 * @queues_ctl: bitmap of queues to flush
4603 * @flush_ctl: control flags
4604 * @reserved: reserved
4606 struct iwm_tx_path_flush_cmd {
4607 uint32_t queues_ctl;
4610 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4613 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4614 * @tx_resp: the Tx response from the fw (agg or non-agg)
4616 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4617 * it can't know that everything will go well until the end of the AMPDU, it
4618 * can't know in advance the number of MPDUs that will be sent in the current
4619 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4620 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4621 * of the batch. This is why the SSN of the SCD is written at the end of the
4622 * whole struct at a variable offset. This function knows how to cope with the
4623 * variable offset and returns the SSN of the SCD.
4625 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4627 return le32_to_cpup((uint32_t *)&tx_resp->status +
4628 tx_resp->frame_count) & 0xfff;
4632 * END mvm/fw-api-tx.h
4636 * BEGIN mvm/fw-api-scan.h
4640 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4642 * @sta_id: station id
4644 * @scd_queue: scheduler queue to confiug
4645 * @enable: 1 queue enable, 0 queue disable
4646 * @aggregate: 1 aggregated queue, 0 otherwise
4647 * @tx_fifo: %enum iwm_mvm_tx_fifo
4648 * @window: BA window size
4649 * @ssn: SSN for the BA agreement
4651 struct iwm_scd_txq_cfg_cmd {
4662 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4665 * struct iwm_scd_txq_cfg_rsp
4666 * @token: taken from the command
4667 * @sta_id: station id from the command
4668 * @tid: tid from the command
4669 * @scd_queue: scd_queue from the command
4671 struct iwm_scd_txq_cfg_rsp {
4676 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4679 /* Scan Commands, Responses, Notifications */
4681 /* Masks for iwm_scan_channel.type flags */
4682 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
4683 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1)
4685 /* Max number of IEs for direct SSID scans in a command */
4686 #define IWM_PROBE_OPTION_MAX 20
4689 * struct iwm_ssid_ie - directed scan network information element
4691 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4692 * selected by "type" bit field in struct iwm_scan_channel;
4693 * each channel may select different ssids from among the 20 entries.
4694 * SSID IEs get transmitted in reverse order of entry.
4696 struct iwm_ssid_ie {
4699 uint8_t ssid[IEEE80211_NWID_LEN];
4700 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4703 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4704 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4705 #define IWM_SCAN_MAX_PROFILES 11
4706 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4708 /* Default watchdog (in MS) for scheduled scan iteration */
4709 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4711 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4712 #define IWM_CAN_ABORT_STATUS 1
4714 #define IWM_FULL_SCAN_MULTIPLIER 5
4715 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4716 #define IWM_MAX_SCHED_SCAN_PLANS 2
4719 * iwm_scan_schedule_lmac - schedule of scan offload
4720 * @delay: delay between iterations, in seconds.
4721 * @iterations: num of scan iterations
4722 * @full_scan_mul: number of partial scans before each full scan
4724 struct iwm_scan_schedule_lmac {
4727 uint8_t full_scan_mul;
4728 } __packed; /* SCAN_SCHEDULE_API_S */
4731 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
4732 * @tx_flags: combination of TX_CMD_FLG_*
4733 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
4734 * cleared. Combination of RATE_MCS_*
4735 * @sta_id: index of destination station in FW station table
4736 * @reserved: for alignment and future use
4738 struct iwm_scan_req_tx_cmd {
4740 uint32_t rate_n_flags;
4742 uint8_t reserved[3];
4745 enum iwm_scan_channel_flags_lmac {
4746 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
4747 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
4751 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
4752 * @flags: bits 1-20: directed scan to i'th ssid
4753 * other bits &enum iwm_scan_channel_flags_lmac
4754 * @channel_number: channel number 1-13 etc
4755 * @iter_count: scan iteration on this channel
4756 * @iter_interval: interval in seconds between iterations on one channel
4758 struct iwm_scan_channel_cfg_lmac {
4760 uint16_t channel_num;
4761 uint16_t iter_count;
4762 uint32_t iter_interval;
4766 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
4767 * @offset: offset in the data block
4768 * @len: length of the segment
4770 struct iwm_scan_probe_segment {
4775 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
4776 * @mac_header: first (and common) part of the probe
4777 * @band_data: band specific data
4778 * @common_data: last (and common) part of the probe
4779 * @buf: raw data block
4781 struct iwm_scan_probe_req {
4782 struct iwm_scan_probe_segment mac_header;
4783 struct iwm_scan_probe_segment band_data[2];
4784 struct iwm_scan_probe_segment common_data;
4785 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
4788 enum iwm_scan_channel_flags {
4789 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
4790 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
4791 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
4794 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
4795 * @flags: enum iwm_scan_channel_flags
4796 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
4798 * 1 - EBS is disabled.
4799 * 2 - every second scan will be full scan(and so on).
4801 struct iwm_scan_channel_opt {
4803 uint16_t non_ebs_ratio;
4807 * iwm_mvm_lmac_scan_flags
4808 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
4809 * without filtering.
4810 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
4811 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
4812 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
4813 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
4814 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
4815 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
4816 * and DS parameter set IEs into probe requests.
4817 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
4819 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
4821 enum iwm_mvm_lmac_scan_flags {
4822 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
4823 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
4824 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
4825 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
4826 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
4827 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
4828 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
4829 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
4830 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
4833 enum iwm_scan_priority {
4834 IWM_SCAN_PRIORITY_LOW,
4835 IWM_SCAN_PRIORITY_MEDIUM,
4836 IWM_SCAN_PRIORITY_HIGH,
4840 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
4841 * @reserved1: for alignment and future use
4842 * @channel_num: num of channels to scan
4843 * @active-dwell: dwell time for active channels
4844 * @passive-dwell: dwell time for passive channels
4845 * @fragmented-dwell: dwell time for fragmented passive scan
4846 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
4847 * @reserved2: for alignment and future use
4848 * @rx_chain_selct: PHY_RX_CHAIN_* flags
4849 * @scan_flags: &enum iwm_mvm_lmac_scan_flags
4850 * @max_out_time: max time (in TU) to be out of associated channel
4851 * @suspend_time: pause scan this long (TUs) when returning to service channel
4852 * @flags: RXON flags
4853 * @filter_flags: RXON filter
4854 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
4855 * @direct_scan: list of SSIDs for directed active scan
4856 * @scan_prio: enum iwm_scan_priority
4857 * @iter_num: number of scan iterations
4858 * @delay: delay in seconds before first iteration
4859 * @schedule: two scheduling plans. The first one is finite, the second one can
4861 * @channel_opt: channel optimization options, for full and partial scan
4862 * @data: channel configuration and probe request packet.
4864 struct iwm_scan_req_lmac {
4865 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
4868 uint8_t active_dwell;
4869 uint8_t passive_dwell;
4870 uint8_t fragmented_dwell;
4871 uint8_t extended_dwell;
4873 uint16_t rx_chain_select;
4874 uint32_t scan_flags;
4875 uint32_t max_out_time;
4876 uint32_t suspend_time;
4877 /* RX_ON_FLAGS_API_S_VER_1 */
4879 uint32_t filter_flags;
4880 struct iwm_scan_req_tx_cmd tx_cmd[2];
4881 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4883 /* SCAN_REQ_PERIODIC_PARAMS_API_S */
4886 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
4887 struct iwm_scan_channel_opt channel_opt[2];
4892 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
4893 * @last_schedule_line: last schedule line executed (fast or regular)
4894 * @last_schedule_iteration: last scan iteration executed before scan abort
4895 * @status: enum iwm_scan_offload_complete_status
4896 * @ebs_status: EBS success status &enum iwm_scan_ebs_status
4897 * @time_after_last_iter; time in seconds elapsed after last iteration
4899 struct iwm_periodic_scan_complete {
4900 uint8_t last_schedule_line;
4901 uint8_t last_schedule_iteration;
4904 uint32_t time_after_last_iter;
4908 /* How many statistics are gathered for each channel */
4909 #define IWM_SCAN_RESULTS_STATISTICS 1
4912 * enum iwm_scan_complete_status - status codes for scan complete notifications
4913 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4914 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4915 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4916 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4917 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4918 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4919 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4920 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4921 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4922 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4924 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4926 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4928 enum iwm_scan_complete_status {
4929 IWM_SCAN_COMP_STATUS_OK = 0x1,
4930 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4931 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4932 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4933 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4934 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4935 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4936 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4937 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4938 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4939 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4940 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4944 * struct iwm_scan_results_notif - scan results for one channel
4945 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4946 * @channel: which channel the results are from
4947 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4948 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4949 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4950 * @duration: duration spent in channel, in usecs
4951 * @statistics: statistics gathered for this channel
4953 struct iwm_scan_results_notif {
4956 uint8_t probe_status;
4957 uint8_t num_probe_not_sent;
4959 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4960 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4962 enum iwm_scan_framework_client {
4963 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4964 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4965 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4969 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4970 * @ssid: MAC address to filter out
4971 * @reported_rssi: AP rssi reported to the host
4972 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4974 struct iwm_scan_offload_blacklist {
4975 uint8_t ssid[IEEE80211_ADDR_LEN];
4976 uint8_t reported_rssi;
4977 uint8_t client_bitmap;
4980 enum iwm_scan_offload_network_type {
4981 IWM_NETWORK_TYPE_BSS = 1,
4982 IWM_NETWORK_TYPE_IBSS = 2,
4983 IWM_NETWORK_TYPE_ANY = 3,
4986 enum iwm_scan_offload_band_selection {
4987 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4988 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4989 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4993 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4994 * @ssid_index: index to ssid list in fixed part
4995 * @unicast_cipher: encryption olgorithm to match - bitmap
4996 * @aut_alg: authentication olgorithm to match - bitmap
4997 * @network_type: enum iwm_scan_offload_network_type
4998 * @band_selection: enum iwm_scan_offload_band_selection
4999 * @client_bitmap: clients waiting for match - enum scan_framework_client
5001 struct iwm_scan_offload_profile {
5003 uint8_t unicast_cipher;
5005 uint8_t network_type;
5006 uint8_t band_selection;
5007 uint8_t client_bitmap;
5008 uint8_t reserved[2];
5012 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
5013 * @blaclist: AP list to filter off from scan results
5014 * @profiles: profiles to search for match
5015 * @blacklist_len: length of blacklist
5016 * @num_profiles: num of profiles in the list
5017 * @match_notify: clients waiting for match found notification
5018 * @pass_match: clients waiting for the results
5019 * @active_clients: active clients bitmap - enum scan_framework_client
5020 * @any_beacon_notify: clients waiting for match notification without match
5022 struct iwm_scan_offload_profile_cfg {
5023 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
5024 uint8_t blacklist_len;
5025 uint8_t num_profiles;
5026 uint8_t match_notify;
5028 uint8_t active_clients;
5029 uint8_t any_beacon_notify;
5030 uint8_t reserved[2];
5033 enum iwm_scan_offload_complete_status {
5034 IWM_SCAN_OFFLOAD_COMPLETED = 1,
5035 IWM_SCAN_OFFLOAD_ABORTED = 2,
5038 enum iwm_scan_ebs_status {
5039 IWM_SCAN_EBS_SUCCESS,
5040 IWM_SCAN_EBS_FAILED,
5041 IWM_SCAN_EBS_CHAN_NOT_FOUND,
5042 IWM_SCAN_EBS_INACTIVE,
5046 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5047 * SCAN_COMPLETE_NTF_API_S_VER_3
5048 * @scanned_channels: number of channels scanned (and number of valid results)
5049 * @status: one of SCAN_COMP_STATUS_*
5050 * @bt_status: BT on/off status
5051 * @last_channel: last channel that was scanned
5052 * @tsf_low: TSF timer (lower half) in usecs
5053 * @tsf_high: TSF timer (higher half) in usecs
5054 * @results: an array of scan results, only "scanned_channels" of them are valid
5056 struct iwm_lmac_scan_complete_notif {
5057 uint8_t scanned_channels;
5060 uint8_t last_channel;
5063 struct iwm_scan_results_notif results[];
5068 * END mvm/fw-api-scan.h
5072 * BEGIN mvm/fw-api-sta.h
5077 /* The maximum of either of these cannot exceed 8, because we use an
5078 * 8-bit mask (see IWM_MVM_SCAN_MASK).
5080 #define IWM_MVM_MAX_UMAC_SCANS 8
5081 #define IWM_MVM_MAX_LMAC_SCANS 1
5083 enum iwm_scan_config_flags {
5084 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5085 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5086 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5087 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5088 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5089 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5090 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5091 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5092 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5093 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5094 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5095 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5096 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5097 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5098 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5099 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5100 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5101 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5103 /* Bits 26-31 are for num of channels in channel_array */
5104 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5107 enum iwm_scan_config_rates {
5108 /* OFDM basic rates */
5109 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5110 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5111 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5112 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5113 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5114 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5115 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5116 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5117 /* CCK basic rates */
5118 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5119 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5120 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5121 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5123 /* Bits 16-27 are for supported rates */
5124 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5127 enum iwm_channel_flags {
5128 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5129 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5130 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5131 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5135 * struct iwm_scan_config
5136 * @flags: enum scan_config_flags
5137 * @tx_chains: valid_tx antenna - ANT_* definitions
5138 * @rx_chains: valid_rx antenna - ANT_* definitions
5139 * @legacy_rates: default legacy rates - enum scan_config_rates
5140 * @out_of_channel_time: default max out of serving channel time
5141 * @suspend_time: default max suspend time
5142 * @dwell_active: default dwell time for active scan
5143 * @dwell_passive: default dwell time for passive scan
5144 * @dwell_fragmented: default dwell time for fragmented scan
5145 * @dwell_extended: default dwell time for channels 1, 6 and 11
5146 * @mac_addr: default mac address to be used in probes
5147 * @bcast_sta_id: the index of the station in the fw
5148 * @channel_flags: default channel flags - enum iwm_channel_flags
5149 * scan_config_channel_flag
5150 * @channel_array: default supported channels
5152 struct iwm_scan_config {
5156 uint32_t legacy_rates;
5157 uint32_t out_of_channel_time;
5158 uint32_t suspend_time;
5159 uint8_t dwell_active;
5160 uint8_t dwell_passive;
5161 uint8_t dwell_fragmented;
5162 uint8_t dwell_extended;
5163 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5164 uint8_t bcast_sta_id;
5165 uint8_t channel_flags;
5166 uint8_t channel_array[];
5167 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5170 * iwm_umac_scan_flags
5171 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5172 * can be preempted by other scan requests with higher priority.
5173 * The low priority scan will be resumed when the higher proirity scan is
5175 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5178 enum iwm_umac_scan_flags {
5179 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5180 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5183 enum iwm_umac_scan_uid_offsets {
5184 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5185 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5188 enum iwm_umac_scan_general_flags {
5189 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5190 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5191 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5192 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5193 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5194 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5195 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5196 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5197 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5198 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5199 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5203 * struct iwm_scan_channel_cfg_umac
5204 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5205 * @channel_num: channel number 1-13 etc.
5206 * @iter_count: repetition count for the channel.
5207 * @iter_interval: interval between two scan iterations on one channel.
5209 struct iwm_scan_channel_cfg_umac {
5211 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5213 uint8_t channel_num;
5215 uint16_t iter_interval;
5216 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5219 * struct iwm_scan_umac_schedule
5220 * @interval: interval in seconds between scan iterations
5221 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5222 * @reserved: for alignment and future use
5224 struct iwm_scan_umac_schedule {
5228 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5231 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5232 * parameters following channels configuration array.
5233 * @schedule: two scheduling plans.
5234 * @delay: delay in TUs before starting the first scan iteration
5235 * @reserved: for future use and alignment
5236 * @preq: probe request with IEs blocks
5237 * @direct_scan: list of SSIDs for directed active scan
5239 struct iwm_scan_req_umac_tail {
5240 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5241 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5244 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5245 struct iwm_scan_probe_req preq;
5246 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5250 * struct iwm_scan_req_umac
5251 * @flags: &enum iwm_umac_scan_flags
5252 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5253 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5254 * @general_flags: &enum iwm_umac_scan_general_flags
5255 * @extended_dwell: dwell time for channels 1, 6 and 11
5256 * @active_dwell: dwell time for active scan
5257 * @passive_dwell: dwell time for passive scan
5258 * @fragmented_dwell: dwell time for fragmented passive scan
5259 * @max_out_time: max out of serving channel time
5260 * @suspend_time: max suspend time
5261 * @scan_priority: scan internal prioritization &enum iwm_scan_priority
5262 * @channel_flags: &enum iwm_scan_channel_flags
5263 * @n_channels: num of channels in scan request
5264 * @reserved: for future use and alignment
5265 * @data: &struct iwm_scan_channel_cfg_umac and
5266 * &struct iwm_scan_req_umac_tail
5268 struct iwm_scan_req_umac {
5271 uint32_t ooc_priority;
5272 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5273 uint32_t general_flags;
5274 uint8_t extended_dwell;
5275 uint8_t active_dwell;
5276 uint8_t passive_dwell;
5277 uint8_t fragmented_dwell;
5278 uint32_t max_out_time;
5279 uint32_t suspend_time;
5280 uint32_t scan_priority;
5281 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5282 uint8_t channel_flags;
5286 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5289 * struct iwm_umac_scan_abort
5290 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5293 struct iwm_umac_scan_abort {
5296 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5299 * struct iwm_umac_scan_complete
5300 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5301 * @last_schedule: last scheduling line
5302 * @last_iter: last scan iteration number
5303 * @scan status: &enum iwm_scan_offload_complete_status
5304 * @ebs_status: &enum iwm_scan_ebs_status
5305 * @time_from_last_iter: time elapsed from last iteration
5306 * @reserved: for future use
5308 struct iwm_umac_scan_complete {
5310 uint8_t last_schedule;
5314 uint32_t time_from_last_iter;
5316 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5318 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5320 * struct iwm_scan_offload_profile_match - match information
5321 * @bssid: matched bssid
5322 * @channel: channel where the match occurred
5324 * @matching_feature:
5325 * @matching_channels: bitmap of channels that matched, referencing
5326 * the channels passed in tue scan offload request
5328 struct iwm_scan_offload_profile_match {
5329 uint8_t bssid[IEEE80211_ADDR_LEN];
5333 uint8_t matching_feature;
5334 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5335 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5338 * struct iwm_scan_offload_profiles_query - match results query response
5339 * @matched_profiles: bitmap of matched profiles, referencing the
5340 * matches passed in the scan offload request
5341 * @last_scan_age: age of the last offloaded scan
5342 * @n_scans_done: number of offloaded scans done
5343 * @gp2_d0u: GP2 when D0U occurred
5344 * @gp2_invoked: GP2 when scan offload was invoked
5345 * @resume_while_scanning: not used
5346 * @self_recovery: obsolete
5347 * @reserved: reserved
5348 * @matches: array of match information, one for each match
5350 struct iwm_scan_offload_profiles_query {
5351 uint32_t matched_profiles;
5352 uint32_t last_scan_age;
5353 uint32_t n_scans_done;
5355 uint32_t gp2_invoked;
5356 uint8_t resume_while_scanning;
5357 uint8_t self_recovery;
5359 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5360 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5363 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5364 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5365 * @scanned_channels: number of channels scanned and number of valid elements in
5367 * @status: one of SCAN_COMP_STATUS_*
5368 * @bt_status: BT on/off status
5369 * @last_channel: last channel that was scanned
5370 * @tsf_low: TSF timer (lower half) in usecs
5371 * @tsf_high: TSF timer (higher half) in usecs
5372 * @results: array of scan results, only "scanned_channels" of them are valid
5374 struct iwm_umac_scan_iter_complete_notif {
5376 uint8_t scanned_channels;
5379 uint8_t last_channel;
5382 struct iwm_scan_results_notif results[];
5383 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5385 /* Please keep this enum *SORTED* by hex value.
5386 * Needed for binary search, otherwise a warning will be triggered.
5388 enum iwm_scan_subcmd_ids {
5389 IWM_GSCAN_START_CMD = 0x0,
5390 IWM_GSCAN_STOP_CMD = 0x1,
5391 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5392 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5393 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5394 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5395 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5396 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5397 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5403 * enum iwm_sta_flags - flags for the ADD_STA host command
5404 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5405 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5406 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5407 * @IWM_STA_FLG_PS: set if STA is in Power Save
5408 * @IWM_STA_FLG_INVALID: set if STA is invalid
5409 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5410 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5411 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5412 * @IWM_STA_FLG_PAN: STA is for PAN interface
5413 * @IWM_STA_FLG_CLASS_AUTH:
5414 * @IWM_STA_FLG_CLASS_ASSOC:
5415 * @IWM_STA_FLG_CLASS_MIMO_PROT:
5416 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5417 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5418 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5419 * initialised by driver and can be updated by fw upon reception of
5420 * action frames that can change the channel width. When cleared the fw
5421 * will send all the frames in 20MHz even when FAT channel is requested.
5422 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5423 * driver and can be updated by fw upon reception of action frames.
5424 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5426 enum iwm_sta_flags {
5427 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5428 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
5430 IWM_STA_FLG_DISABLE_TX = (1 << 4),
5432 IWM_STA_FLG_PS = (1 << 8),
5433 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5434 IWM_STA_FLG_PAN = (1 << 13),
5435 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5436 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5437 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
5439 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5440 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5441 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5442 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5443 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5444 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5445 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5446 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5447 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5448 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5450 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5451 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5452 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5453 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5454 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5455 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5457 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5458 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5459 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5460 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5461 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
5463 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5464 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5465 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5466 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5470 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
5471 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5472 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5473 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5474 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5475 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5476 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5477 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5478 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5479 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5480 * station info array (1 - n 1X mode)
5481 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5482 * @IWM_STA_KEY_NOT_VALID: key is invalid
5483 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5484 * @IWM_STA_KEY_MULTICAST: set for multical key
5485 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5487 enum iwm_sta_key_flag {
5488 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5489 IWM_STA_KEY_FLG_WEP = (1 << 0),
5490 IWM_STA_KEY_FLG_CCM = (2 << 0),
5491 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5492 IWM_STA_KEY_FLG_EXT = (4 << 0),
5493 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5494 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5495 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
5497 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5498 IWM_STA_KEY_FLG_KEYID_POS = 8,
5499 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5500 IWM_STA_KEY_NOT_VALID = (1 << 11),
5501 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5502 IWM_STA_KEY_MULTICAST = (1 << 14),
5503 IWM_STA_KEY_MFP = (1 << 15),
5507 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5508 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5509 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5510 * @IWM_STA_MODIFY_TX_RATE: unused
5511 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5512 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5513 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5514 * @IWM_STA_MODIFY_PROT_TH:
5515 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5517 enum iwm_sta_modify_flag {
5518 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5519 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5520 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5521 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5522 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5523 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5524 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5525 IWM_STA_MODIFY_QUEUES = (1 << 7),
5528 #define IWM_STA_MODE_MODIFY 1
5531 * enum iwm_sta_sleep_flag - type of sleep of the station
5532 * @IWM_STA_SLEEP_STATE_AWAKE:
5533 * @IWM_STA_SLEEP_STATE_PS_POLL:
5534 * @IWM_STA_SLEEP_STATE_UAPSD:
5535 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5536 * (last) released frame
5538 enum iwm_sta_sleep_flag {
5539 IWM_STA_SLEEP_STATE_AWAKE = 0,
5540 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5541 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5542 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5545 /* STA ID and color bits definitions */
5546 #define IWM_STA_ID_SEED (0x0f)
5547 #define IWM_STA_ID_POS (0)
5548 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5550 #define IWM_STA_COLOR_SEED (0x7)
5551 #define IWM_STA_COLOR_POS (4)
5552 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5554 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5555 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5556 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5557 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5559 #define IWM_STA_KEY_MAX_NUM (16)
5560 #define IWM_STA_KEY_IDX_INVALID (0xff)
5561 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5562 #define IWM_MAX_GLOBAL_KEYS (4)
5563 #define IWM_STA_KEY_LEN_WEP40 (5)
5564 #define IWM_STA_KEY_LEN_WEP104 (13)
5567 * struct iwm_mvm_keyinfo - key information
5568 * @key_flags: type %iwm_sta_key_flag
5569 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5570 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5571 * @key_offset: key offset in the fw's key table
5572 * @key: 16-byte unicast decryption key
5573 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5574 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5575 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5577 struct iwm_mvm_keyinfo {
5579 uint8_t tkip_rx_tsc_byte2;
5581 uint16_t tkip_rx_ttak[5];
5585 uint64_t tx_secur_seq_cnt;
5586 uint64_t hw_tkip_mic_rx_key;
5587 uint64_t hw_tkip_mic_tx_key;
5590 #define IWM_ADD_STA_STATUS_MASK 0xFF
5591 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5592 #define IWM_ADD_STA_BAID_MASK 0x7F00
5593 #define IWM_ADD_STA_BAID_SHIFT 8
5596 * struct iwm_mvm_add_sta_cmd - Add/modify a station in the fw's sta table.
5597 * ( REPLY_ADD_STA = 0x18 )
5598 * @add_modify: 1: modify existing, 0: add new station
5600 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5601 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5602 * @mac_id_n_color: the Mac context this station belongs to
5603 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5604 * @sta_id: index of station in uCode's station table
5605 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5606 * alone. 1 - modify, 0 - don't change.
5607 * @station_flags: look at %iwm_sta_flags
5608 * @station_flags_msk: what of %station_flags have changed
5609 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5610 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5611 * add_immediate_ba_ssn.
5612 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5613 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5614 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5615 * add_immediate_ba_tid.
5616 * @sleep_tx_count: number of packets to transmit to station even though it is
5617 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5618 * keeps track of STA sleep state.
5619 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5620 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5622 * @beamform_flags: beam forming controls
5623 * @tfd_queue_msk: tfd queues used by this station
5625 * The device contains an internal table of per-station information, with info
5626 * on security keys, aggregation parameters, and Tx rates for initial Tx
5627 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5629 * ADD_STA sets up the table entry for one station, either creating a new
5630 * entry, or modifying a pre-existing one.
5632 struct iwm_mvm_add_sta_cmd {
5635 uint16_t tid_disable_tx;
5636 uint32_t mac_id_n_color;
5637 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5640 uint8_t modify_mask;
5642 uint32_t station_flags;
5643 uint32_t station_flags_msk;
5644 uint8_t add_immediate_ba_tid;
5645 uint8_t remove_immediate_ba_tid;
5646 uint16_t add_immediate_ba_ssn;
5647 uint16_t sleep_tx_count;
5648 uint16_t sleep_state_flags;
5650 uint16_t beamform_flags;
5651 uint32_t tfd_queue_msk;
5652 } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5655 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5656 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5657 * @sta_id: index of station in uCode's station table
5658 * @key_offset: key offset in key storage
5659 * @key_flags: type %iwm_sta_key_flag
5660 * @key: key material data
5661 * @key2: key material data
5662 * @rx_secur_seq_cnt: RX security sequence counter for the key
5663 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5664 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5666 struct iwm_mvm_add_sta_key_cmd {
5672 uint8_t rx_secur_seq_cnt[16];
5673 uint8_t tkip_rx_tsc_byte2;
5675 uint16_t tkip_rx_ttak[5];
5676 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5679 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5680 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5681 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5682 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5683 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5684 * that doesn't exist.
5686 enum iwm_mvm_add_sta_rsp_status {
5687 IWM_ADD_STA_SUCCESS = 0x1,
5688 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5689 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5690 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5694 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5695 * ( IWM_REMOVE_STA = 0x19 )
5696 * @sta_id: the station id of the station to be removed
5698 struct iwm_mvm_rm_sta_cmd {
5700 uint8_t reserved[3];
5701 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5704 * struct iwm_mvm_mgmt_mcast_key_cmd
5705 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5706 * @ctrl_flags: %iwm_sta_key_flag
5708 * @K1: IGTK master key
5710 * @sta_id: station ID that support IGTK
5712 * @receive_seq_cnt: initial RSC/PN needed for replay check
5714 struct iwm_mvm_mgmt_mcast_key_cmd {
5715 uint32_t ctrl_flags;
5721 uint64_t receive_seq_cnt;
5722 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5724 struct iwm_mvm_wep_key {
5729 uint8_t reserved2[3];
5733 struct iwm_mvm_wep_key_cmd {
5734 uint32_t mac_id_n_color;
5736 uint8_t decryption_type;
5739 struct iwm_mvm_wep_key wep_key[0];
5740 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5743 * END mvm/fw-api-sta.h
5750 enum iwm_bt_coex_mode {
5751 IWM_BT_COEX_DISABLE = 0x0,
5752 IWM_BT_COEX_NW = 0x1,
5753 IWM_BT_COEX_BT = 0x2,
5754 IWM_BT_COEX_WIFI = 0x3,
5755 }; /* BT_COEX_MODES_E */
5757 enum iwm_bt_coex_enabled_modules {
5758 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
5759 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
5760 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
5761 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
5762 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
5763 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
5766 * struct iwm_bt_coex_cmd - bt coex configuration command
5767 * @mode: enum %iwm_bt_coex_mode
5768 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
5770 * The structure is used for the BT_COEX command.
5772 struct iwm_bt_coex_cmd {
5774 uint32_t enabled_modules;
5775 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
5779 * Location Aware Regulatory (LAR) API - MCC updates
5783 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
5784 * regulatory profile according to the given MCC (Mobile Country Code).
5785 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5786 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5787 * MCC in the cmd response will be the relevant MCC in the NVM.
5788 * @mcc: given mobile country code
5789 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5790 * @reserved: reserved for alignment
5792 struct iwm_mcc_update_cmd_v1 {
5796 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
5799 * struct iwm_mcc_update_cmd - Request the device to update geographic
5800 * regulatory profile according to the given MCC (Mobile Country Code).
5801 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5802 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5803 * MCC in the cmd response will be the relevant MCC in the NVM.
5804 * @mcc: given mobile country code
5805 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5806 * @reserved: reserved for alignment
5807 * @key: integrity key for MCC API OEM testing
5808 * @reserved2: reserved
5810 struct iwm_mcc_update_cmd {
5815 uint32_t reserved2[5];
5816 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
5819 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
5820 * Contains the new channel control profile map, if changed, and the new MCC
5821 * (mobile country code).
5822 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5823 * @status: see &enum iwm_mcc_update_status
5824 * @mcc: the new applied MCC
5825 * @cap: capabilities for all channels which matches the MCC
5826 * @source_id: the MCC source, see iwm_mcc_source
5827 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5828 * channels, depending on platform)
5829 * @channels: channel control data map, DWORD for each channel. Only the first
5832 struct iwm_mcc_update_resp_v1 {
5837 uint32_t n_channels;
5838 uint32_t channels[0];
5839 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
5842 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
5843 * Contains the new channel control profile map, if changed, and the new MCC
5844 * (mobile country code).
5845 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5846 * @status: see &enum iwm_mcc_update_status
5847 * @mcc: the new applied MCC
5848 * @cap: capabilities for all channels which matches the MCC
5849 * @source_id: the MCC source, see iwm_mcc_source
5850 * @time: time elapsed from the MCC test start (in 30 seconds TU)
5851 * @reserved: reserved.
5852 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5853 * channels, depending on platform)
5854 * @channels: channel control data map, DWORD for each channel. Only the first
5857 struct iwm_mcc_update_resp {
5864 uint32_t n_channels;
5865 uint32_t channels[0];
5866 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
5869 * struct iwm_mcc_chub_notif - chub notifies of mcc change
5870 * (MCC_CHUB_UPDATE_CMD = 0xc9)
5871 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
5872 * the cellular and connectivity cores that gets updates of the mcc, and
5873 * notifies the ucode directly of any mcc change.
5874 * The ucode requests the driver to request the device to update geographic
5875 * regulatory profile according to the given MCC (Mobile Country Code).
5876 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5877 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5878 * MCC in the cmd response will be the relevant MCC in the NVM.
5879 * @mcc: given mobile country code
5880 * @source_id: identity of the change originator, see iwm_mcc_source
5881 * @reserved1: reserved for alignment
5883 struct iwm_mcc_chub_notif {
5887 } __packed; /* LAR_MCC_NOTIFY_S */
5889 enum iwm_mcc_update_status {
5890 IWM_MCC_RESP_NEW_CHAN_PROFILE,
5891 IWM_MCC_RESP_SAME_CHAN_PROFILE,
5892 IWM_MCC_RESP_INVALID,
5893 IWM_MCC_RESP_NVM_DISABLED,
5894 IWM_MCC_RESP_ILLEGAL,
5895 IWM_MCC_RESP_LOW_PRIORITY,
5896 IWM_MCC_RESP_TEST_MODE_ACTIVE,
5897 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
5898 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
5901 enum iwm_mcc_source {
5902 IWM_MCC_SOURCE_OLD_FW = 0,
5903 IWM_MCC_SOURCE_ME = 1,
5904 IWM_MCC_SOURCE_BIOS = 2,
5905 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
5906 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
5907 IWM_MCC_SOURCE_WIFI = 5,
5908 IWM_MCC_SOURCE_RESERVED = 6,
5909 IWM_MCC_SOURCE_DEFAULT = 7,
5910 IWM_MCC_SOURCE_UNINITIALIZED = 8,
5911 IWM_MCC_SOURCE_MCC_API = 9,
5912 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
5913 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
5917 * struct iwm_dts_measurement_notif_v1 - measurements notification
5919 * @temp: the measured temperature
5920 * @voltage: the measured voltage
5922 struct iwm_dts_measurement_notif_v1 {
5925 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_1*/
5928 * struct iwm_dts_measurement_notif_v2 - measurements notification
5930 * @temp: the measured temperature
5931 * @voltage: the measured voltage
5932 * @threshold_idx: the trip index that was crossed
5934 struct iwm_dts_measurement_notif_v2 {
5937 int32_t threshold_idx;
5938 } __packed; /* TEMPERATURE_MEASUREMENT_TRIGGER_NTFY_S_VER_2 */
5941 * Some cherry-picked definitions
5944 #define IWM_FRAME_LIMIT 64
5947 * These functions retrieve specific information from the id field in
5948 * the iwm_host_cmd struct which contains the command id, the group id,
5949 * and the version of the command and vice versa.
5951 static inline uint8_t
5952 iwm_cmd_opcode(uint32_t cmdid)
5954 return cmdid & 0xff;
5957 static inline uint8_t
5958 iwm_cmd_groupid(uint32_t cmdid)
5960 return ((cmdid & 0xff00) >> 8);
5963 static inline uint8_t
5964 iwm_cmd_version(uint32_t cmdid)
5966 return ((cmdid & 0xff0000) >> 16);
5969 static inline uint32_t
5970 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
5972 return opcode + (groupid << 8) + (version << 16);
5975 /* make uint16_t wide id out of uint8_t group and opcode */
5976 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
5978 /* due to the conversion, this group is special */
5979 #define IWM_ALWAYS_LONG_GROUP 1
5981 struct iwm_cmd_header {
5988 struct iwm_cmd_header_wide {
5999 * enum iwm_power_scheme
6000 * @IWM_POWER_LEVEL_CAM - Continuously Active Mode
6001 * @IWM_POWER_LEVEL_BPS - Balanced Power Save (default)
6002 * @IWM_POWER_LEVEL_LP - Low Power
6004 enum iwm_power_scheme {
6005 IWM_POWER_SCHEME_CAM = 1,
6006 IWM_POWER_SCHEME_BPS,
6010 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
6011 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6012 #define IWM_CMD_FAILED_MSK 0x40
6015 * struct iwm_device_cmd
6017 * For allocation of the command and tx queues, this establishes the overall
6018 * size of the largest command we send to uCode, except for commands that
6019 * aren't fully copied and use other TFD space.
6021 struct iwm_device_cmd {
6024 struct iwm_cmd_header hdr;
6025 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
6028 struct iwm_cmd_header_wide hdr_wide;
6029 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
6030 sizeof(struct iwm_cmd_header_wide) +
6031 sizeof(struct iwm_cmd_header)];
6036 struct iwm_rx_packet {
6038 * The first 4 bytes of the RX frame header contain both the RX frame
6039 * size and some flags.
6041 * 31: flag flush RB request
6042 * 30: flag ignore TC (terminal counter) request
6043 * 29: flag fast IRQ request
6045 * 13-00: RX frame size
6047 uint32_t len_n_flags;
6048 struct iwm_cmd_header hdr;
6052 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6053 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000
6054 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40
6056 static inline uint32_t
6057 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6060 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6063 static inline uint32_t
6064 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
6067 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6071 #define IWM_MIN_DBM -100
6072 #define IWM_MAX_DBM -33 /* realistic guess */
6074 #define IWM_READ(sc, reg) \
6075 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6077 #define IWM_WRITE(sc, reg, val) \
6078 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6080 #define IWM_WRITE_1(sc, reg, val) \
6081 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6083 #define IWM_SETBITS(sc, reg, mask) \
6084 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
6086 #define IWM_CLRBITS(sc, reg, mask) \
6087 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
6089 #define IWM_BARRIER_WRITE(sc) \
6090 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6091 BUS_SPACE_BARRIER_WRITE)
6093 #define IWM_BARRIER_READ_WRITE(sc) \
6094 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6095 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
6097 #endif /* __IF_IWM_REG_H__ */