2 /* $OpenBSD: if_iwnreg.h,v 1.40 2010/05/05 19:41:57 damien Exp $ */
5 * Copyright (c) 2007, 2008
6 * Damien Bergamini <damien.bergamini@free.fr>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #ifndef __IF_IWNREG_H__
21 #define __IF_IWNREG_H__
23 #define IWN_CT_KILL_THRESHOLD 114 /* in Celsius */
24 #define IWN_CT_KILL_EXIT_THRESHOLD 95 /* in Celsius */
26 #define IWN_TX_RING_COUNT 256
27 #define IWN_TX_RING_LOMARK 192
28 #define IWN_TX_RING_HIMARK 224
29 #define IWN_RX_RING_COUNT_LOG 6
30 #define IWN_RX_RING_COUNT (1 << IWN_RX_RING_COUNT_LOG)
32 #define IWN4965_NTXQUEUES 16
33 #define IWN5000_NTXQUEUES 20
35 #define IWN4965_FIRSTAGGQUEUE 7
36 #define IWN5000_FIRSTAGGQUEUE 10
38 #define IWN4965_NDMACHNLS 7
39 #define IWN5000_NDMACHNLS 8
41 #define IWN_SRVC_DMACHNL 9
43 #define IWN_ICT_SIZE 4096
44 #define IWN_ICT_COUNT (IWN_ICT_SIZE / sizeof (uint32_t))
46 /* For cards with PAN command, default is IWN_CMD_QUEUE_NUM */
47 #define IWN_CMD_QUEUE_NUM 4
48 #define IWN_PAN_CMD_QUEUE 9
50 /* Maximum number of DMA segments for TX. */
51 #define IWN_MAX_SCATTER 20
53 /* RX buffers must be large enough to hold a full 4K A-MPDU. */
54 #define IWN_RBUF_SIZE (4 * 1024)
57 /* HW supports 36-bit DMA addresses. */
58 #define IWN_LOADDR(paddr) ((uint32_t)(paddr))
59 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
61 #define IWN_LOADDR(paddr) (paddr)
62 #define IWN_HIADDR(paddr) (0)
66 * Control and status registers.
68 #define IWN_HW_IF_CONFIG 0x000
69 #define IWN_INT_COALESCING 0x004
70 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
72 #define IWN_INT_MASK 0x00c
73 #define IWN_FH_INT 0x010
74 #define IWN_GPIO_IN 0x018 /* read external chip pins */
75 #define IWN_RESET 0x020
76 #define IWN_GP_CNTRL 0x024
77 #define IWN_HW_REV 0x028
78 #define IWN_EEPROM 0x02c
79 #define IWN_EEPROM_GP 0x030
80 #define IWN_OTP_GP 0x034
82 #define IWN_GP_UCODE 0x048
83 #define IWN_GP_DRIVER 0x050
84 #define IWN_UCODE_GP1 0x054
85 #define IWN_UCODE_GP1_SET 0x058
86 #define IWN_UCODE_GP1_CLR 0x05c
87 #define IWN_UCODE_GP2 0x060
89 #define IWN_DRAM_INT_TBL 0x0a0
90 #define IWN_SHADOW_REG_CTRL 0x0a8
91 #define IWN_GIO_CHICKEN 0x100
92 #define IWN_ANA_PLL 0x20c
93 #define IWN_HW_REV_WA 0x22c
94 #define IWN_DBG_HPET_MEM 0x240
95 #define IWN_DBG_LINK_PWR_MGMT 0x250
96 /* Need nic_lock for use above */
97 #define IWN_MEM_RADDR 0x40c
98 #define IWN_MEM_WADDR 0x410
99 #define IWN_MEM_WDATA 0x418
100 #define IWN_MEM_RDATA 0x41c
101 #define IWN_TARG_MBX_C 0x430
102 #define IWN_PRPH_WADDR 0x444
103 #define IWN_PRPH_RADDR 0x448
104 #define IWN_PRPH_WDATA 0x44c
105 #define IWN_PRPH_RDATA 0x450
106 #define IWN_HBUS_TARG_WRPTR 0x460
109 * Flow-Handler registers.
111 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
112 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
113 #define IWN_FH_KW_ADDR 0x197c
114 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
115 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
116 #define IWN_FH_STATUS_WPTR 0x1bc0
117 #define IWN_FH_RX_BASE 0x1bc4
118 #define IWN_FH_RX_WPTR 0x1bc8
119 #define IWN_FH_RX_CONFIG 0x1c00
120 #define IWN_FH_RX_STATUS 0x1c44
121 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
122 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
123 #define IWN_FH_TX_CHICKEN 0x1e98
124 #define IWN_FH_TX_STATUS 0x1eb0
127 * TX scheduler registers.
129 #define IWN_SCHED_BASE 0xa02c00
130 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
131 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
132 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
133 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
134 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
135 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
136 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
137 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
138 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
139 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
140 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
141 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
142 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
143 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
146 * Offsets in TX scheduler's SRAM.
148 #define IWN4965_SCHED_CTX_OFF 0x380
149 #define IWN4965_SCHED_CTX_LEN 416
150 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
151 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
152 #define IWN5000_SCHED_CTX_OFF 0x600
153 #define IWN5000_SCHED_CTX_LEN 520
154 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
155 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
158 * NIC internal memory offsets.
160 #define IWN_APMG_CLK_CTRL 0x3000
161 #define IWN_APMG_CLK_EN 0x3004
162 #define IWN_APMG_CLK_DIS 0x3008
163 #define IWN_APMG_PS 0x300c
164 #define IWN_APMG_DIGITAL_SVR 0x3058
165 #define IWN_APMG_ANALOG_SVR 0x306c
166 #define IWN_APMG_PCI_STT 0x3010
167 #define IWN_BSM_WR_CTRL 0x3400
168 #define IWN_BSM_WR_MEM_SRC 0x3404
169 #define IWN_BSM_WR_MEM_DST 0x3408
170 #define IWN_BSM_WR_DWCOUNT 0x340c
171 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490
172 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494
173 #define IWN_BSM_DRAM_DATA_ADDR 0x3498
174 #define IWN_BSM_DRAM_DATA_SIZE 0x349c
175 #define IWN_BSM_SRAM_BASE 0x3800
177 /* Possible flags for register IWN_HW_IF_CONFIG. */
178 #define IWN_HW_IF_CONFIG_4965_R (1 << 4)
179 #define IWN_HW_IF_CONFIG_MAC_SI (1 << 8)
180 #define IWN_HW_IF_CONFIG_RADIO_SI (1 << 9)
181 #define IWN_HW_IF_CONFIG_EEPROM_LOCKED (1 << 21)
182 #define IWN_HW_IF_CONFIG_NIC_READY (1 << 22)
183 #define IWN_HW_IF_CONFIG_HAP_WAKE_L1A (1 << 23)
184 #define IWN_HW_IF_CONFIG_PREPARE_DONE (1 << 25)
185 #define IWN_HW_IF_CONFIG_PREPARE (1 << 27)
187 /* Possible values for register IWN_INT_PERIODIC. */
188 #define IWN_INT_PERIODIC_DIS 0x00
189 #define IWN_INT_PERIODIC_ENA 0xff
191 /* Possible flags for registers IWN_PRPH_RADDR/IWN_PRPH_WADDR. */
192 #define IWN_PRPH_DWORD ((sizeof (uint32_t) - 1) << 24)
194 /* Possible values for IWN_BSM_WR_MEM_DST. */
195 #define IWN_FW_TEXT_BASE 0x00000000
196 #define IWN_FW_DATA_BASE 0x00800000
198 /* Possible flags for register IWN_RESET. */
199 #define IWN_RESET_NEVO (1 << 0)
200 #define IWN_RESET_SW (1 << 7)
201 #define IWN_RESET_MASTER_DISABLED (1 << 8)
202 #define IWN_RESET_STOP_MASTER (1 << 9)
203 #define IWN_RESET_LINK_PWR_MGMT_DIS (1U << 31)
205 /* Possible flags for register IWN_GP_CNTRL. */
206 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
207 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
208 #define IWN_GP_CNTRL_INIT_DONE (1 << 2)
209 #define IWN_GP_CNTRL_MAC_ACCESS_REQ (1 << 3)
210 #define IWN_GP_CNTRL_SLEEP (1 << 4)
211 #define IWN_GP_CNTRL_RFKILL (1 << 27)
213 /* Possible flags for register IWN_GIO_CHICKEN. */
214 #define IWN_GIO_CHICKEN_L1A_NO_L0S_RX (1 << 23)
215 #define IWN_GIO_CHICKEN_DIS_L0S_TIMER (1 << 29)
217 /* Possible flags for register IWN_GIO. */
218 #define IWN_GIO_L0S_ENA (1 << 1)
220 /* Possible flags for register IWN_GP_DRIVER. */
221 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0)
222 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0)
223 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0)
224 #define IWN_GP_DRIVER_CALIB_VER6 (1 << 2)
225 #define IWN_GP_DRIVER_6050_1X2 (1 << 3)
226 #define IWN_GP_DRIVER_REG_BIT_RADIO_IQ_INVERT (1 << 7)
227 #define IWN_GP_DRIVER_NONE 0
229 /* Possible flags for register IWN_UCODE_GP1_CLR. */
230 #define IWN_UCODE_GP1_RFKILL (1 << 1)
231 #define IWN_UCODE_GP1_CMD_BLOCKED (1 << 2)
232 #define IWN_UCODE_GP1_CTEMP_STOP_RF (1 << 3)
233 #define IWN_UCODE_GP1_CFG_COMPLETE (1 << 5)
235 /* Possible flags/values for register IWN_LED. */
236 #define IWN_LED_BSM_CTRL (1 << 5)
237 #define IWN_LED_OFF 0x00000038
238 #define IWN_LED_ON 0x00000078
240 #define IWN_MAX_BLINK_TBL 10
241 #define IWN_LED_STATIC_ON 0
242 #define IWN_LED_STATIC_OFF 1
243 #define IWN_LED_SLOW_BLINK 2
244 #define IWN_LED_INT_BLINK 3
245 #define IWN_LED_UNIT 0x1388 /* 5 ms */
247 static const struct {
248 uint16_t tpt; /* Mb/s */
266 /* Possible flags for register IWN_DRAM_INT_TBL. */
267 #define IWN_DRAM_INT_TBL_WRAP_CHECK (1 << 27)
268 #define IWN_DRAM_INT_TBL_ENABLE (1U << 31)
270 /* Possible values for register IWN_ANA_PLL. */
271 #define IWN_ANA_PLL_INIT 0x00880300
273 /* Possible flags for register IWN_FH_RX_STATUS. */
274 #define IWN_FH_RX_STATUS_IDLE (1 << 24)
276 /* Possible flags for register IWN_BSM_WR_CTRL. */
277 #define IWN_BSM_WR_CTRL_START_EN (1 << 30)
278 #define IWN_BSM_WR_CTRL_START (1U << 31)
280 /* Possible flags for register IWN_INT. */
281 #define IWN_INT_ALIVE (1 << 0)
282 #define IWN_INT_WAKEUP (1 << 1)
283 #define IWN_INT_SW_RX (1 << 3)
284 #define IWN_INT_CT_REACHED (1 << 6)
285 #define IWN_INT_RF_TOGGLED (1 << 7)
286 #define IWN_INT_SW_ERR (1 << 25)
287 #define IWN_INT_SCHED (1 << 26)
288 #define IWN_INT_FH_TX (1 << 27)
289 #define IWN_INT_RX_PERIODIC (1 << 28)
290 #define IWN_INT_HW_ERR (1 << 29)
291 #define IWN_INT_FH_RX (1U << 31)
294 #define IWN_INT_MASK_DEF \
295 (IWN_INT_SW_ERR | IWN_INT_HW_ERR | IWN_INT_FH_TX | \
296 IWN_INT_FH_RX | IWN_INT_ALIVE | IWN_INT_WAKEUP | \
297 IWN_INT_SW_RX | IWN_INT_CT_REACHED | IWN_INT_RF_TOGGLED)
299 /* Possible flags for register IWN_FH_INT. */
300 #define IWN_FH_INT_TX_CHNL(x) (1 << (x))
301 #define IWN_FH_INT_RX_CHNL(x) (1 << ((x) + 16))
302 #define IWN_FH_INT_HI_PRIOR (1 << 30)
303 /* Shortcuts for the above. */
304 #define IWN_FH_INT_TX \
305 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
306 #define IWN_FH_INT_RX \
307 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
309 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
310 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0
311 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31)
312 #define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD (1 << 20)
314 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
315 #define IWN_FH_TXBUF_STATUS_TBNUM(x) ((x) << 20)
316 #define IWN_FH_TXBUF_STATUS_TBIDX(x) ((x) << 12)
317 #define IWN_FH_TXBUF_STATUS_TFBD_VALID 3
319 /* Possible flags for register IWN_FH_TX_CHICKEN. */
320 #define IWN_FH_TX_CHICKEN_SCHED_RETRY (1 << 1)
322 /* Possible flags for register IWN_FH_TX_STATUS. */
323 #define IWN_FH_TX_STATUS_IDLE(chnl) (1 << ((chnl) + 16))
325 /* Possible flags for register IWN_FH_RX_CONFIG. */
326 #define IWN_FH_RX_CONFIG_ENA (1U << 31)
327 #define IWN_FH_RX_CONFIG_NRBD(x) ((x) << 20)
328 #define IWN_FH_RX_CONFIG_RB_SIZE_8K (1 << 16)
329 #define IWN_FH_RX_CONFIG_SINGLE_FRAME (1 << 15)
330 #define IWN_FH_RX_CONFIG_IRQ_DST_HOST (1 << 12)
331 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x) ((x) << 4)
332 #define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY (1 << 2)
334 /* Possible flags for register IWN_FH_TX_CONFIG. */
335 #define IWN_FH_TX_CONFIG_DMA_ENA (1U << 31)
336 #define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA (1 << 3)
338 /* Possible flags for register IWN_EEPROM. */
339 #define IWN_EEPROM_READ_VALID (1 << 0)
340 #define IWN_EEPROM_CMD (1 << 1)
342 /* Possible flags for register IWN_EEPROM_GP. */
343 #define IWN_EEPROM_GP_IF_OWNER 0x00000180
345 /* Possible flags for register IWN_OTP_GP. */
346 #define IWN_OTP_GP_DEV_SEL_OTP (1 << 16)
347 #define IWN_OTP_GP_RELATIVE_ACCESS (1 << 17)
348 #define IWN_OTP_GP_ECC_CORR_STTS (1 << 20)
349 #define IWN_OTP_GP_ECC_UNCORR_STTS (1 << 21)
351 /* Possible flags for register IWN_SCHED_QUEUE_STATUS. */
352 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
353 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
354 #define IWN4965_TXQ_STATUS_AGGR_ENA (1 << 5 | 1 << 8)
355 #define IWN4965_TXQ_STATUS_CHGACT (1 << 10)
356 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
357 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
358 #define IWN5000_TXQ_STATUS_CHGACT (1 << 19)
360 /* Possible flags for registers IWN_APMG_CLK_*. */
361 #define IWN_APMG_CLK_CTRL_DMA_CLK_RQT (1 << 9)
362 #define IWN_APMG_CLK_CTRL_BSM_CLK_RQT (1 << 11)
364 /* Possible flags for register IWN_APMG_PS. */
365 #define IWN_APMG_PS_EARLY_PWROFF_DIS (1 << 22)
366 #define IWN_APMG_PS_PWR_SRC(x) ((x) << 24)
367 #define IWN_APMG_PS_PWR_SRC_VMAIN 0
368 #define IWN_APMG_PS_PWR_SRC_VAUX 2
369 #define IWN_APMG_PS_PWR_SRC_MASK IWN_APMG_PS_PWR_SRC(3)
370 #define IWN_APMG_PS_RESET_REQ (1 << 26)
372 /* Possible flags for register IWN_APMG_DIGITAL_SVR. */
373 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
374 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK \
375 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
376 #define IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32 \
377 IWN_APMG_DIGITAL_SVR_VOLTAGE(3)
379 /* Possible flags for IWN_APMG_PCI_STT. */
380 #define IWN_APMG_PCI_STT_L1A_DIS (1 << 11)
382 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
383 #define IWN_FW_UPDATED (1U << 31)
385 #define IWN_SCHED_WINSZ 64
386 #define IWN_SCHED_LIMIT 64
387 #define IWN4965_SCHED_COUNT 512
388 #define IWN5000_SCHED_COUNT (IWN_TX_RING_COUNT + IWN_SCHED_WINSZ)
389 #define IWN4965_SCHEDSZ (IWN4965_NTXQUEUES * IWN4965_SCHED_COUNT * 2)
390 #define IWN5000_SCHEDSZ (IWN5000_NTXQUEUES * IWN5000_SCHED_COUNT * 2)
393 uint8_t reserved1[3];
398 } __packed segs[IWN_MAX_SCATTER];
399 /* Pad to 128 bytes. */
403 struct iwn_rx_status {
404 uint16_t closed_count;
405 uint16_t closed_rx_count;
406 uint16_t finished_count;
407 uint16_t finished_rx_count;
408 uint32_t reserved[2];
413 * The first 4 bytes of the RX frame header contain both the RX frame
414 * size and some flags.
416 * 31: flag flush RB request
417 * 30: flag ignore TC (terminal counter) request
418 * 29: flag fast IRQ request
420 * 13-00: RX frame size
424 #define IWN_UC_READY 1
425 #define IWN_ADD_NODE_DONE 24
426 #define IWN_TX_DONE 28
427 #define IWN_REPLY_LED_CMD 72
428 #define IWN5000_CALIBRATION_RESULT 102
429 #define IWN5000_CALIBRATION_DONE 103
430 #define IWN_START_SCAN 130
431 #define IWN_NOTIF_SCAN_RESULT 131
432 #define IWN_STOP_SCAN 132
433 #define IWN_RX_STATISTICS 156
434 #define IWN_BEACON_STATISTICS 157
435 #define IWN_STATE_CHANGED 161
436 #define IWN_BEACON_MISSED 162
437 #define IWN_RX_PHY 192
438 #define IWN_MPDU_RX_DONE 193
439 #define IWN_RX_DONE 195
440 #define IWN_RX_COMPRESSED_BA 197
442 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */
443 uint8_t idx; /* position within TX queue */
445 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX
446 * or uCode-originated notification
450 #define IWN_RX_DESC_QID_MSK 0x1F
451 #define IWN_UNSOLICITED_RX_NOTIF 0x80
453 /* CARD_STATE_NOTIFICATION */
454 #define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01
455 #define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02
456 #define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04
457 #define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10
459 /* Possible RX status flags. */
460 #define IWN_RX_NO_CRC_ERR (1 << 0)
461 #define IWN_RX_NO_OVFL_ERR (1 << 1)
462 /* Shortcut for the above. */
463 #define IWN_RX_NOERROR (IWN_RX_NO_CRC_ERR | IWN_RX_NO_OVFL_ERR)
464 #define IWN_RX_MPDU_MIC_OK (1 << 6)
465 #define IWN_RX_CIPHER_MASK (7 << 8)
466 #define IWN_RX_CIPHER_CCMP (2 << 8)
467 #define IWN_RX_MPDU_DEC (1 << 11)
468 #define IWN_RX_DECRYPT_MASK (3 << 11)
469 #define IWN_RX_DECRYPT_OK (3 << 11)
473 #define IWN_CMD_RXON 16
474 #define IWN_CMD_RXON_ASSOC 17
475 #define IWN_CMD_EDCA_PARAMS 19
476 #define IWN_CMD_TIMING 20
477 #define IWN_CMD_ADD_NODE 24
478 #define IWN_CMD_TX_DATA 28
479 #define IWN_CMD_LINK_QUALITY 78
480 #define IWN_CMD_SET_LED 72
481 #define IWN5000_CMD_WIMAX_COEX 90
482 #define IWN_TEMP_NOTIFICATION 98
483 #define IWN5000_CMD_CALIB_CONFIG 101
484 #define IWN5000_CMD_CALIB_RESULT 102
485 #define IWN5000_CMD_CALIB_COMPLETE 103
486 #define IWN_CMD_SET_POWER_MODE 119
487 #define IWN_CMD_SCAN 128
488 #define IWN_CMD_SCAN_RESULTS 131
489 #define IWN_CMD_TXPOWER_DBM 149
490 #define IWN_CMD_TXPOWER 151
491 #define IWN5000_CMD_TX_ANT_CONFIG 152
492 #define IWN_CMD_TXPOWER_DBM_V1 152
493 #define IWN_CMD_BT_COEX 155
494 #define IWN_CMD_GET_STATISTICS 156
495 #define IWN_CMD_SET_CRITICAL_TEMP 164
496 #define IWN_CMD_SET_SENSITIVITY 168
497 #define IWN_CMD_PHY_CALIB 176
498 #define IWN_CMD_BT_COEX_PRIOTABLE 204
499 #define IWN_CMD_BT_COEX_PROT 205
500 #define IWN_CMD_BT_COEX_NOTIF 206
502 #define IWN_CMD_WIPAN_PARAMS 0xb2
503 #define IWN_CMD_WIPAN_RXON 0xb3
504 #define IWN_CMD_WIPAN_RXON_TIMING 0xb4
505 #define IWN_CMD_WIPAN_RXON_ASSOC 0xb6
506 #define IWN_CMD_WIPAN_QOS_PARAM 0xb7
507 #define IWN_CMD_WIPAN_WEPKEY 0xb8
508 #define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9
509 #define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc
510 #define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd
519 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156
520 * all devices identical.
522 * This command triggers an immediate response containing uCode statistics.
523 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157.
525 * If the CLEAR_STATS configuration flag is set, uCode will clear its
526 * internal copy of the statistics (counters) after issuing the response.
527 * This flag does not affect IWN_BEACON_STATISTICS after beacons (see below).
529 * If the DISABLE_NOTIF configuration flag is set, uCode will not issue
530 * IWN_BEACON_STATISTICS after received beacons. This flag
531 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself.
533 struct iwn_statistics_cmd {
534 uint32_t configuration_flags;
535 #define IWN_STATS_CONF_CLEAR_STATS htole32(0x1)
536 #define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2)
539 /* Antenna flags, used in various commands. */
540 #define IWN_ANT_A (1 << 0)
541 #define IWN_ANT_B (1 << 1)
542 #define IWN_ANT_C (1 << 2)
544 #define IWN_ANT_AB (IWN_ANT_A | IWN_ANT_B)
545 #define IWN_ANT_BC (IWN_ANT_B | IWN_ANT_C)
546 #define IWN_ANT_AC (IWN_ANT_A | IWN_ANT_C)
547 #define IWN_ANT_ABC (IWN_ANT_A | IWN_ANT_B | IWN_ANT_C)
549 /* Structure for command IWN_CMD_RXON. */
551 uint8_t myaddr[IEEE80211_ADDR_LEN];
553 uint8_t bssid[IEEE80211_ADDR_LEN];
555 uint8_t wlap[IEEE80211_ADDR_LEN];
558 #define IWN_MODE_HOSTAP 1
559 #define IWN_MODE_STA 3
560 #define IWN_MODE_IBSS 4
561 #define IWN_MODE_MONITOR 6
562 #define IWN_MODE_2STA 8
563 #define IWN_MODE_P2P 9
567 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0)
568 #define IWN_RXCHAIN_VALID(x) (((x) & IWN_ANT_ABC) << 1)
569 #define IWN_RXCHAIN_FORCE_SEL(x) (((x) & IWN_ANT_ABC) << 4)
570 #define IWN_RXCHAIN_FORCE_MIMO_SEL(x) (((x) & IWN_ANT_ABC) << 7)
571 #define IWN_RXCHAIN_IDLE_COUNT(x) ((x) << 10)
572 #define IWN_RXCHAIN_MIMO_COUNT(x) ((x) << 12)
573 #define IWN_RXCHAIN_MIMO_FORCE (1 << 14)
579 #define IWN_RXON_24GHZ (1 << 0)
580 #define IWN_RXON_CCK (1 << 1)
581 #define IWN_RXON_AUTO (1 << 2)
582 #define IWN_RXON_SHSLOT (1 << 4)
583 #define IWN_RXON_SHPREAMBLE (1 << 5)
584 #define IWN_RXON_NODIVERSITY (1 << 7)
585 #define IWN_RXON_ANTENNA_A (1 << 8)
586 #define IWN_RXON_ANTENNA_B (1 << 9)
587 #define IWN_RXON_TSF (1 << 15)
588 #define IWN_RXON_HT_HT40MINUS (1 << 22)
590 #define IWN_RXON_HT_PROTMODE(x) (x << 23)
592 /* 0=legacy, 1=pure40, 2=mixed */
593 #define IWN_RXON_HT_MODEPURE40 (1 << 25)
594 #define IWN_RXON_HT_MODEMIXED (2 << 25)
596 #define IWN_RXON_CTS_TO_SELF (1 << 30)
599 #define IWN_FILTER_PROMISC (1 << 0)
600 #define IWN_FILTER_CTL (1 << 1)
601 #define IWN_FILTER_MULTICAST (1 << 2)
602 #define IWN_FILTER_NODECRYPT (1 << 3)
603 #define IWN_FILTER_BSS (1 << 5)
604 #define IWN_FILTER_BEACON (1 << 6)
608 uint8_t ht_single_mask;
609 uint8_t ht_dual_mask;
610 /* The following fields are for >=5000 Series only. */
611 uint8_t ht_triple_mask;
613 uint16_t acquisition;
617 #define IWN4965_RXONSZ (sizeof (struct iwn_rxon) - 6)
618 #define IWN5000_RXONSZ (sizeof (struct iwn_rxon))
620 /* Structure for command IWN_CMD_ASSOCIATE. */
629 /* Structure for command IWN_CMD_EDCA_PARAMS. */
630 struct iwn_edca_params {
632 #define IWN_EDCA_UPDATE (1 << 0)
633 #define IWN_EDCA_TXOP (1 << 4)
641 } __packed ac[WME_NUM_AC];
644 /* Structure for command IWN_CMD_TIMING. */
645 struct iwn_cmd_timing {
652 uint8_t delta_cp_bss_tbtts;
655 /* Structure for command IWN_CMD_ADD_NODE. */
656 struct iwn_node_info {
658 #define IWN_NODE_UPDATE (1 << 0)
660 uint8_t reserved1[3];
662 uint8_t macaddr[IEEE80211_ADDR_LEN];
668 #define IWN_PAN_ID_BCAST 14
669 #define IWN5000_ID_BROADCAST 15
670 #define IWN4965_ID_BROADCAST 31
673 #define IWN_FLAG_SET_KEY (1 << 0)
674 #define IWN_FLAG_SET_DISABLE_TID (1 << 1)
675 #define IWN_FLAG_SET_TXRATE (1 << 2)
676 #define IWN_FLAG_SET_ADDBA (1 << 3)
677 #define IWN_FLAG_SET_DELBA (1 << 4)
681 #define IWN_KFLAG_CCMP (1 << 1)
682 #define IWN_KFLAG_MAP (1 << 3)
683 #define IWN_KFLAG_KID(kid) ((kid) << 8)
684 #define IWN_KFLAG_INVALID (1 << 11)
685 #define IWN_KFLAG_GROUP (1 << 14)
687 uint8_t tsc2; /* TKIP TSC2 */
693 /* The following 3 fields are for 5000 Series only. */
699 #define IWN_SMPS_MIMO_PROT (1 << 17)
700 #define IWN_AMDPU_SIZE_FACTOR(x) ((x) << 19)
701 #define IWN_NODE_HT40 (1 << 21)
702 #define IWN_SMPS_MIMO_DIS (1 << 22)
703 #define IWN_AMDPU_DENSITY(x) ((x) << 23)
706 uint16_t disable_tid;
714 struct iwn4965_node_info {
716 uint8_t reserved1[3];
717 uint8_t macaddr[IEEE80211_ADDR_LEN];
723 uint8_t tsc2; /* TKIP TSC2 */
731 uint16_t disable_tid;
739 #define IWN_RFLAG_MCS (1 << 8)
740 #define IWN_RFLAG_CCK (1 << 9)
741 #define IWN_RFLAG_GREENFIELD (1 << 10)
742 #define IWN_RFLAG_HT40 (1 << 11)
743 #define IWN_RFLAG_DUPLICATE (1 << 12)
744 #define IWN_RFLAG_SGI (1 << 13)
745 #define IWN_RFLAG_ANT(x) ((x) << 14)
747 /* Structure for command IWN_CMD_TX_DATA. */
748 struct iwn_cmd_data {
752 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
753 #define IWN_TX_NEED_RTS (1 << 1)
754 #define IWN_TX_NEED_CTS (1 << 2)
755 #define IWN_TX_NEED_ACK (1 << 3)
756 #define IWN_TX_LINKQ (1 << 4)
757 #define IWN_TX_IMM_BA (1 << 6)
758 #define IWN_TX_FULL_TXOP (1 << 7)
759 #define IWN_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */
760 #define IWN_TX_AUTO_SEQ (1 << 13)
761 #define IWN_TX_MORE_FRAG (1 << 14)
762 #define IWN_TX_INSERT_TSTAMP (1 << 16)
763 #define IWN_TX_NEED_PADDING (1 << 20)
770 #define IWN_CIPHER_WEP40 1
771 #define IWN_CIPHER_CCMP 2
772 #define IWN_CIPHER_TKIP 3
773 #define IWN_CIPHER_WEP104 9
781 #define IWN_LIFETIME_INFINITE 0xffffffff
792 /* Structure for command IWN_CMD_LINK_QUALITY. */
793 #define IWN_MAX_TX_RETRIES 16
794 struct iwn_cmd_link_quality {
800 uint8_t antmsk_1stream;
801 uint8_t antmsk_2stream;
802 uint8_t ridx[WME_NUM_AC];
803 uint16_t ampdu_limit;
804 uint8_t ampdu_threshold;
807 uint32_t retry[IWN_MAX_TX_RETRIES];
811 /* Structure for command IWN_CMD_SET_LED. */
813 uint32_t unit; /* multiplier (in usecs) */
815 #define IWN_LED_ACTIVITY 1
816 #define IWN_LED_LINK 2
823 /* Structure for command IWN5000_CMD_WIMAX_COEX. */
824 struct iwn5000_wimax_coex {
826 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
827 #define IWN_WIMAX_COEX_UNASSOC_WA_UNMASK (1 << 2)
828 #define IWN_WIMAX_COEX_ASSOC_WA_UNMASK (1 << 3)
829 #define IWN_WIMAX_COEX_ENABLE (1 << 7)
831 struct iwn5000_wimax_event {
836 } __packed events[16];
839 /* Structures for command IWN5000_CMD_CALIB_CONFIG. */
840 struct iwn5000_calib_elem {
843 #define IWN5000_CALIB_DC (1 << 1)
850 struct iwn5000_calib_status {
851 struct iwn5000_calib_elem once;
852 struct iwn5000_calib_elem perd;
856 struct iwn5000_calib_config {
857 struct iwn5000_calib_status ucode;
858 struct iwn5000_calib_status driver;
862 /* Structure for command IWN_CMD_SET_POWER_MODE. */
863 struct iwn_pmgt_cmd {
865 #define IWN_PS_ALLOW_SLEEP (1 << 0)
866 #define IWN_PS_NOTIFY (1 << 1)
867 #define IWN_PS_SLEEP_OVER_DTIM (1 << 2)
868 #define IWN_PS_PCI_PMGT (1 << 3)
869 #define IWN_PS_FAST_PD (1 << 4)
870 #define IWN_PS_BEACON_FILTERING (1 << 5)
871 #define IWN_PS_SHADOW_REG (1 << 6)
872 #define IWN_PS_CT_KILL (1 << 7)
873 #define IWN_PS_BT_SCD (1 << 8)
874 #define IWN_PS_ADVANCED_PM (1 << 9)
884 /* Structures for command IWN_CMD_SCAN. */
885 struct iwn_scan_essid {
888 uint8_t data[IEEE80211_NWID_LEN];
891 struct iwn_scan_hdr {
896 uint16_t quiet_threshold;
897 uint16_t crc_threshold;
899 uint32_t max_svc; /* background scans */
900 uint32_t pause_svc; /* background scans */
904 /* Followed by a struct iwn_cmd_data. */
905 /* Followed by an array of 20 structs iwn_scan_essid. */
906 /* Followed by probe request body. */
907 /* Followed by an array of ``nchan'' structs iwn_scan_chan. */
910 struct iwn_scan_chan {
912 #define IWN_CHAN_PASSIVE (0 << 0)
913 #define IWN_CHAN_ACTIVE (1 << 0)
914 #define IWN_CHAN_NPBREQS(x) (((1 << (x)) - 1) << 1)
919 uint16_t active; /* msecs */
920 uint16_t passive; /* msecs */
923 #define IWN_SCAN_CRC_TH_DISABLED 0
924 #define IWN_SCAN_CRC_TH_DEFAULT htole16(1)
925 #define IWN_SCAN_CRC_TH_NEVER htole16(0xffff)
927 /* Maximum size of a scan command. */
928 #define IWN_SCAN_MAXSZ (MCLBYTES - 4)
931 * For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
932 * sending probe req. This should be set long enough to hear probe responses
933 * from more than one AP.
935 #define IWN_ACTIVE_DWELL_TIME_2GHZ (30) /* all times in msec */
936 #define IWN_ACTIVE_DWELL_TIME_5GHZ (20)
937 #define IWN_ACTIVE_DWELL_FACTOR_2GHZ (3)
938 #define IWN_ACTIVE_DWELL_FACTOR_5GHZ (2)
941 * For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
942 * Must be set longer than active dwell time.
943 * For the most reliable scan, set > AP beacon interval (typically 100msec).
945 #define IWN_PASSIVE_DWELL_TIME_2GHZ (20) /* all times in msec */
946 #define IWN_PASSIVE_DWELL_TIME_5GHZ (10)
947 #define IWN_PASSIVE_DWELL_BASE (100)
948 #define IWN_CHANNEL_TUNE_TIME (5)
950 #define IWN_SCAN_CHAN_TIMEOUT 2
951 #define IWN_MAX_SCAN_CHANNEL 50
954 * If active scanning is requested but a certain channel is
955 * marked passive, we can do active scanning if we detect
958 * There is an issue with some firmware versions that triggers
959 * a sysassert on a "good CRC threshold" of zero (== disabled),
960 * on a radar channel even though this means that we should NOT
963 * The "good CRC threshold" is the number of frames that we
964 * need to receive during our dwell time on a channel before
965 * sending out probes -- setting this to a huge value will
966 * mean we never reach it, but at the same time work around
967 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
968 * here instead of IWL_GOOD_CRC_TH_DISABLED.
970 * This was fixed in later versions along with some other
971 * scan changes, and the threshold behaves as a flag in those
974 #define IWN_GOOD_CRC_TH_DISABLED 0
975 #define IWN_GOOD_CRC_TH_DEFAULT htole16(1)
976 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff)
978 /* Structure for command IWN_CMD_TXPOWER (4965AGN only.) */
979 #define IWN_RIDX_MAX 32
980 struct iwn4965_cmd_txpower {
988 } __packed power[IWN_RIDX_MAX + 1];
991 /* Structure for command IWN_CMD_TXPOWER_DBM (5000 Series only.) */
992 struct iwn5000_cmd_txpower {
993 int8_t global_limit; /* in half-dBm */
994 #define IWN5000_TXPOWER_AUTO 0x7f
995 #define IWN5000_TXPOWER_MAX_DBM 16
998 #define IWN5000_TXPOWER_NO_CLOSED (1 << 6)
1000 int8_t srv_limit; /* in half-dBm */
1004 /* Structures for command IWN_CMD_BLUETOOTH. */
1005 struct iwn_bluetooth {
1007 #define IWN_BT_COEX_CHAN_ANN (1 << 0)
1008 #define IWN_BT_COEX_BT_PRIO (1 << 1)
1009 #define IWN_BT_COEX_2_WIRE (1 << 2)
1012 #define IWN_BT_LEAD_TIME_DEF 30
1015 #define IWN_BT_MAX_KILL_DEF 5
1022 struct iwn6000_btcoex_config {
1024 #define IWN_BT_FLAG_COEX6000_CHAN_INHIBITION 1
1025 #define IWN_BT_FLAG_COEX6000_MODE_MASK ((1 << 3) | (1 << 4) | (1 << 5 ))
1026 #define IWN_BT_FLAG_COEX6000_MODE_SHIFT 3
1027 #define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0
1028 #define IWN_BT_FLAG_COEX6000_MODE_LEGACY_2W 1
1029 #define IWN_BT_FLAG_COEX6000_MODE_3W 2
1030 #define IWN_BT_FLAG_COEX6000_MODE_4W 3
1032 #define IWN_BT_FLAG_UCODE_DEFAULT (1 << 6)
1033 #define IWN_BT_FLAG_SYNC_2_BT_DISABLE (1 << 7)
1036 uint8_t bt3_t7_timer;
1039 uint8_t sample_time;
1040 uint8_t bt3_t2_timer;
1041 uint16_t bt4_reaction;
1042 uint32_t lookup_table[12];
1043 uint16_t bt4_decision;
1046 uint8_t tx_prio_boost;
1047 uint16_t rx_prio_boost;
1050 /* Structure for enhanced command IWN_CMD_BLUETOOTH for 2000 Series. */
1051 struct iwn2000_btcoex_config {
1052 uint8_t flags; /* Cf Flags in iwn6000_btcoex_config */
1055 uint8_t bt3_t7_timer;
1058 uint8_t sample_time;
1059 uint8_t bt3_t2_timer;
1060 uint16_t bt4_reaction;
1061 uint32_t lookup_table[12];
1062 uint16_t bt4_decision;
1065 uint32_t prio_boost; /* size change prior to iwn6000_btcoex_config */
1066 uint8_t reserved; /* added prior to iwn6000_btcoex_config */
1068 uint8_t tx_prio_boost;
1069 uint16_t rx_prio_boost;
1072 struct iwn_btcoex_priotable {
1073 uint8_t calib_init1;
1074 uint8_t calib_init2;
1075 uint8_t calib_periodic_low1;
1076 uint8_t calib_periodic_low2;
1077 uint8_t calib_periodic_high1;
1078 uint8_t calib_periodic_high2;
1082 uint8_t reserved[7];
1085 struct iwn_btcoex_prot {
1088 uint8_t reserved[2];
1091 /* Structure for command IWN_CMD_SET_CRITICAL_TEMP. */
1092 struct iwn_critical_temp {
1096 /* degK <-> degC conversion macros. */
1097 #define IWN_CTOK(c) ((c) + 273)
1098 #define IWN_KTOC(k) ((k) - 273)
1099 #define IWN_CTOMUK(c) (((c) * 1000000) + 273150000)
1102 /* Structures for command IWN_CMD_SET_SENSITIVITY. */
1103 struct iwn_sensitivity_cmd {
1105 #define IWN_SENSITIVITY_DEFAULTTBL 0
1106 #define IWN_SENSITIVITY_WORKTBL 1
1108 uint16_t energy_cck;
1109 uint16_t energy_ofdm;
1110 uint16_t corr_ofdm_x1;
1111 uint16_t corr_ofdm_mrc_x1;
1112 uint16_t corr_cck_mrc_x4;
1113 uint16_t corr_ofdm_x4;
1114 uint16_t corr_ofdm_mrc_x4;
1115 uint16_t corr_barker;
1116 uint16_t corr_barker_mrc;
1117 uint16_t corr_cck_x4;
1118 uint16_t energy_ofdm_th;
1121 struct iwn_enhanced_sensitivity_cmd {
1123 uint16_t energy_cck;
1124 uint16_t energy_ofdm;
1125 uint16_t corr_ofdm_x1;
1126 uint16_t corr_ofdm_mrc_x1;
1127 uint16_t corr_cck_mrc_x4;
1128 uint16_t corr_ofdm_x4;
1129 uint16_t corr_ofdm_mrc_x4;
1130 uint16_t corr_barker;
1131 uint16_t corr_barker_mrc;
1132 uint16_t corr_cck_x4;
1133 uint16_t energy_ofdm_th;
1134 /* "Enhanced" part. */
1135 uint16_t ina_det_ofdm;
1136 uint16_t ina_det_cck;
1137 uint16_t corr_11_9_en;
1138 uint16_t ofdm_det_slope_mrc;
1139 uint16_t ofdm_det_icept_mrc;
1140 uint16_t ofdm_det_slope;
1141 uint16_t ofdm_det_icept;
1142 uint16_t cck_det_slope_mrc;
1143 uint16_t cck_det_icept_mrc;
1144 uint16_t cck_det_slope;
1145 uint16_t cck_det_icept;
1150 * Define maximal number of calib result send to runtime firmware
1151 * PS: TEMP_OFFSET count for 2 (std and v2)
1153 #define IWN5000_PHY_CALIB_MAX_RESULT 8
1155 /* Structures for command IWN_CMD_PHY_CALIB. */
1156 struct iwn_phy_calib {
1158 #define IWN4965_PHY_CALIB_DIFF_GAIN 7
1159 #define IWN5000_PHY_CALIB_DC 8
1160 #define IWN5000_PHY_CALIB_LO 9
1161 #define IWN5000_PHY_CALIB_TX_IQ 11
1162 #define IWN5000_PHY_CALIB_CRYSTAL 15
1163 #define IWN5000_PHY_CALIB_BASE_BAND 16
1164 #define IWN5000_PHY_CALIB_TX_IQ_PERIODIC 17
1165 #define IWN5000_PHY_CALIB_TEMP_OFFSET 18
1167 #define IWN5000_PHY_CALIB_RESET_NOISE_GAIN 18
1168 #define IWN5000_PHY_CALIB_NOISE_GAIN 19
1175 struct iwn5000_phy_calib_crystal {
1182 uint8_t reserved[2];
1185 struct iwn5000_phy_calib_temp_offset {
1191 #define IWN_DEFAULT_TEMP_OFFSET 2700
1196 struct iwn5000_phy_calib_temp_offsetv2 {
1201 int16_t offset_high;
1203 int16_t burnt_voltage_ref;
1207 struct iwn_phy_calib_gain {
1217 /* Structure for command IWN_CMD_SPECTRUM_MEASUREMENT. */
1218 struct iwn_spectrum_cmd {
1235 #define IWN_MEASUREMENT_BASIC (1 << 0)
1236 #define IWN_MEASUREMENT_CCA (1 << 1)
1237 #define IWN_MEASUREMENT_RPI_HISTOGRAM (1 << 2)
1238 #define IWN_MEASUREMENT_NOISE_HISTOGRAM (1 << 3)
1239 #define IWN_MEASUREMENT_FRAME (1 << 4)
1240 #define IWN_MEASUREMENT_IDLE (1 << 7)
1243 } __packed chan[10];
1246 /* Structure for IWN_UC_READY notification. */
1247 #define IWN_NATTEN_GROUPS 5
1248 struct iwn_ucode_info {
1252 uint8_t revision[8];
1255 #define IWN_UCODE_RUNTIME 0
1256 #define IWN_UCODE_INIT 9
1264 /* The following fields are for UCODE_INIT only. */
1270 int32_t atten[IWN_NATTEN_GROUPS][2];
1273 /* Structures for IWN_TX_DONE notification. */
1276 * TX command response is sent after *agn* transmission attempts.
1278 * both postpone and abort status are expected behavior from uCode. there is
1279 * no special operation required from driver; except for RFKILL_FLUSH,
1280 * which required tx flush host command to flush all the tx frames in queues
1282 #define IWN_TX_STATUS_MSK 0x000000ff
1283 #define IWN_TX_STATUS_DELAY_MSK 0x00000040
1284 #define IWN_TX_STATUS_ABORT_MSK 0x00000080
1285 #define IWN_TX_PACKET_MODE_MSK 0x0000ff00
1286 #define IWN_TX_FIFO_NUMBER_MSK 0x00070000
1287 #define IWN_TX_RESERVED 0x00780000
1288 #define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000
1289 #define IWN_TX_ABORT_REQUIRED_MSK 0x80000000
1291 /* Success status */
1292 #define IWN_TX_STATUS_SUCCESS 0x01
1293 #define IWN_TX_STATUS_DIRECT_DONE 0x02
1296 #define IWN_TX_STATUS_POSTPONE_DELAY 0x40
1297 #define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41
1298 #define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42
1299 #define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
1300 #define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44
1303 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */
1304 #define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
1305 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
1306 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
1307 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
1308 #define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85
1309 #define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
1310 #define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
1311 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
1312 #define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89
1313 #define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a
1314 #define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */
1315 #define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
1316 #define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d
1317 #define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
1318 #define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f
1319 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
1320 #define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91
1323 * TX command response for A-MPDU packet responses.
1325 * The status response is different to the non A-MPDU responses.
1326 * In addition, the sequence number is treated as the sequence
1327 * number of the TX command, NOT the 802.11 sequence number!
1329 #define IWN_AGG_TX_STATE_TRANSMITTED 0x00
1330 #define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01
1331 #define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04
1332 #define IWN_AGG_TX_STATE_ABORT_MSK 0x08
1334 #define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10
1335 #define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20
1337 #define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80
1339 #define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100
1341 #define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff
1342 #define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200
1343 #define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400
1345 #define IWN_AGG_TX_STATUS_MSK 0x00000fff
1346 #define IWN_AGG_TX_TRY_MSK 0x0000f000
1348 #define IWN_AGG_TX_STATE_LAST_SENT_MSK \
1349 (IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1350 IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK)
1352 /* # tx attempts for first frame in aggregation */
1353 #define IWN_AGG_TX_STATE_TRY_CNT_POS 12
1354 #define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000
1356 /* Command ID and sequence number of Tx command for this frame */
1357 #define IWN_AGG_TX_STATE_SEQ_NUM_POS 16
1358 #define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1360 struct iwn4965_tx_stat {
1372 struct iwn5000_tx_stat {
1373 uint8_t nframes; /* 1 no aggregation, >1 aggregation */
1385 uint8_t ratid; /* tid (0:3), sta_id (4:7) */
1391 /* Structure for IWN_BEACON_MISSED notification. */
1392 struct iwn_beacon_missed {
1393 uint32_t consecutive;
1399 /* Structure for IWN_MPDU_RX_DONE notification. */
1400 struct iwn_rx_mpdu {
1405 /* Structures for IWN_RX_DONE and IWN_MPDU_RX_DONE notifications. */
1406 struct iwn4965_rx_phystat {
1412 struct iwn5000_rx_phystat {
1418 struct iwn_rx_stat {
1420 uint8_t cfg_phy_len;
1421 #define IWN_STAT_MAXLEN 20
1428 #define IWN_STAT_FLAG_SHPREAMBLE (1 << 2)
1436 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"):
1446 * 4-3: 0) Single stream (SISO)
1447 * 1) Dual stream (MIMO)
1448 * 2) Triple stream (MIMO)
1450 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
1452 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"):
1462 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"):
1473 #define IWN_RSSI_TO_DBM 44
1475 /* Structure for IWN_RX_COMPRESSED_BA notification. */
1476 struct iwn_compressed_ba {
1477 uint8_t macaddr[IEEE80211_ADDR_LEN];
1485 /* extra fields starting with iwn5000 */
1487 uint8_t txed; /* number of frames sent */
1488 uint8_t txed_2_done; /* number of frames acked */
1493 /* Structure for IWN_START_SCAN notification. */
1494 struct iwn_start_scan {
1503 /* Structure for IWN_STOP_SCAN notification. */
1504 struct iwn_stop_scan {
1512 /* Structure for IWN_SPECTRUM_MEASUREMENT notification. */
1513 struct iwn_spectrum_notif {
1518 #define IWN_MEASUREMENT_START 0
1519 #define IWN_MEASUREMENT_STOP 1
1530 uint8_t reserved2[3];
1535 #define IWN_MEASUREMENT_OK 0
1536 #define IWN_MEASUREMENT_CONCURRENT 1
1537 #define IWN_MEASUREMENT_CSA_CONFLICT 2
1538 #define IWN_MEASUREMENT_TGH_CONFLICT 3
1539 #define IWN_MEASUREMENT_STOPPED 6
1540 #define IWN_MEASUREMENT_TIMEOUT 7
1541 #define IWN_MEASUREMENT_FAILED 8
1544 /* Structures for IWN_{RX,BEACON}_STATISTICS notification. */
1545 struct iwn_rx_phy_stats {
1552 uint32_t good_crc32;
1554 uint32_t bad_fina_sync;
1555 uint32_t sfd_timeout;
1556 uint32_t fina_timeout;
1557 uint32_t no_rts_ack;
1568 struct iwn_rx_general_stats {
1575 uint32_t missed_beacons;
1576 uint32_t adc_saturated; /* time in 0.8us */
1577 uint32_t ina_searched; /* time in 0.8us */
1586 struct iwn_rx_ht_phy_stats {
1590 uint32_t good_crc32;
1593 uint32_t good_ampdu_crc32;
1596 uint32_t unsupport_mcs;
1599 struct iwn_rx_stats {
1600 struct iwn_rx_phy_stats ofdm;
1601 struct iwn_rx_phy_stats cck;
1602 struct iwn_rx_general_stats general;
1603 struct iwn_rx_ht_phy_stats ht;
1606 struct iwn_rx_general_stats_bt {
1607 struct iwn_rx_general_stats common;
1608 /* additional stats for bt */
1609 uint32_t num_bt_kills;
1610 uint32_t reserved[2];
1613 struct iwn_rx_stats_bt {
1614 struct iwn_rx_phy_stats ofdm;
1615 struct iwn_rx_phy_stats cck;
1616 struct iwn_rx_general_stats_bt general_bt;
1617 struct iwn_rx_ht_phy_stats ht;
1620 struct iwn_tx_stats {
1622 uint32_t rx_detected;
1626 uint32_t cts_timeout;
1627 uint32_t ack_timeout;
1631 uint32_t burst_err1;
1632 uint32_t burst_err2;
1633 uint32_t cts_collision;
1634 uint32_t ack_collision;
1635 uint32_t ba_timeout;
1636 uint32_t ba_resched;
1637 uint32_t query_ampdu;
1639 uint32_t query_ampdu_frag;
1640 uint32_t query_mismatch;
1643 uint32_t bt_ht_kill;
1644 uint32_t rx_ba_resp;
1646 * 6000 series only - LSB=ant A, ant B, ant C, MSB=reserved
1647 * TX power on chain in 1/2 dBm.
1650 uint32_t reserved[1];
1653 struct iwn_general_stats {
1654 uint32_t temp; /* radio temperature */
1655 uint32_t temp_m; /* radio voltage */
1656 uint32_t burst_check;
1658 uint32_t wait_for_silence_timeout_cnt;
1659 uint32_t reserved1[3];
1663 uint32_t ttl_tstamp;
1668 uint32_t reserved2[2];
1669 uint32_t rx_enabled;
1671 * This is the number of times we have to re-tune
1672 * in order to get out of bad PHY status.
1674 uint32_t num_of_sos_states;
1679 struct iwn_rx_stats rx;
1680 struct iwn_tx_stats tx;
1681 struct iwn_general_stats general;
1682 uint32_t reserved1[2];
1685 struct iwn_bt_activity_stats {
1687 uint32_t hi_priority_tx_req_cnt;
1688 uint32_t hi_priority_tx_denied_cnt;
1689 uint32_t lo_priority_tx_req_cnt;
1690 uint32_t lo_priority_tx_denied_cnt;
1692 uint32_t hi_priority_rx_req_cnt;
1693 uint32_t hi_priority_rx_denied_cnt;
1694 uint32_t lo_priority_rx_req_cnt;
1695 uint32_t lo_priority_rx_denied_cnt;
1698 struct iwn_stats_bt {
1700 struct iwn_rx_stats_bt rx_bt;
1701 struct iwn_tx_stats tx;
1702 struct iwn_general_stats general;
1703 struct iwn_bt_activity_stats activity;
1704 uint32_t reserved1[2];
1707 /* Firmware error dump. */
1708 struct iwn_fw_dump {
1712 uint32_t branch_link[2];
1713 uint32_t interrupt_link[2];
1714 uint32_t error_data[2];
1720 /* TLV firmware header. */
1721 struct iwn_fw_tlv_hdr {
1722 uint32_t zero; /* Always 0, to differentiate from legacy. */
1724 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */
1728 #define IWN_FW_API(x) (((x) >> 8) & 0xff)
1737 #define IWN_FW_TLV_MAIN_TEXT 1
1738 #define IWN_FW_TLV_MAIN_DATA 2
1739 #define IWN_FW_TLV_INIT_TEXT 3
1740 #define IWN_FW_TLV_INIT_DATA 4
1741 #define IWN_FW_TLV_BOOT_TEXT 5
1742 #define IWN_FW_TLV_PBREQ_MAXLEN 6
1743 #define IWN_FW_TLV_PAN 7
1744 #define IWN_FW_TLV_RUNT_EVTLOG_PTR 8
1745 #define IWN_FW_TLV_RUNT_EVTLOG_SIZE 9
1746 #define IWN_FW_TLV_RUNT_ERRLOG_PTR 10
1747 #define IWN_FW_TLV_INIT_EVTLOG_PTR 11
1748 #define IWN_FW_TLV_INIT_EVTLOG_SIZE 12
1749 #define IWN_FW_TLV_INIT_ERRLOG_PTR 13
1750 #define IWN_FW_TLV_ENH_SENS 14
1751 #define IWN_FW_TLV_PHY_CALIB 15
1752 #define IWN_FW_TLV_WOWLAN_INST 16
1753 #define IWN_FW_TLV_WOWLAN_DATA 17
1754 #define IWN_FW_TLV_FLAGS 18
1760 #define IWN4965_FW_TEXT_MAXSZ ( 96 * 1024)
1761 #define IWN4965_FW_DATA_MAXSZ ( 40 * 1024)
1762 #define IWN5000_FW_TEXT_MAXSZ (256 * 1024)
1763 #define IWN5000_FW_DATA_MAXSZ ( 80 * 1024)
1764 #define IWN_FW_BOOT_TEXT_MAXSZ 1024
1765 #define IWN4965_FWSZ (IWN4965_FW_TEXT_MAXSZ + IWN4965_FW_DATA_MAXSZ)
1766 #define IWN5000_FWSZ IWN5000_FW_TEXT_MAXSZ
1769 * Microcode flags TLV (18.)
1773 * enum iwn_ucode_tlv_flag - ucode API flags
1774 * @IWN_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
1775 * was a separate TLV but moved here to save space.
1776 * @IWN_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
1777 * treats good CRC threshold as a boolean
1778 * @IWN_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
1779 * @IWN_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
1780 * @IWN_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
1781 * @IWN_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
1782 * @IWN_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
1783 * offload profile config command.
1784 * @IWN_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
1785 * @IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
1786 * @IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
1787 * (rather than two) IPv6 addresses
1788 * @IWN_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
1789 * @IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
1790 * from the probe request template.
1791 * @IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
1792 * connection when going back to D0
1793 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
1794 * @IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
1795 * @IWN_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
1796 * @IWN_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
1797 * @IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
1798 * containing CAM (Continuous Active Mode) indication.
1800 enum iwn_ucode_tlv_flag {
1801 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0),
1802 IWN_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
1803 IWN_UCODE_TLV_FLAGS_MFP = (1 << 2),
1804 IWN_UCODE_TLV_FLAGS_P2P = (1 << 3),
1805 IWN_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
1806 IWN_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
1807 IWN_UCODE_TLV_FLAGS_UAPSD = (1 << 6),
1808 IWN_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
1809 IWN_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
1810 IWN_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
1811 IWN_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
1812 IWN_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
1813 IWN_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
1814 IWN_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
1815 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
1816 IWN_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
1817 IWN_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
1818 IWN_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
1819 IWN_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
1823 * Offsets into EEPROM.
1825 #define IWN_EEPROM_MAC 0x015
1826 #define IWN_EEPROM_SKU_CAP 0x045
1827 #define IWN_EEPROM_RFCFG 0x048
1828 #define IWN4965_EEPROM_DOMAIN 0x060
1829 #define IWN4965_EEPROM_BAND1 0x063
1830 #define IWN5000_EEPROM_REG 0x066
1831 #define IWN5000_EEPROM_CAL 0x067
1832 #define IWN4965_EEPROM_BAND2 0x072
1833 #define IWN4965_EEPROM_BAND3 0x080
1834 #define IWN4965_EEPROM_BAND4 0x08d
1835 #define IWN4965_EEPROM_BAND5 0x099
1836 #define IWN4965_EEPROM_BAND6 0x0a0
1837 #define IWN4965_EEPROM_BAND7 0x0a8
1838 #define IWN4965_EEPROM_MAXPOW 0x0e8
1839 #define IWN4965_EEPROM_VOLTAGE 0x0e9
1840 #define IWN4965_EEPROM_BANDS 0x0ea
1841 /* Indirect offsets. */
1842 #define IWN5000_EEPROM_NO_HT40 0x000
1843 #define IWN5000_EEPROM_DOMAIN 0x001
1844 #define IWN5000_EEPROM_BAND1 0x004
1845 #define IWN5000_EEPROM_BAND2 0x013
1846 #define IWN5000_EEPROM_BAND3 0x021
1847 #define IWN5000_EEPROM_BAND4 0x02e
1848 #define IWN5000_EEPROM_BAND5 0x03a
1849 #define IWN5000_EEPROM_BAND6 0x041
1850 #define IWN6000_EEPROM_BAND6 0x040
1851 #define IWN5000_EEPROM_BAND7 0x049
1852 #define IWN6000_EEPROM_ENHINFO 0x054
1853 #define IWN5000_EEPROM_CRYSTAL 0x128
1854 #define IWN5000_EEPROM_TEMP 0x12a
1855 #define IWN5000_EEPROM_VOLT 0x12b
1857 /* Possible flags for IWN_EEPROM_SKU_CAP. */
1858 #define IWN_EEPROM_SKU_CAP_11N (1 << 6)
1859 #define IWN_EEPROM_SKU_CAP_AMT (1 << 7)
1860 #define IWN_EEPROM_SKU_CAP_IPAN (1 << 8)
1862 /* Possible flags for IWN_EEPROM_RFCFG. */
1863 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1864 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1865 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1866 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1867 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1869 struct iwn_eeprom_chan {
1871 #define IWN_EEPROM_CHAN_VALID (1 << 0)
1872 #define IWN_EEPROM_CHAN_IBSS (1 << 1)
1873 #define IWN_EEPROM_CHAN_ACTIVE (1 << 3)
1874 #define IWN_EEPROM_CHAN_RADAR (1 << 4)
1879 struct iwn_eeprom_enhinfo {
1881 #define IWN_ENHINFO_VALID 0x01
1882 #define IWN_ENHINFO_5GHZ 0x02
1883 #define IWN_ENHINFO_OFDM 0x04
1884 #define IWN_ENHINFO_HT40 0x08
1885 #define IWN_ENHINFO_HTAP 0x10
1886 #define IWN_ENHINFO_RES1 0x20
1887 #define IWN_ENHINFO_RES2 0x40
1888 #define IWN_ENHINFO_COMMON 0x80
1891 int8_t chain[3]; /* max power in half-dBm */
1893 int8_t mimo2; /* max power in half-dBm */
1894 int8_t mimo3; /* max power in half-dBm */
1897 struct iwn5000_eeprom_calib_hdr {
1903 #define IWN_NSAMPLES 3
1904 struct iwn4965_eeprom_chan_samples {
1911 } samples[2][IWN_NSAMPLES];
1914 #define IWN_NBANDS 8
1915 struct iwn4965_eeprom_band {
1916 uint8_t lo; /* low channel number */
1917 uint8_t hi; /* high channel number */
1918 struct iwn4965_eeprom_chan_samples chans[2];
1922 * Offsets of channels descriptions in EEPROM.
1924 static const uint32_t iwn4965_regulatory_bands[IWN_NBANDS] = {
1925 IWN4965_EEPROM_BAND1,
1926 IWN4965_EEPROM_BAND2,
1927 IWN4965_EEPROM_BAND3,
1928 IWN4965_EEPROM_BAND4,
1929 IWN4965_EEPROM_BAND5,
1930 IWN4965_EEPROM_BAND6,
1931 IWN4965_EEPROM_BAND7
1934 static const uint32_t iwn5000_regulatory_bands[IWN_NBANDS] = {
1935 IWN5000_EEPROM_BAND1,
1936 IWN5000_EEPROM_BAND2,
1937 IWN5000_EEPROM_BAND3,
1938 IWN5000_EEPROM_BAND4,
1939 IWN5000_EEPROM_BAND5,
1940 IWN5000_EEPROM_BAND6,
1941 IWN5000_EEPROM_BAND7
1944 static const uint32_t iwn6000_regulatory_bands[IWN_NBANDS] = {
1945 IWN5000_EEPROM_BAND1,
1946 IWN5000_EEPROM_BAND2,
1947 IWN5000_EEPROM_BAND3,
1948 IWN5000_EEPROM_BAND4,
1949 IWN5000_EEPROM_BAND5,
1950 IWN6000_EEPROM_BAND6,
1951 IWN5000_EEPROM_BAND7
1954 static const uint32_t iwn1000_regulatory_bands[IWN_NBANDS] = {
1955 IWN5000_EEPROM_BAND1,
1956 IWN5000_EEPROM_BAND2,
1957 IWN5000_EEPROM_BAND3,
1958 IWN5000_EEPROM_BAND4,
1959 IWN5000_EEPROM_BAND5,
1960 IWN5000_EEPROM_BAND6,
1961 IWN5000_EEPROM_NO_HT40,
1964 static const uint32_t iwn2030_regulatory_bands[IWN_NBANDS] = {
1965 IWN5000_EEPROM_BAND1,
1966 IWN5000_EEPROM_BAND2,
1967 IWN5000_EEPROM_BAND3,
1968 IWN5000_EEPROM_BAND4,
1969 IWN5000_EEPROM_BAND5,
1970 IWN6000_EEPROM_BAND6,
1971 IWN5000_EEPROM_BAND7
1974 #define IWN_CHAN_BANDS_COUNT 7
1975 #define IWN_MAX_CHAN_PER_BAND 14
1976 static const struct iwn_chan_band {
1978 uint8_t chan[IWN_MAX_CHAN_PER_BAND];
1980 /* 20MHz channels, 2GHz band. */
1981 { 14, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } },
1982 /* 20MHz channels, 5GHz band. */
1983 { 13, { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } },
1984 { 12, { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } },
1985 { 11, { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } },
1986 { 6, { 145, 149, 153, 157, 161, 165 } },
1987 /* 40MHz channels (primary channels), 2GHz band. */
1988 { 7, { 1, 2, 3, 4, 5, 6, 7 } },
1989 /* 40MHz channels (primary channels), 5GHz band. */
1990 { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } }
1993 static const uint8_t iwn_bss_ac_to_queue[] = {
1997 static const uint8_t iwn_pan_ac_to_queue[] = {
2000 #define IWN1000_OTP_NBLOCKS 3
2001 #define IWN6000_OTP_NBLOCKS 4
2002 #define IWN6050_OTP_NBLOCKS 7
2004 /* HW rate indices. */
2005 #define IWN_RIDX_CCK1 0
2006 #define IWN_RIDX_OFDM6 4
2008 #define IWN4965_MAX_PWR_INDEX 107
2009 #define IWN_POWERSAVE_LVL_NONE 0
2010 #define IWN_POWERSAVE_LVL_VOIP_COMPATIBLE 1
2011 #define IWN_POWERSAVE_LVL_MAX 5
2013 #define IWN_POWERSAVE_LVL_DEFAULT IWN_POWERSAVE_LVL_NONE
2015 /* DTIM value to pass in for IWN_POWERSAVE_LVL_VOIP_COMPATIBLE */
2016 #define IWN_POWERSAVE_DTIM_VOIP_COMPATIBLE 2
2019 * RF Tx gain values from highest to lowest power (values obtained from
2020 * the reference driver.)
2022 static const uint8_t iwn4965_rf_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2023 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
2024 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
2025 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
2026 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
2027 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
2028 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
2029 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2030 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2031 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2032 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
2035 static const uint8_t iwn4965_rf_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2036 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
2037 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
2038 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
2039 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
2040 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
2041 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
2042 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
2043 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
2044 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
2045 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
2049 * DSP pre-DAC gain values from highest to lowest power (values obtained
2050 * from the reference driver.)
2052 static const uint8_t iwn4965_dsp_gain_2ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2053 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2054 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2055 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2056 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2057 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2058 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2059 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
2060 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
2061 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
2062 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
2065 static const uint8_t iwn4965_dsp_gain_5ghz[IWN4965_MAX_PWR_INDEX + 1] = {
2066 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2067 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2068 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2069 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2070 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2071 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2072 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2073 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2074 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2075 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
2079 * Power saving settings (values obtained from the reference driver.)
2081 #define IWN_NDTIMRANGES 3
2082 #define IWN_NPOWERLEVELS 6
2083 static const struct iwn_pmgt {
2088 } iwn_pmgt[IWN_NDTIMRANGES][IWN_NPOWERLEVELS] = {
2091 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
2092 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
2093 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
2094 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
2095 { 50, 25, { 2, 2, 4, 4, -1 }, 1 }, /* PS level 4 */
2096 { 25, 25, { 2, 2, 4, 6, -1 }, 2 } /* PS level 5 */
2098 /* 3 <= DTIM <= 10 */
2100 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
2101 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
2102 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
2103 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
2104 { 50, 25, { 2, 4, 6, 9, 10 }, 1 }, /* PS level 4 */
2105 { 25, 25, { 2, 4, 7, 10, 10 }, 2 } /* PS level 5 */
2109 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
2110 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
2111 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
2112 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
2113 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
2114 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
2118 struct iwn_sensitivity_limits {
2119 uint32_t min_ofdm_x1;
2120 uint32_t max_ofdm_x1;
2121 uint32_t min_ofdm_mrc_x1;
2122 uint32_t max_ofdm_mrc_x1;
2123 uint32_t min_ofdm_x4;
2124 uint32_t max_ofdm_x4;
2125 uint32_t min_ofdm_mrc_x4;
2126 uint32_t max_ofdm_mrc_x4;
2127 uint32_t min_cck_x4;
2128 uint32_t max_cck_x4;
2129 uint32_t min_cck_mrc_x4;
2130 uint32_t max_cck_mrc_x4;
2131 uint32_t min_energy_cck;
2132 uint32_t energy_cck;
2133 uint32_t energy_ofdm;
2134 uint32_t barker_mrc;
2138 * RX sensitivity limits (values obtained from the reference driver.)
2140 static const struct iwn_sensitivity_limits iwn4965_sensitivity_limits = {
2153 static const struct iwn_sensitivity_limits iwn5000_sensitivity_limits = {
2154 120, 120, /* min = max for performance bug in DSP. */
2155 240, 240, /* min = max for performance bug in DSP. */
2166 static const struct iwn_sensitivity_limits iwn5150_sensitivity_limits = {
2167 105, 105, /* min = max for performance bug in DSP. */
2168 220, 220, /* min = max for performance bug in DSP. */
2179 static const struct iwn_sensitivity_limits iwn1000_sensitivity_limits = {
2192 static const struct iwn_sensitivity_limits iwn6000_sensitivity_limits = {
2205 static const struct iwn_sensitivity_limits iwn6235_sensitivity_limits = {
2219 /* Get value from linux kernel 3.2.+ in Drivers/net/wireless/iwlwifi/iwl-2000.c*/
2220 static const struct iwn_sensitivity_limits iwn2030_sensitivity_limits = {
2232 /* Map TID to TX scheduler's FIFO. */
2233 static const uint8_t iwn_tid2fifo[] = {
2234 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
2237 /* WiFi/WiMAX coexist event priority table for 6050. */
2238 static const struct iwn5000_wimax_event iwn6050_wimax_events[] = {
2239 { 0x04, 0x03, 0x00, 0x00 },
2240 { 0x04, 0x03, 0x00, 0x03 },
2241 { 0x04, 0x03, 0x00, 0x03 },
2242 { 0x04, 0x03, 0x00, 0x03 },
2243 { 0x04, 0x03, 0x00, 0x00 },
2244 { 0x04, 0x03, 0x00, 0x07 },
2245 { 0x04, 0x03, 0x00, 0x00 },
2246 { 0x04, 0x03, 0x00, 0x03 },
2247 { 0x04, 0x03, 0x00, 0x03 },
2248 { 0x04, 0x03, 0x00, 0x00 },
2249 { 0x06, 0x03, 0x00, 0x07 },
2250 { 0x04, 0x03, 0x00, 0x00 },
2251 { 0x06, 0x06, 0x00, 0x03 },
2252 { 0x04, 0x03, 0x00, 0x07 },
2253 { 0x04, 0x03, 0x00, 0x00 },
2254 { 0x04, 0x03, 0x00, 0x00 }
2257 /* Firmware errors. */
2258 static const char * const iwn_fw_errmsg[] = {
2263 "NMI_INTERRUPT_WDG",
2267 "HW_ERROR_TUNE_LOCK",
2268 "HW_ERROR_TEMPERATURE",
2269 "ILLEGAL_CHAN_FREQ",
2272 "NMI_INTERRUPT_HOST",
2273 "NMI_INTERRUPT_ACTION_PT",
2274 "NMI_INTERRUPT_UNKNOWN",
2275 "UCODE_VERSION_MISMATCH",
2276 "HW_ERROR_ABS_LOCK",
2277 "HW_ERROR_CAL_LOCK_FAIL",
2278 "NMI_INTERRUPT_INST_ACTION_PT",
2279 "NMI_INTERRUPT_DATA_ACTION_PT",
2281 "NMI_INTERRUPT_TRM",
2282 "NMI_INTERRUPT_BREAKPOINT",
2287 "ADVANCED_SYSASSERT"
2290 /* Find least significant bit that is set. */
2291 #define IWN_LSB(x) ((((x) - 1) & (x)) ^ (x))
2293 #define IWN_READ(sc, reg) \
2294 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
2296 #define IWN_WRITE(sc, reg, val) \
2297 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
2299 #define IWN_WRITE_1(sc, reg, val) \
2300 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
2302 #define IWN_SETBITS(sc, reg, mask) \
2303 IWN_WRITE(sc, reg, IWN_READ(sc, reg) | (mask))
2305 #define IWN_CLRBITS(sc, reg, mask) \
2306 IWN_WRITE(sc, reg, IWN_READ(sc, reg) & ~(mask))
2308 #define IWN_BARRIER_WRITE(sc) \
2309 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
2310 BUS_SPACE_BARRIER_WRITE)
2312 #define IWN_BARRIER_READ_WRITE(sc) \
2313 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
2314 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
2316 #endif /* __IF_IWNREG_H__ */