1 /*******************************************************************************
3 Copyright (c) 2001-2004, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 *******************************************************************************/
39 #define IXGB_EEPROM_SIZE 64 /* Size in words */
41 #define IXGB_ETH_LENGTH_OF_ADDRESS 6
45 #define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
46 #define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
47 #define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
48 #define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
49 #define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
51 /* EEPROM MAP (Word Offsets) */
52 #define EEPROM_IA_1_2_REG 0x0000
53 #define EEPROM_IA_3_4_REG 0x0001
54 #define EEPROM_IA_5_6_REG 0x0002
55 #define EEPROM_COMPATIBILITY_REG 0x0003
56 #define EEPROM_PBA_1_2_REG 0x0008
57 #define EEPROM_PBA_3_4_REG 0x0009
58 #define EEPROM_INIT_CONTROL1_REG 0x000A
59 #define EEPROM_SUBSYS_ID_REG 0x000B
60 #define EEPROM_SUBVEND_ID_REG 0x000C
61 #define EEPROM_DEVICE_ID_REG 0x000D
62 #define EEPROM_VENDOR_ID_REG 0x000E
63 #define EEPROM_INIT_CONTROL2_REG 0x000F
64 #define EEPROM_SWDPINS_REG 0x0020
65 #define EEPROM_CIRCUIT_CTRL_REG 0x0021
66 #define EEPROM_D0_D3_POWER_REG 0x0022
67 #define EEPROM_FLASH_VERSION 0x0032
68 #define EEPROM_CHECKSUM_REG 0x003F
70 /* Mask bits for fields in Word 0x0a of the EEPROM */
72 #define EEPROM_ICW1_SIGNATURE_MASK 0xC000
73 #define EEPROM_ICW1_SIGNATURE_VALID 0x4000
75 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
76 #define EEPROM_SUM 0xBABA
78 /* EEPROM Map Sizes (Byte Counts) */
81 /* EEPROM Map defines (WORD OFFSETS)*/
83 /* EEPROM structure */
84 struct ixgb_ee_map_type{
85 uint8_t mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS];
86 uint16_t compatibility;
87 uint16_t reserved1[4];
89 uint16_t init_ctrl_reg_1;
90 uint16_t subsystem_id;
91 uint16_t subvendor_id;
94 uint16_t init_ctrl_reg_2;
95 uint16_t oem_reserved[16];
97 uint16_t circuit_ctrl_reg;
100 uint16_t reserved2[28];
104 /* EEPROM Functions */
105 uint16_t ixgb_read_eeprom(struct ixgb_hw *hw,
108 boolean_t ixgb_validate_eeprom_checksum(struct ixgb_hw *hw);
110 void ixgb_update_eeprom_checksum(struct ixgb_hw *hw);
112 void ixgb_write_eeprom(struct ixgb_hw *hw,
116 #endif /* IXGB_EE_H */