1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
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14 notice, this list of conditions and the following disclaimer in the
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31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/buf_ring.h>
42 #include <sys/protosw.h>
43 #include <sys/socket.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/sockio.h>
48 #include <sys/eventhandler.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/if_vlan_var.h>
60 #include <net/iflib.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in.h>
64 #include <netinet/if_ether.h>
67 #include <machine/bus.h>
69 #include <machine/resource.h>
72 #include <machine/clock.h>
73 #include <dev/pci/pcivar.h>
74 #include <dev/pci/pcireg.h>
76 #include <sys/sysctl.h>
77 #include <sys/endian.h>
78 #include <sys/gtaskqueue.h>
81 #include <machine/smp.h>
84 #include "ixgbe_api.h"
85 #include "ixgbe_common.h"
86 #include "ixgbe_phy.h"
88 #include "ixgbe_features.h"
93 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
94 * number of transmit descriptors allocated by the driver. Increasing this
95 * value allows the driver to queue more transmits. Each descriptor is 16
96 * bytes. Performance tests have show the 2K value to be optimal for top
99 #define DEFAULT_TXD 2048
100 #define PERFORM_TXD 2048
105 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the
106 * number of receive descriptors allocated for each RX queue. Increasing this
107 * value allows the driver to buffer more incoming packets. Each descriptor
108 * is 16 bytes. A receive buffer is also allocated for each descriptor.
110 * Note: with 8 rings and a dual port card, it is possible to bump up
111 * against the system mbuf pool limit, you can tune nmbclusters
112 * to adjust for this.
114 #define DEFAULT_RXD 2048
115 #define PERFORM_RXD 2048
119 /* Alignment for rings */
120 #define DBA_ALIGN 128
123 * This is the max watchdog interval, ie. the time that can
124 * pass between any two TX clean operations, such only happening
125 * when the TX hardware is functioning.
127 #define IXGBE_WATCHDOG (10 * hz)
130 * This parameters control when the driver calls the routine to reclaim
131 * transmit descriptors.
133 #define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8)
134 #define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32)
136 /* These defines are used in MTU calculations */
137 #define IXGBE_MAX_FRAME_SIZE 9728
138 #define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN)
139 #define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \
140 ETHER_VLAN_ENCAP_LEN)
141 #define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR)
142 #define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN)
144 /* Flow control constants */
145 #define IXGBE_FC_PAUSE 0xFFFF
146 #define IXGBE_FC_HI 0x20000
147 #define IXGBE_FC_LO 0x10000
150 * Used for optimizing small rx mbufs. Effort is made to keep the copy
151 * small and aligned for the CPU L1 cache.
153 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting
154 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
155 * wasted. Getting 64 byte alignment, which _should_ be ideal for
156 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
157 * in observed efficiency of the optimization, 97.9% -> 81.8%.
159 #define IXGBE_MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr))
161 #define IXGBE_RX_COPY_HDR_PADDED ((((IXGBE_MPKTHSIZE - 1) / 32) + 1) * 32)
162 #define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED)
163 #define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - IXGBE_MPKTHSIZE)
165 /* Defines for printing debug information */
167 #define DEBUG_IOCTL 0
170 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
171 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
172 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
173 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
174 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
175 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
176 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
177 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
178 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
180 #define MAX_NUM_MULTICAST_ADDRESSES 128
181 #define IXGBE_82598_SCATTER 100
182 #define IXGBE_82599_SCATTER 32
183 #define IXGBE_TSO_SIZE 262140
184 #define IXGBE_RX_HDR 128
185 #define IXGBE_VFTA_SIZE 128
186 #define IXGBE_BR_SIZE 4096
187 #define IXGBE_QUEUE_MIN_FREE 32
188 #define IXGBE_MAX_TX_BUSY 10
189 #define IXGBE_QUEUE_HUNG 0x80000000
191 #define IXGBE_EITR_DEFAULT 128
193 /* Supported offload bits in mbuf flag */
194 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
195 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
196 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
198 #define IXGBE_CAPS (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_TSO | \
199 IFCAP_LRO | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO | \
200 IFCAP_VLAN_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU | \
201 IFCAP_VLAN_HWFILTER | IFCAP_WOL)
203 #ifndef DEVMETHOD_END
204 #define DEVMETHOD_END { NULL, NULL }
208 * Interrupt Moderation parameters
210 #define IXGBE_LOW_LATENCY 128
211 #define IXGBE_AVE_LATENCY 400
212 #define IXGBE_BULK_LATENCY 1200
214 /* Using 1FF (the max value), the interval is ~1.05ms */
215 #define IXGBE_LINK_ITR_QUANTA 0x1FF
216 #define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \
217 IXGBE_EITR_ITR_INT_MASK)
220 /************************************************************************
223 * Contains the list of Subvendor/Subdevice IDs on
224 * which the driver should load.
225 ************************************************************************/
226 typedef struct _ixgbe_vendor_info_t {
227 unsigned int vendor_id;
228 unsigned int device_id;
229 unsigned int subvendor_id;
230 unsigned int subdevice_id;
232 } ixgbe_vendor_info_t;
234 struct ixgbe_bp_data {
243 struct ixgbe_dma_alloc {
244 bus_addr_t dma_paddr;
246 bus_dma_tag_t dma_tag;
247 bus_dmamap_t dma_map;
248 bus_dma_segment_t dma_seg;
253 struct ixgbe_mc_addr {
254 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
259 * The transmit ring, one per queue
262 struct ixgbe_softc *sc;
263 union ixgbe_adv_tx_desc *tx_base;
269 qidx_t tx_cidx_processed;
276 u32 bytes; /* used for AIM */
285 * The Receive ring, one per rx queue
288 struct ix_rx_queue *que;
289 struct ixgbe_softc *sc;
292 union ixgbe_adv_rx_desc *rx_base;
298 u32 bytes; /* Used for AIM calc */
314 * Driver queue struct: this is the interrupt container
315 * for the associated tx and rx ring.
318 struct ixgbe_softc *sc;
319 u32 msix; /* This queue's MSIX vector */
321 struct resource *res;
325 struct if_irq que_irq;
330 struct ixgbe_softc *sc;
331 u32 msix; /* This queue's MSIX vector */
335 #define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */
340 u_int maximum_frame_size;
342 uint8_t ether_addr[ETHER_ADDR_LEN];
343 uint16_t mc_hash[IXGBE_MAX_VF_MC];
344 uint16_t num_mc_hashes;
345 uint16_t default_vlan;
350 /* Our softc structure */
353 struct ixgbe_osdep osdep;
355 if_softc_ctx_t shared;
356 #define num_tx_queues shared->isc_ntxqsets
357 #define num_rx_queues shared->isc_nrxqsets
358 #define max_frame_size shared->isc_max_frame_size
359 #define intr_type shared->isc_intr
364 struct resource *pci_mem;
367 * Interrupt resources: this set is
368 * either used for legacy, or for Link
373 struct resource *res;
375 struct ifmedia *media;
382 * Shadow VFTA table, this is needed because
383 * the real vlan filter table gets cleared during
384 * a soft reset and the driver needs to be able
387 u32 shadow_vfta[IXGBE_VFTA_SIZE];
389 /* Info about the interface */
390 int advertise; /* link speeds */
391 int enable_aim; /* adaptive interrupt moderation */
401 /* Power management-related */
405 /* Mbuf cluster size */
408 /* Support for pluggable optics */
418 * This is the irq holder, it has
419 * and RX/TX pair or rings associated
422 struct ix_tx_queue *tx_queues;
423 struct ix_rx_queue *rx_queues;
425 /* Multicast array memory */
426 struct ixgbe_mc_addr *mta;
432 struct ixgbe_vf *vfs;
435 struct ixgbe_bp_data bypass;
437 /* Misc stats maintained by the driver */
438 unsigned long dropped_pkts;
439 unsigned long mbuf_header_failed;
440 unsigned long mbuf_packet_failed;
441 unsigned long watchdog_events;
442 unsigned long link_irq;
444 struct ixgbe_hw_stats pf;
445 struct ixgbevf_hw_stats vf;
448 /* counter(9) stats */
460 /* Feature capable/enabled flags. See ixgbe_features.h */
465 /* Precision Time Sync (IEEE 1588) defines */
466 #define ETHERTYPE_IEEE1588 0x88F7
467 #define PICOSECS_PER_TICK 20833
468 #define TSYNC_UDP_PORT 319 /* UDP port for the protocol */
469 #define IXGBE_ADVTXD_TSTAMP 0x00080000
472 #define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count)
473 #define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count)
474 #define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count)
475 #define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count)
476 #define IXGBE_SET_COLLISIONS(sc, count)
477 #define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count)
478 #define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count)
479 #define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count)
480 #define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count)
481 #define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count)
483 /* External PHY register addresses */
484 #define IXGBE_PHY_CURRENT_TEMP 0xC820
485 #define IXGBE_PHY_OVERTEMP_STATUS 0xC830
487 /* Sysctl help messages; displayed with sysctl -d */
488 #define IXGBE_SYSCTL_DESC_ADV_SPEED \
489 "\nControl advertised link speed using these flags:\n" \
490 "\t0x1 - advertise 100M\n" \
491 "\t0x2 - advertise 1G\n" \
492 "\t0x4 - advertise 10G\n" \
493 "\t0x8 - advertise 10M\n\n" \
494 "\t0x10 - advertise 2.5G\n" \
495 "\t0x20 - advertise 5G\n\n" \
496 "\t100M and 10M are only supported on certain adapters.\n"
498 #define IXGBE_SYSCTL_DESC_SET_FC \
499 "\nSet flow control mode using these values:\n" \
503 "\t3 - tx and rx pause"
505 #define IXGBE_SYSCTL_DESC_RX_ERRS \
506 "\nSum of the following RX errors counters:\n" \
508 " * illegal byte error count,\n" \
509 " * missed packet count,\n" \
510 " * length error count,\n" \
511 " * undersized packets count,\n" \
512 " * fragmented packets count,\n" \
513 " * oversized packets count,\n" \
517 * This checks for a zero mac addr, something that will be likely
518 * unless the Admin on the Host has created one.
521 ixv_check_ether_addr(u8 *addr)
525 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 &&
526 addr[3] == 0 && addr[4]== 0 && addr[5] == 0))
532 uint64_t ixgbe_link_speed_to_baudrate(ixgbe_link_speed speed);
534 /* Shared Prototypes */
536 int ixgbe_allocate_queues(struct ixgbe_softc *);
537 int ixgbe_setup_transmit_structures(struct ixgbe_softc *);
538 void ixgbe_free_transmit_structures(struct ixgbe_softc *);
539 int ixgbe_setup_receive_structures(struct ixgbe_softc *);
540 void ixgbe_free_receive_structures(struct ixgbe_softc *);
541 int ixgbe_get_regs(SYSCTL_HANDLER_ARGS);
543 #include "ixgbe_bypass.h"
544 #include "ixgbe_fdir.h"
545 #include "ixgbe_rss.h"
547 #endif /* _IXGBE_H_ */