1 /******************************************************************************
3 Copyright (c) 2001-2009, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_common.h"
36 #include "ixgbe_api.h"
38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
52 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
55 * ixgbe_init_ops_generic - Inits function ptrs
56 * @hw: pointer to the hardware structure
58 * Initialize the function pointers.
60 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
63 struct ixgbe_mac_info *mac = &hw->mac;
64 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
68 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
70 eeprom->ops.read = &ixgbe_read_eeprom_generic;
72 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
73 eeprom->ops.write = &ixgbe_write_eeprom_generic;
74 eeprom->ops.validate_checksum =
75 &ixgbe_validate_eeprom_checksum_generic;
76 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
79 mac->ops.init_hw = &ixgbe_init_hw_generic;
80 mac->ops.reset_hw = NULL;
81 mac->ops.start_hw = &ixgbe_start_hw_generic;
82 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
83 mac->ops.get_media_type = NULL;
84 mac->ops.get_supported_physical_layer = NULL;
85 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
86 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
87 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
88 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
89 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
92 mac->ops.led_on = &ixgbe_led_on_generic;
93 mac->ops.led_off = &ixgbe_led_off_generic;
94 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
95 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
97 /* RAR, Multicast, VLAN */
98 mac->ops.set_rar = &ixgbe_set_rar_generic;
99 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
100 mac->ops.insert_mac_addr = NULL;
101 mac->ops.set_vmdq = NULL;
102 mac->ops.clear_vmdq = NULL;
103 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
104 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
105 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
106 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
107 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
108 mac->ops.clear_vfta = NULL;
109 mac->ops.set_vfta = NULL;
110 mac->ops.init_uta_tables = NULL;
113 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
116 mac->ops.get_link_capabilities = NULL;
117 mac->ops.setup_link = NULL;
118 mac->ops.setup_link_speed = NULL;
119 mac->ops.check_link = NULL;
121 return IXGBE_SUCCESS;
125 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
126 * @hw: pointer to hardware structure
128 * Starts the hardware by filling the bus info structure and media type, clears
129 * all on chip counters, initializes receive address registers, multicast
130 * table, VLAN filter table, calls routine to set up link and flow control
131 * settings, and leaves transmit and receive units disabled and uninitialized
133 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
136 s32 ret_val = IXGBE_SUCCESS;
138 /* Set the media type */
139 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
141 /* PHY ops initialization must be done in reset_hw() */
143 /* Clear the VLAN filter table */
144 hw->mac.ops.clear_vfta(hw);
146 /* Clear statistics registers */
147 hw->mac.ops.clear_hw_cntrs(hw);
149 /* Set No Snoop Disable */
150 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
151 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
152 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
153 IXGBE_WRITE_FLUSH(hw);
155 /* Setup flow control */
156 ixgbe_setup_fc(hw, 0);
158 /* Clear adapter stopped flag */
159 hw->adapter_stopped = FALSE;
165 * ixgbe_init_hw_generic - Generic hardware initialization
166 * @hw: pointer to hardware structure
168 * Initialize the hardware by resetting the hardware, filling the bus info
169 * structure and media type, clears all on chip counters, initializes receive
170 * address registers, multicast table, VLAN filter table, calls routine to set
171 * up link and flow control settings, and leaves transmit and receive units
172 * disabled and uninitialized
174 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
176 s32 status = IXGBE_SUCCESS;
178 /* Reset the hardware */
179 status = hw->mac.ops.reset_hw(hw);
181 if (status == IXGBE_SUCCESS) {
183 status = hw->mac.ops.start_hw(hw);
190 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
191 * @hw: pointer to hardware structure
193 * Clears all hardware statistics counters by reading them from the hardware
194 * Statistics counters are clear on read.
196 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
200 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
201 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
202 IXGBE_READ_REG(hw, IXGBE_ERRBC);
203 IXGBE_READ_REG(hw, IXGBE_MSPDC);
204 for (i = 0; i < 8; i++)
205 IXGBE_READ_REG(hw, IXGBE_MPC(i));
207 IXGBE_READ_REG(hw, IXGBE_MLFC);
208 IXGBE_READ_REG(hw, IXGBE_MRFC);
209 IXGBE_READ_REG(hw, IXGBE_RLEC);
210 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
211 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
212 if (hw->mac.type >= ixgbe_mac_82599EB) {
213 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
214 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
216 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
217 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
220 for (i = 0; i < 8; i++) {
221 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
222 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
223 if (hw->mac.type >= ixgbe_mac_82599EB) {
224 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
225 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
227 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
228 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
231 if (hw->mac.type >= ixgbe_mac_82599EB)
232 for (i = 0; i < 8; i++)
233 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
234 IXGBE_READ_REG(hw, IXGBE_PRC64);
235 IXGBE_READ_REG(hw, IXGBE_PRC127);
236 IXGBE_READ_REG(hw, IXGBE_PRC255);
237 IXGBE_READ_REG(hw, IXGBE_PRC511);
238 IXGBE_READ_REG(hw, IXGBE_PRC1023);
239 IXGBE_READ_REG(hw, IXGBE_PRC1522);
240 IXGBE_READ_REG(hw, IXGBE_GPRC);
241 IXGBE_READ_REG(hw, IXGBE_BPRC);
242 IXGBE_READ_REG(hw, IXGBE_MPRC);
243 IXGBE_READ_REG(hw, IXGBE_GPTC);
244 IXGBE_READ_REG(hw, IXGBE_GORCL);
245 IXGBE_READ_REG(hw, IXGBE_GORCH);
246 IXGBE_READ_REG(hw, IXGBE_GOTCL);
247 IXGBE_READ_REG(hw, IXGBE_GOTCH);
248 for (i = 0; i < 8; i++)
249 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
250 IXGBE_READ_REG(hw, IXGBE_RUC);
251 IXGBE_READ_REG(hw, IXGBE_RFC);
252 IXGBE_READ_REG(hw, IXGBE_ROC);
253 IXGBE_READ_REG(hw, IXGBE_RJC);
254 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
255 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
256 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
257 IXGBE_READ_REG(hw, IXGBE_TORL);
258 IXGBE_READ_REG(hw, IXGBE_TORH);
259 IXGBE_READ_REG(hw, IXGBE_TPR);
260 IXGBE_READ_REG(hw, IXGBE_TPT);
261 IXGBE_READ_REG(hw, IXGBE_PTC64);
262 IXGBE_READ_REG(hw, IXGBE_PTC127);
263 IXGBE_READ_REG(hw, IXGBE_PTC255);
264 IXGBE_READ_REG(hw, IXGBE_PTC511);
265 IXGBE_READ_REG(hw, IXGBE_PTC1023);
266 IXGBE_READ_REG(hw, IXGBE_PTC1522);
267 IXGBE_READ_REG(hw, IXGBE_MPTC);
268 IXGBE_READ_REG(hw, IXGBE_BPTC);
269 for (i = 0; i < 16; i++) {
270 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
271 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
272 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
273 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
276 return IXGBE_SUCCESS;
280 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
281 * @hw: pointer to hardware structure
282 * @pba_num: stores the part number from the EEPROM
284 * Reads the part number from the EEPROM.
286 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
291 DEBUGFUNC("ixgbe_read_pba_num_generic");
293 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
295 DEBUGOUT("NVM Read Error\n");
298 *pba_num = (u32)(data << 16);
300 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
302 DEBUGOUT("NVM Read Error\n");
307 return IXGBE_SUCCESS;
311 * ixgbe_get_mac_addr_generic - Generic get MAC address
312 * @hw: pointer to hardware structure
313 * @mac_addr: Adapter MAC address
315 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
316 * A reset of the adapter must be performed prior to calling this function
317 * in order for the MAC address to have been loaded from the EEPROM into RAR0
319 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
325 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
326 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
328 for (i = 0; i < 4; i++)
329 mac_addr[i] = (u8)(rar_low >> (i*8));
331 for (i = 0; i < 2; i++)
332 mac_addr[i+4] = (u8)(rar_high >> (i*8));
334 return IXGBE_SUCCESS;
338 * ixgbe_get_bus_info_generic - Generic set PCI bus info
339 * @hw: pointer to hardware structure
341 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
343 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
345 struct ixgbe_mac_info *mac = &hw->mac;
348 hw->bus.type = ixgbe_bus_type_pci_express;
350 /* Get the negotiated link width and speed from PCI config space */
351 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
353 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
354 case IXGBE_PCI_LINK_WIDTH_1:
355 hw->bus.width = ixgbe_bus_width_pcie_x1;
357 case IXGBE_PCI_LINK_WIDTH_2:
358 hw->bus.width = ixgbe_bus_width_pcie_x2;
360 case IXGBE_PCI_LINK_WIDTH_4:
361 hw->bus.width = ixgbe_bus_width_pcie_x4;
363 case IXGBE_PCI_LINK_WIDTH_8:
364 hw->bus.width = ixgbe_bus_width_pcie_x8;
367 hw->bus.width = ixgbe_bus_width_unknown;
371 switch (link_status & IXGBE_PCI_LINK_SPEED) {
372 case IXGBE_PCI_LINK_SPEED_2500:
373 hw->bus.speed = ixgbe_bus_speed_2500;
375 case IXGBE_PCI_LINK_SPEED_5000:
376 hw->bus.speed = ixgbe_bus_speed_5000;
379 hw->bus.speed = ixgbe_bus_speed_unknown;
383 mac->ops.set_lan_id(hw);
385 return IXGBE_SUCCESS;
389 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
390 * @hw: pointer to the HW structure
392 * Determines the LAN function id by reading memory-mapped registers
393 * and swaps the port value if requested.
395 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
397 struct ixgbe_bus_info *bus = &hw->bus;
400 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
401 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
402 bus->lan_id = bus->func;
404 /* check for a port swap */
405 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
406 if (reg & IXGBE_FACTPS_LFS)
411 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
412 * @hw: pointer to hardware structure
414 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
415 * disables transmit and receive units. The adapter_stopped flag is used by
416 * the shared code and drivers to determine if the adapter is in a stopped
417 * state and should not touch the hardware.
419 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
421 u32 number_of_queues;
426 * Set the adapter_stopped flag so other driver functions stop touching
429 hw->adapter_stopped = TRUE;
431 /* Disable the receive unit */
432 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
433 reg_val &= ~(IXGBE_RXCTRL_RXEN);
434 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
435 IXGBE_WRITE_FLUSH(hw);
438 /* Clear interrupt mask to stop from interrupts being generated */
439 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
441 /* Clear any pending interrupts */
442 IXGBE_READ_REG(hw, IXGBE_EICR);
444 /* Disable the transmit unit. Each queue must be disabled. */
445 number_of_queues = hw->mac.max_tx_queues;
446 for (i = 0; i < number_of_queues; i++) {
447 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
448 if (reg_val & IXGBE_TXDCTL_ENABLE) {
449 reg_val &= ~IXGBE_TXDCTL_ENABLE;
450 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
455 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
456 * access and verify no pending requests
458 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS)
459 DEBUGOUT("PCI-E Master disable polling has failed.\n");
461 return IXGBE_SUCCESS;
465 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
466 * @hw: pointer to hardware structure
467 * @index: led number to turn on
469 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
471 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
473 /* To turn on the LED, set mode to ON. */
474 led_reg &= ~IXGBE_LED_MODE_MASK(index);
475 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
476 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
477 IXGBE_WRITE_FLUSH(hw);
479 return IXGBE_SUCCESS;
483 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
484 * @hw: pointer to hardware structure
485 * @index: led number to turn off
487 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
489 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
491 /* To turn off the LED, set mode to OFF. */
492 led_reg &= ~IXGBE_LED_MODE_MASK(index);
493 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
494 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
495 IXGBE_WRITE_FLUSH(hw);
497 return IXGBE_SUCCESS;
501 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
502 * @hw: pointer to hardware structure
504 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
505 * ixgbe_hw struct in order to set up EEPROM access.
507 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
509 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
513 if (eeprom->type == ixgbe_eeprom_uninitialized) {
514 eeprom->type = ixgbe_eeprom_none;
515 /* Set default semaphore delay to 10ms which is a well
517 eeprom->semaphore_delay = 10;
520 * Check for EEPROM present first.
521 * If not present leave as none
523 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
524 if (eec & IXGBE_EEC_PRES) {
525 eeprom->type = ixgbe_eeprom_spi;
528 * SPI EEPROM is assumed here. This code would need to
529 * change if a future EEPROM is not SPI.
531 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
532 IXGBE_EEC_SIZE_SHIFT);
533 eeprom->word_size = 1 << (eeprom_size +
534 IXGBE_EEPROM_WORD_SIZE_SHIFT);
537 if (eec & IXGBE_EEC_ADDR_SIZE)
538 eeprom->address_bits = 16;
540 eeprom->address_bits = 8;
541 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
542 "%d\n", eeprom->type, eeprom->word_size,
543 eeprom->address_bits);
546 return IXGBE_SUCCESS;
550 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
551 * @hw: pointer to hardware structure
552 * @offset: offset within the EEPROM to be written to
553 * @data: 16 bit word to be written to the EEPROM
555 * If ixgbe_eeprom_update_checksum is not called after this function, the
556 * EEPROM will most likely contain an invalid checksum.
558 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
561 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
563 hw->eeprom.ops.init_params(hw);
565 if (offset >= hw->eeprom.word_size) {
566 status = IXGBE_ERR_EEPROM;
570 /* Prepare the EEPROM for writing */
571 status = ixgbe_acquire_eeprom(hw);
573 if (status == IXGBE_SUCCESS) {
574 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
575 ixgbe_release_eeprom(hw);
576 status = IXGBE_ERR_EEPROM;
580 if (status == IXGBE_SUCCESS) {
581 ixgbe_standby_eeprom(hw);
583 /* Send the WRITE ENABLE command (8 bit opcode ) */
584 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
585 IXGBE_EEPROM_OPCODE_BITS);
587 ixgbe_standby_eeprom(hw);
590 * Some SPI eeproms use the 8th address bit embedded in the
593 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
594 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
596 /* Send the Write command (8-bit opcode + addr) */
597 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
598 IXGBE_EEPROM_OPCODE_BITS);
599 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
600 hw->eeprom.address_bits);
603 data = (data >> 8) | (data << 8);
604 ixgbe_shift_out_eeprom_bits(hw, data, 16);
605 ixgbe_standby_eeprom(hw);
607 /* Done with writing - release the EEPROM */
608 ixgbe_release_eeprom(hw);
616 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
617 * @hw: pointer to hardware structure
618 * @offset: offset within the EEPROM to be read
619 * @data: read 16 bit value from EEPROM
621 * Reads 16 bit value from EEPROM through bit-bang method
623 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
628 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
630 hw->eeprom.ops.init_params(hw);
632 if (offset >= hw->eeprom.word_size) {
633 status = IXGBE_ERR_EEPROM;
637 /* Prepare the EEPROM for reading */
638 status = ixgbe_acquire_eeprom(hw);
640 if (status == IXGBE_SUCCESS) {
641 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
642 ixgbe_release_eeprom(hw);
643 status = IXGBE_ERR_EEPROM;
647 if (status == IXGBE_SUCCESS) {
648 ixgbe_standby_eeprom(hw);
651 * Some SPI eeproms use the 8th address bit embedded in the
654 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
655 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
657 /* Send the READ command (opcode + addr) */
658 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
659 IXGBE_EEPROM_OPCODE_BITS);
660 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
661 hw->eeprom.address_bits);
664 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
665 *data = (word_in >> 8) | (word_in << 8);
667 /* End this read operation */
668 ixgbe_release_eeprom(hw);
676 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
677 * @hw: pointer to hardware structure
678 * @offset: offset of word in the EEPROM to read
679 * @data: word read from the EEPROM
681 * Reads a 16 bit word from the EEPROM using the EERD register.
683 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
688 hw->eeprom.ops.init_params(hw);
690 if (offset >= hw->eeprom.word_size) {
691 status = IXGBE_ERR_EEPROM;
695 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
696 IXGBE_EEPROM_READ_REG_START;
698 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
699 status = ixgbe_poll_eeprom_eerd_done(hw);
701 if (status == IXGBE_SUCCESS)
702 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
703 IXGBE_EEPROM_READ_REG_DATA);
705 DEBUGOUT("Eeprom read timed out\n");
712 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
713 * @hw: pointer to hardware structure
715 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
717 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
721 s32 status = IXGBE_ERR_EEPROM;
723 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
724 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
725 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
726 status = IXGBE_SUCCESS;
735 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
736 * @hw: pointer to hardware structure
738 * Prepares EEPROM for access using bit-bang method. This function should
739 * be called before issuing a command to the EEPROM.
741 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
743 s32 status = IXGBE_SUCCESS;
747 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
748 status = IXGBE_ERR_SWFW_SYNC;
750 if (status == IXGBE_SUCCESS) {
751 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
753 /* Request EEPROM Access */
754 eec |= IXGBE_EEC_REQ;
755 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
757 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
758 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
759 if (eec & IXGBE_EEC_GNT)
764 /* Release if grant not acquired */
765 if (!(eec & IXGBE_EEC_GNT)) {
766 eec &= ~IXGBE_EEC_REQ;
767 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
768 DEBUGOUT("Could not acquire EEPROM grant\n");
770 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
771 status = IXGBE_ERR_EEPROM;
775 /* Setup EEPROM for Read/Write */
776 if (status == IXGBE_SUCCESS) {
777 /* Clear CS and SK */
778 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
779 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
780 IXGBE_WRITE_FLUSH(hw);
787 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
788 * @hw: pointer to hardware structure
790 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
792 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
794 s32 status = IXGBE_ERR_EEPROM;
799 /* Set timeout value based on size of EEPROM */
800 timeout = hw->eeprom.word_size + 1;
802 /* Get SMBI software semaphore between device drivers first */
803 for (i = 0; i < timeout; i++) {
805 * If the SMBI bit is 0 when we read it, then the bit will be
806 * set and we have the semaphore
808 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
809 if (!(swsm & IXGBE_SWSM_SMBI)) {
810 status = IXGBE_SUCCESS;
816 /* Now get the semaphore between SW/FW through the SWESMBI bit */
817 if (status == IXGBE_SUCCESS) {
818 for (i = 0; i < timeout; i++) {
819 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
821 /* Set the SW EEPROM semaphore bit to request access */
822 swsm |= IXGBE_SWSM_SWESMBI;
823 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
826 * If we set the bit successfully then we got the
829 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
830 if (swsm & IXGBE_SWSM_SWESMBI)
837 * Release semaphores and return error if SW EEPROM semaphore
838 * was not granted because we don't have access to the EEPROM
841 DEBUGOUT("SWESMBI Software EEPROM semaphore "
843 ixgbe_release_eeprom_semaphore(hw);
844 status = IXGBE_ERR_EEPROM;
847 DEBUGOUT("Software semaphore SMBI between device drivers "
855 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
856 * @hw: pointer to hardware structure
858 * This function clears hardware semaphore bits.
860 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
864 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
866 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
867 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
868 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
869 IXGBE_WRITE_FLUSH(hw);
873 * ixgbe_ready_eeprom - Polls for EEPROM ready
874 * @hw: pointer to hardware structure
876 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
878 s32 status = IXGBE_SUCCESS;
883 * Read "Status Register" repeatedly until the LSB is cleared. The
884 * EEPROM will signal that the command has been completed by clearing
885 * bit 0 of the internal status register. If it's not cleared within
886 * 5 milliseconds, then error out.
888 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
889 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
890 IXGBE_EEPROM_OPCODE_BITS);
891 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
892 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
896 ixgbe_standby_eeprom(hw);
900 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
901 * devices (and only 0-5mSec on 5V devices)
903 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
904 DEBUGOUT("SPI EEPROM Status error\n");
905 status = IXGBE_ERR_EEPROM;
912 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
913 * @hw: pointer to hardware structure
915 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
919 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
921 /* Toggle CS to flush commands */
923 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
924 IXGBE_WRITE_FLUSH(hw);
926 eec &= ~IXGBE_EEC_CS;
927 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
928 IXGBE_WRITE_FLUSH(hw);
933 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
934 * @hw: pointer to hardware structure
935 * @data: data to send to the EEPROM
936 * @count: number of bits to shift out
938 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
945 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
948 * Mask is used to shift "count" bits of "data" out to the EEPROM
949 * one bit at a time. Determine the starting bit based on count
951 mask = 0x01 << (count - 1);
953 for (i = 0; i < count; i++) {
955 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
956 * "1", and then raising and then lowering the clock (the SK
957 * bit controls the clock input to the EEPROM). A "0" is
958 * shifted out to the EEPROM by setting "DI" to "0" and then
959 * raising and then lowering the clock.
964 eec &= ~IXGBE_EEC_DI;
966 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
967 IXGBE_WRITE_FLUSH(hw);
971 ixgbe_raise_eeprom_clk(hw, &eec);
972 ixgbe_lower_eeprom_clk(hw, &eec);
975 * Shift mask to signify next bit of data to shift in to the
981 /* We leave the "DI" bit set to "0" when we leave this routine. */
982 eec &= ~IXGBE_EEC_DI;
983 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
984 IXGBE_WRITE_FLUSH(hw);
988 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
989 * @hw: pointer to hardware structure
991 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
998 * In order to read a register from the EEPROM, we need to shift
999 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1000 * the clock input to the EEPROM (setting the SK bit), and then reading
1001 * the value of the "DO" bit. During this "shifting in" process the
1002 * "DI" bit should always be clear.
1004 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1006 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1008 for (i = 0; i < count; i++) {
1010 ixgbe_raise_eeprom_clk(hw, &eec);
1012 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1014 eec &= ~(IXGBE_EEC_DI);
1015 if (eec & IXGBE_EEC_DO)
1018 ixgbe_lower_eeprom_clk(hw, &eec);
1025 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1026 * @hw: pointer to hardware structure
1027 * @eec: EEC register's current value
1029 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1032 * Raise the clock input to the EEPROM
1033 * (setting the SK bit), then delay
1035 *eec = *eec | IXGBE_EEC_SK;
1036 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1037 IXGBE_WRITE_FLUSH(hw);
1042 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1043 * @hw: pointer to hardware structure
1044 * @eecd: EECD's current value
1046 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1049 * Lower the clock input to the EEPROM (clearing the SK bit), then
1052 *eec = *eec & ~IXGBE_EEC_SK;
1053 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1054 IXGBE_WRITE_FLUSH(hw);
1059 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1060 * @hw: pointer to hardware structure
1062 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1066 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1068 eec |= IXGBE_EEC_CS; /* Pull CS high */
1069 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1071 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1072 IXGBE_WRITE_FLUSH(hw);
1076 /* Stop requesting EEPROM access */
1077 eec &= ~IXGBE_EEC_REQ;
1078 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1080 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1084 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1085 * @hw: pointer to hardware structure
1087 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1096 /* Include 0x0-0x3F in the checksum */
1097 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1098 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1099 DEBUGOUT("EEPROM read failed\n");
1105 /* Include all data from pointers except for the fw pointer */
1106 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1107 hw->eeprom.ops.read(hw, i, &pointer);
1109 /* Make sure the pointer seems valid */
1110 if (pointer != 0xFFFF && pointer != 0) {
1111 hw->eeprom.ops.read(hw, pointer, &length);
1113 if (length != 0xFFFF && length != 0) {
1114 for (j = pointer+1; j <= pointer+length; j++) {
1115 hw->eeprom.ops.read(hw, j, &word);
1122 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1128 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1129 * @hw: pointer to hardware structure
1130 * @checksum_val: calculated checksum
1132 * Performs checksum calculation and validates the EEPROM checksum. If the
1133 * caller does not need checksum_val, the value can be NULL.
1135 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1140 u16 read_checksum = 0;
1143 * Read the first word from the EEPROM. If this times out or fails, do
1144 * not continue or we could be in for a very long wait while every
1147 status = hw->eeprom.ops.read(hw, 0, &checksum);
1149 if (status == IXGBE_SUCCESS) {
1150 checksum = ixgbe_calc_eeprom_checksum(hw);
1152 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1155 * Verify read checksum from EEPROM is the same as
1156 * calculated checksum
1158 if (read_checksum != checksum)
1159 status = IXGBE_ERR_EEPROM_CHECKSUM;
1161 /* If the user cares, return the calculated checksum */
1163 *checksum_val = checksum;
1165 DEBUGOUT("EEPROM read failed\n");
1172 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1173 * @hw: pointer to hardware structure
1175 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1181 * Read the first word from the EEPROM. If this times out or fails, do
1182 * not continue or we could be in for a very long wait while every
1185 status = hw->eeprom.ops.read(hw, 0, &checksum);
1187 if (status == IXGBE_SUCCESS) {
1188 checksum = ixgbe_calc_eeprom_checksum(hw);
1189 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1192 DEBUGOUT("EEPROM read failed\n");
1199 * ixgbe_validate_mac_addr - Validate MAC address
1200 * @mac_addr: pointer to MAC address.
1202 * Tests a MAC address to ensure it is a valid Individual Address
1204 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1206 s32 status = IXGBE_SUCCESS;
1208 /* Make sure it is not a multicast address */
1209 if (IXGBE_IS_MULTICAST(mac_addr)) {
1210 DEBUGOUT("MAC address is multicast\n");
1211 status = IXGBE_ERR_INVALID_MAC_ADDR;
1212 /* Not a broadcast address */
1213 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1214 DEBUGOUT("MAC address is broadcast\n");
1215 status = IXGBE_ERR_INVALID_MAC_ADDR;
1216 /* Reject the zero address */
1217 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1218 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1219 DEBUGOUT("MAC address is all zeros\n");
1220 status = IXGBE_ERR_INVALID_MAC_ADDR;
1226 * ixgbe_set_rar_generic - Set Rx address register
1227 * @hw: pointer to hardware structure
1228 * @index: Receive address register to write
1229 * @addr: Address to put into receive address register
1230 * @vmdq: VMDq "set" or "pool" index
1231 * @enable_addr: set flag that address is active
1233 * Puts an ethernet address into a receive address register.
1235 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1238 u32 rar_low, rar_high;
1239 u32 rar_entries = hw->mac.num_rar_entries;
1241 /* setup VMDq pool selection before this RAR gets enabled */
1242 hw->mac.ops.set_vmdq(hw, index, vmdq);
1244 /* Make sure we are using a valid rar index range */
1245 if (index < rar_entries) {
1247 * HW expects these in little endian so we reverse the byte
1248 * order from network order (big endian) to little endian
1250 rar_low = ((u32)addr[0] |
1251 ((u32)addr[1] << 8) |
1252 ((u32)addr[2] << 16) |
1253 ((u32)addr[3] << 24));
1255 * Some parts put the VMDq setting in the extra RAH bits,
1256 * so save everything except the lower 16 bits that hold part
1257 * of the address and the address valid bit.
1259 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1260 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1261 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1263 if (enable_addr != 0)
1264 rar_high |= IXGBE_RAH_AV;
1266 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1267 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1269 DEBUGOUT1("RAR index %d is out of range.\n", index);
1272 return IXGBE_SUCCESS;
1276 * ixgbe_clear_rar_generic - Remove Rx address register
1277 * @hw: pointer to hardware structure
1278 * @index: Receive address register to write
1280 * Clears an ethernet address from a receive address register.
1282 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1285 u32 rar_entries = hw->mac.num_rar_entries;
1287 /* Make sure we are using a valid rar index range */
1288 if (index < rar_entries) {
1290 * Some parts put the VMDq setting in the extra RAH bits,
1291 * so save everything except the lower 16 bits that hold part
1292 * of the address and the address valid bit.
1294 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1295 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1297 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1298 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1300 DEBUGOUT1("RAR index %d is out of range.\n", index);
1303 /* clear VMDq pool/queue selection for this RAR */
1304 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1306 return IXGBE_SUCCESS;
1310 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1311 * @hw: pointer to hardware structure
1313 * Places the MAC address in receive address register 0 and clears the rest
1314 * of the receive address registers. Clears the multicast table. Assumes
1315 * the receiver is in reset when the routine is called.
1317 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1320 u32 rar_entries = hw->mac.num_rar_entries;
1323 * If the current mac address is valid, assume it is a software override
1324 * to the permanent address.
1325 * Otherwise, use the permanent address from the eeprom.
1327 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1328 IXGBE_ERR_INVALID_MAC_ADDR) {
1329 /* Get the MAC address from the RAR0 for later reference */
1330 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1332 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1333 hw->mac.addr[0], hw->mac.addr[1],
1335 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1336 hw->mac.addr[4], hw->mac.addr[5]);
1338 /* Setup the receive address. */
1339 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
1340 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
1341 hw->mac.addr[0], hw->mac.addr[1],
1343 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1344 hw->mac.addr[4], hw->mac.addr[5]);
1346 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1348 hw->addr_ctrl.overflow_promisc = 0;
1350 hw->addr_ctrl.rar_used_count = 1;
1352 /* Zero out the other receive addresses. */
1353 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
1354 for (i = 1; i < rar_entries; i++) {
1355 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1356 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1360 hw->addr_ctrl.mta_in_use = 0;
1361 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1363 DEBUGOUT(" Clearing MTA\n");
1364 for (i = 0; i < hw->mac.mcft_size; i++)
1365 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1367 ixgbe_init_uta_tables(hw);
1369 return IXGBE_SUCCESS;
1373 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1374 * @hw: pointer to hardware structure
1375 * @addr: new address
1377 * Adds it to unused receive address register or goes into promiscuous mode.
1379 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1381 u32 rar_entries = hw->mac.num_rar_entries;
1384 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1385 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1388 * Place this address in the RAR if there is room,
1389 * else put the controller into promiscuous mode
1391 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1392 rar = hw->addr_ctrl.rar_used_count;
1393 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1394 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
1395 hw->addr_ctrl.rar_used_count++;
1397 hw->addr_ctrl.overflow_promisc++;
1400 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
1404 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1405 * @hw: pointer to hardware structure
1406 * @addr_list: the list of new addresses
1407 * @addr_count: number of addresses
1408 * @next: iterator function to walk the address list
1410 * The given list replaces any existing list. Clears the secondary addrs from
1411 * receive address registers. Uses unused receive address registers for the
1412 * first secondary addresses, and falls back to promiscuous mode as needed.
1414 * Drivers using secondary unicast addresses must set user_set_promisc when
1415 * manually putting the device into promiscuous mode.
1417 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
1418 u32 addr_count, ixgbe_mc_addr_itr next)
1422 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1428 * Clear accounting of old secondary address list,
1429 * don't count RAR[0]
1431 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1432 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1433 hw->addr_ctrl.overflow_promisc = 0;
1435 /* Zero out the other receive addresses */
1436 DEBUGOUT1("Clearing RAR[1-%d]\n", hw->addr_ctrl.rar_used_count);
1437 for (i = 1; i <= hw->addr_ctrl.rar_used_count; i++) {
1438 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1439 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1442 /* Add the new addresses */
1443 for (i = 0; i < addr_count; i++) {
1444 DEBUGOUT(" Adding the secondary addresses:\n");
1445 addr = next(hw, &addr_list, &vmdq);
1446 ixgbe_add_uc_addr(hw, addr, vmdq);
1449 if (hw->addr_ctrl.overflow_promisc) {
1450 /* enable promisc if not already in overflow or set by user */
1451 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1452 DEBUGOUT(" Entering address overflow promisc mode\n");
1453 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1454 fctrl |= IXGBE_FCTRL_UPE;
1455 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1458 /* only disable if set by overflow, not by user */
1459 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1460 DEBUGOUT(" Leaving address overflow promisc mode\n");
1461 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1462 fctrl &= ~IXGBE_FCTRL_UPE;
1463 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1467 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
1468 return IXGBE_SUCCESS;
1472 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1473 * @hw: pointer to hardware structure
1474 * @mc_addr: the multicast address
1476 * Extracts the 12 bits, from a multicast address, to determine which
1477 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1478 * incoming rx multicast addresses, to determine the bit-vector to check in
1479 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1480 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1481 * to mc_filter_type.
1483 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1487 switch (hw->mac.mc_filter_type) {
1488 case 0: /* use bits [47:36] of the address */
1489 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1491 case 1: /* use bits [46:35] of the address */
1492 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1494 case 2: /* use bits [45:34] of the address */
1495 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1497 case 3: /* use bits [43:32] of the address */
1498 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1500 default: /* Invalid mc_filter_type */
1501 DEBUGOUT("MC filter type param set incorrectly\n");
1506 /* vector can only be 12-bits or boundary will be exceeded */
1512 * ixgbe_set_mta - Set bit-vector in multicast table
1513 * @hw: pointer to hardware structure
1514 * @hash_value: Multicast address hash value
1516 * Sets the bit-vector in the multicast table.
1518 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1525 hw->addr_ctrl.mta_in_use++;
1527 vector = ixgbe_mta_vector(hw, mc_addr);
1528 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
1531 * The MTA is a register array of 128 32-bit registers. It is treated
1532 * like an array of 4096 bits. We want to set bit
1533 * BitArray[vector_value]. So we figure out what register the bit is
1534 * in, read it, OR in the new bit, then write back the new value. The
1535 * register is determined by the upper 7 bits of the vector value and
1536 * the bit within that register are determined by the lower 5 bits of
1539 vector_reg = (vector >> 5) & 0x7F;
1540 vector_bit = vector & 0x1F;
1541 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1542 mta_reg |= (1 << vector_bit);
1543 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1547 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1548 * @hw: pointer to hardware structure
1549 * @mc_addr_list: the list of new multicast addresses
1550 * @mc_addr_count: number of addresses
1551 * @next: iterator function to walk the multicast address list
1553 * The given list replaces any existing list. Clears the MC addrs from receive
1554 * address registers and the multicast table. Uses unused receive address
1555 * registers for the first multicast addresses, and hashes the rest into the
1558 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1559 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1565 * Set the new number of MC addresses that we are being requested to
1568 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1569 hw->addr_ctrl.mta_in_use = 0;
1572 DEBUGOUT(" Clearing MTA\n");
1573 for (i = 0; i < hw->mac.mcft_size; i++)
1574 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1576 /* Add the new addresses */
1577 for (i = 0; i < mc_addr_count; i++) {
1578 DEBUGOUT(" Adding the multicast addresses:\n");
1579 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1583 if (hw->addr_ctrl.mta_in_use > 0)
1584 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1585 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1587 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
1588 return IXGBE_SUCCESS;
1592 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1593 * @hw: pointer to hardware structure
1595 * Enables multicast address in RAR and the use of the multicast hash table.
1597 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1599 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1601 if (a->mta_in_use > 0)
1602 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1603 hw->mac.mc_filter_type);
1605 return IXGBE_SUCCESS;
1609 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1610 * @hw: pointer to hardware structure
1612 * Disables multicast address in RAR and the use of the multicast hash table.
1614 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1616 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1618 if (a->mta_in_use > 0)
1619 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1621 return IXGBE_SUCCESS;
1625 * ixgbe_fc_enable_generic - Enable flow control
1626 * @hw: pointer to hardware structure
1627 * @packetbuf_num: packet buffer number (0-7)
1629 * Enable flow control according to the current settings.
1631 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1633 s32 ret_val = IXGBE_SUCCESS;
1634 u32 mflcn_reg, fccfg_reg;
1637 DEBUGFUNC("ixgbe_fc_enable_generic");
1639 /* Negotiate the fc mode to use */
1640 ret_val = ixgbe_fc_autoneg(hw);
1644 /* Disable any previous flow control settings */
1645 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1646 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1648 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1649 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1652 * The possible values of fc.current_mode are:
1653 * 0: Flow control is completely disabled
1654 * 1: Rx flow control is enabled (we can receive pause frames,
1655 * but not send pause frames).
1656 * 2: Tx flow control is enabled (we can send pause frames but
1657 * we do not support receiving pause frames).
1658 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1661 switch (hw->fc.current_mode) {
1663 /* Flow control is disabled by software override or autoneg.
1664 * The code below will actually disable it in the HW.
1667 case ixgbe_fc_rx_pause:
1669 * Rx Flow control is enabled and Tx Flow control is
1670 * disabled by software override. Since there really
1671 * isn't a way to advertise that we are capable of RX
1672 * Pause ONLY, we will advertise that we support both
1673 * symmetric and asymmetric Rx PAUSE. Later, we will
1674 * disable the adapter's ability to send PAUSE frames.
1676 mflcn_reg |= IXGBE_MFLCN_RFCE;
1678 case ixgbe_fc_tx_pause:
1680 * Tx Flow control is enabled, and Rx Flow control is
1681 * disabled by software override.
1683 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1686 /* Flow control (both Rx and Tx) is enabled by SW override. */
1687 mflcn_reg |= IXGBE_MFLCN_RFCE;
1688 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1691 DEBUGOUT("Flow control param set incorrectly\n");
1692 ret_val = -IXGBE_ERR_CONFIG;
1697 /* Set 802.3x based flow control settings. */
1698 mflcn_reg |= IXGBE_MFLCN_DPF;
1699 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1700 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1702 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1703 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1704 if (hw->fc.send_xon) {
1705 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1706 (hw->fc.low_water | IXGBE_FCRTL_XONE));
1708 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1712 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1713 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1716 /* Configure pause time (2 TCs per register) */
1717 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
1718 if ((packetbuf_num & 1) == 0)
1719 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1721 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1722 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1724 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1731 * ixgbe_fc_autoneg - Configure flow control
1732 * @hw: pointer to hardware structure
1734 * Compares our advertised flow control capabilities to those advertised by
1735 * our link partner, and determines the proper flow control mode to use.
1737 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1739 s32 ret_val = IXGBE_SUCCESS;
1740 ixgbe_link_speed speed;
1741 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1744 DEBUGFUNC("ixgbe_fc_autoneg");
1747 * AN should have completed when the cable was plugged in.
1748 * Look for reasons to bail out. Bail out if:
1749 * - FC autoneg is disabled, or if
1750 * - we don't have multispeed fiber, or if
1751 * - we're not running at 1G, or if
1752 * - link is not up, or if
1753 * - link is up but AN did not complete, or if
1754 * - link is up and AN completed but timed out
1756 * Since we're being called from an LSC, link is already know to be up.
1757 * So use link_up_wait_to_complete=FALSE.
1759 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
1760 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1762 if (hw->fc.disable_fc_autoneg ||
1763 !hw->phy.multispeed_fiber ||
1764 (speed != IXGBE_LINK_SPEED_1GB_FULL) ||
1766 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1767 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1768 hw->fc.fc_was_autonegged = FALSE;
1769 hw->fc.current_mode = hw->fc.requested_mode;
1770 DEBUGOUT("Autoneg FC was skipped.\n");
1775 * Read the AN advertisement and LP ability registers and resolve
1776 * local flow control settings accordingly
1778 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1779 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1780 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1781 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1783 * Now we need to check if the user selected Rx ONLY
1784 * of pause frames. In this case, we had to advertise
1785 * FULL flow control because we could not advertise RX
1786 * ONLY. Hence, we must now check to see if we need to
1787 * turn OFF the TRANSMISSION of PAUSE frames.
1789 if (hw->fc.requested_mode == ixgbe_fc_full) {
1790 hw->fc.current_mode = ixgbe_fc_full;
1791 DEBUGOUT("Flow Control = FULL.\n");
1793 hw->fc.current_mode = ixgbe_fc_rx_pause;
1794 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1796 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1797 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1798 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1799 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1800 hw->fc.current_mode = ixgbe_fc_tx_pause;
1801 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1802 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1803 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1804 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1805 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1806 hw->fc.current_mode = ixgbe_fc_rx_pause;
1807 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1809 hw->fc.current_mode = ixgbe_fc_none;
1810 DEBUGOUT("Flow Control = NONE.\n");
1813 /* Record that current_mode is the result of a successful autoneg */
1814 hw->fc.fc_was_autonegged = TRUE;
1821 * ixgbe_setup_fc - Set up flow control
1822 * @hw: pointer to hardware structure
1824 * Called at init time to set up flow control.
1826 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1828 s32 ret_val = IXGBE_SUCCESS;
1832 /* Validate the packetbuf configuration */
1833 if (packetbuf_num < 0 || packetbuf_num > 7) {
1834 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
1835 " 0-7\n", packetbuf_num);
1836 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1841 * Validate the water mark configuration. Zero water marks are invalid
1842 * because it causes the controller to just blast out fc packets.
1844 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1845 DEBUGOUT("Invalid water mark configuration\n");
1846 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1851 * Validate the requested mode. Strict IEEE mode does not allow
1852 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1854 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1855 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
1856 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1861 * 10gig parts do not have a word in the EEPROM to determine the
1862 * default flow control setting, so we explicitly set it to full.
1864 if (hw->fc.requested_mode == ixgbe_fc_default)
1865 hw->fc.requested_mode = ixgbe_fc_full;
1868 * Set up the 1G flow control advertisement registers so the HW will be
1869 * able to do fc autoneg once the cable is plugged in. If we end up
1870 * using 10g instead, this is harmless.
1872 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1875 * The possible values of fc.requested_mode are:
1876 * 0: Flow control is completely disabled
1877 * 1: Rx flow control is enabled (we can receive pause frames,
1878 * but not send pause frames).
1879 * 2: Tx flow control is enabled (we can send pause frames but
1880 * we do not support receiving pause frames).
1881 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1884 switch (hw->fc.requested_mode) {
1886 /* Flow control completely disabled by software override. */
1887 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1889 case ixgbe_fc_rx_pause:
1891 * Rx Flow control is enabled and Tx Flow control is
1892 * disabled by software override. Since there really
1893 * isn't a way to advertise that we are capable of RX
1894 * Pause ONLY, we will advertise that we support both
1895 * symmetric and asymmetric Rx PAUSE. Later, we will
1896 * disable the adapter's ability to send PAUSE frames.
1898 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1900 case ixgbe_fc_tx_pause:
1902 * Tx Flow control is enabled, and Rx Flow control is
1903 * disabled by software override.
1905 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1906 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1909 /* Flow control (both Rx and Tx) is enabled by SW override. */
1910 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1913 DEBUGOUT("Flow control param set incorrectly\n");
1914 ret_val = -IXGBE_ERR_CONFIG;
1919 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1920 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1922 /* Enable and restart autoneg to inform the link partner */
1923 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1925 /* Disable AN timeout */
1926 if (hw->fc.strict_ieee)
1927 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1929 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1930 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
1937 * ixgbe_disable_pcie_master - Disable PCI-express master access
1938 * @hw: pointer to hardware structure
1940 * Disables PCI-Express master access and verifies there are no pending
1941 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1942 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
1943 * is returned signifying master requests disabled.
1945 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1949 u32 number_of_queues;
1950 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1952 /* Disable the receive unit by stopping each queue */
1953 number_of_queues = hw->mac.max_rx_queues;
1954 for (i = 0; i < number_of_queues; i++) {
1955 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1956 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1957 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1958 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1962 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
1963 reg_val |= IXGBE_CTRL_GIO_DIS;
1964 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
1966 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1967 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1968 status = IXGBE_SUCCESS;
1979 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
1980 * @hw: pointer to hardware structure
1981 * @mask: Mask to specify which semaphore to acquire
1983 * Acquires the SWFW semaphore thought the GSSR register for the specified
1984 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1986 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1990 u32 fwmask = mask << 5;
1995 * SW EEPROM semaphore bit is used for access to all
1996 * SW_FW_SYNC/GSSR bits (not just EEPROM)
1998 if (ixgbe_get_eeprom_semaphore(hw))
1999 return -IXGBE_ERR_SWFW_SYNC;
2001 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2002 if (!(gssr & (fwmask | swmask)))
2006 * Firmware currently using resource (fwmask) or other software
2007 * thread currently using resource (swmask)
2009 ixgbe_release_eeprom_semaphore(hw);
2015 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2016 return -IXGBE_ERR_SWFW_SYNC;
2020 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2022 ixgbe_release_eeprom_semaphore(hw);
2023 return IXGBE_SUCCESS;
2027 * ixgbe_release_swfw_sync - Release SWFW semaphore
2028 * @hw: pointer to hardware structure
2029 * @mask: Mask to specify which semaphore to release
2031 * Releases the SWFW semaphore thought the GSSR register for the specified
2032 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2034 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2039 ixgbe_get_eeprom_semaphore(hw);
2041 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2043 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2045 ixgbe_release_eeprom_semaphore(hw);
2047 /* Delay before attempt to obtain semaphore again to allow FW access */
2048 msec_delay(hw->eeprom.semaphore_delay);
2052 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2053 * @hw: pointer to hardware structure
2054 * @regval: register value to write to RXCTRL
2056 * Enables the Rx DMA unit
2058 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2060 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2062 return IXGBE_SUCCESS;
2066 * ixgbe_blink_led_start_generic - Blink LED based on index.
2067 * @hw: pointer to hardware structure
2068 * @index: led number to blink
2070 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2072 ixgbe_link_speed speed = 0;
2074 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2075 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2078 * Link must be up to auto-blink the LEDs;
2079 * Force it if link is down.
2081 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2084 autoc_reg |= IXGBE_AUTOC_FLU;
2085 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2089 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2090 led_reg |= IXGBE_LED_BLINK(index);
2091 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2092 IXGBE_WRITE_FLUSH(hw);
2094 return IXGBE_SUCCESS;
2098 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2099 * @hw: pointer to hardware structure
2100 * @index: led number to stop blinking
2102 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2104 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2105 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2107 autoc_reg &= ~IXGBE_AUTOC_FLU;
2108 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2109 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2111 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2112 led_reg &= ~IXGBE_LED_BLINK(index);
2113 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2114 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2115 IXGBE_WRITE_FLUSH(hw);
2117 return IXGBE_SUCCESS;