1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_common.h"
36 #include "ixgbe_api.h"
38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
52 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
53 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
55 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
56 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
59 * ixgbe_init_ops_generic - Inits function ptrs
60 * @hw: pointer to the hardware structure
62 * Initialize the function pointers.
64 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
66 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
67 struct ixgbe_mac_info *mac = &hw->mac;
68 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
71 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
72 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
74 eeprom->ops.read = &ixgbe_read_eeprom_generic;
76 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
77 eeprom->ops.write = &ixgbe_write_eeprom_generic;
78 eeprom->ops.validate_checksum =
79 &ixgbe_validate_eeprom_checksum_generic;
80 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
83 mac->ops.init_hw = &ixgbe_init_hw_generic;
84 mac->ops.reset_hw = NULL;
85 mac->ops.start_hw = &ixgbe_start_hw_generic;
86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
87 mac->ops.get_media_type = NULL;
88 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
89 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
90 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
91 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_generic;
92 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_generic;
95 mac->ops.led_on = &ixgbe_led_on_generic;
96 mac->ops.led_off = &ixgbe_led_off_generic;
97 mac->ops.blink_led_start = NULL;
98 mac->ops.blink_led_stop = NULL;
100 /* RAR, Multicast, VLAN */
101 mac->ops.set_rar = &ixgbe_set_rar_generic;
102 mac->ops.set_vmdq = NULL;
103 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
104 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
105 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
106 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
107 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
108 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
109 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
112 mac->ops.setup_fc = NULL;
115 mac->ops.get_link_capabilities = NULL;
116 mac->ops.setup_link = NULL;
117 mac->ops.setup_link_speed = NULL;
118 mac->ops.check_link = NULL;
120 return IXGBE_SUCCESS;
124 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
125 * @hw: pointer to hardware structure
127 * Starts the hardware by filling the bus info structure and media type, clears
128 * all on chip counters, initializes receive address registers, multicast
129 * table, VLAN filter table, calls routine to set up link and flow control
130 * settings, and leaves transmit and receive units disabled and uninitialized
132 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
136 /* Set the media type */
137 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
140 hw->mac.ops.get_bus_info(hw);
142 /* Identify the PHY */
143 hw->phy.ops.identify(hw);
146 * Store MAC address from RAR0, clear receive address registers, and
147 * clear the multicast table
149 hw->mac.ops.init_rx_addrs(hw);
151 /* Clear the VLAN filter table */
152 hw->mac.ops.clear_vfta(hw);
155 hw->mac.ops.setup_link(hw);
157 /* Clear statistics registers */
158 hw->mac.ops.clear_hw_cntrs(hw);
160 /* Set No Snoop Disable */
161 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
162 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
163 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
164 IXGBE_WRITE_FLUSH(hw);
166 /* Clear adapter stopped flag */
167 hw->adapter_stopped = FALSE;
169 return IXGBE_SUCCESS;
173 * ixgbe_init_hw_generic - Generic hardware initialization
174 * @hw: pointer to hardware structure
176 * Initialize the hardware by resetting the hardware, filling the bus info
177 * structure and media type, clears all on chip counters, initializes receive
178 * address registers, multicast table, VLAN filter table, calls routine to set
179 * up link and flow control settings, and leaves transmit and receive units
180 * disabled and uninitialized
182 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
184 /* Reset the hardware */
185 hw->mac.ops.reset_hw(hw);
188 hw->mac.ops.start_hw(hw);
190 return IXGBE_SUCCESS;
194 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
195 * @hw: pointer to hardware structure
197 * Clears all hardware statistics counters by reading them from the hardware
198 * Statistics counters are clear on read.
200 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
204 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
205 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
206 IXGBE_READ_REG(hw, IXGBE_ERRBC);
207 IXGBE_READ_REG(hw, IXGBE_MSPDC);
208 for (i = 0; i < 8; i++)
209 IXGBE_READ_REG(hw, IXGBE_MPC(i));
211 IXGBE_READ_REG(hw, IXGBE_MLFC);
212 IXGBE_READ_REG(hw, IXGBE_MRFC);
213 IXGBE_READ_REG(hw, IXGBE_RLEC);
214 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
215 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
216 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
217 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
219 for (i = 0; i < 8; i++) {
220 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
221 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
222 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
223 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
226 IXGBE_READ_REG(hw, IXGBE_PRC64);
227 IXGBE_READ_REG(hw, IXGBE_PRC127);
228 IXGBE_READ_REG(hw, IXGBE_PRC255);
229 IXGBE_READ_REG(hw, IXGBE_PRC511);
230 IXGBE_READ_REG(hw, IXGBE_PRC1023);
231 IXGBE_READ_REG(hw, IXGBE_PRC1522);
232 IXGBE_READ_REG(hw, IXGBE_GPRC);
233 IXGBE_READ_REG(hw, IXGBE_BPRC);
234 IXGBE_READ_REG(hw, IXGBE_MPRC);
235 IXGBE_READ_REG(hw, IXGBE_GPTC);
236 IXGBE_READ_REG(hw, IXGBE_GORCL);
237 IXGBE_READ_REG(hw, IXGBE_GORCH);
238 IXGBE_READ_REG(hw, IXGBE_GOTCL);
239 IXGBE_READ_REG(hw, IXGBE_GOTCH);
240 for (i = 0; i < 8; i++)
241 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
242 IXGBE_READ_REG(hw, IXGBE_RUC);
243 IXGBE_READ_REG(hw, IXGBE_RFC);
244 IXGBE_READ_REG(hw, IXGBE_ROC);
245 IXGBE_READ_REG(hw, IXGBE_RJC);
246 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
247 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
248 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
249 IXGBE_READ_REG(hw, IXGBE_TORL);
250 IXGBE_READ_REG(hw, IXGBE_TORH);
251 IXGBE_READ_REG(hw, IXGBE_TPR);
252 IXGBE_READ_REG(hw, IXGBE_TPT);
253 IXGBE_READ_REG(hw, IXGBE_PTC64);
254 IXGBE_READ_REG(hw, IXGBE_PTC127);
255 IXGBE_READ_REG(hw, IXGBE_PTC255);
256 IXGBE_READ_REG(hw, IXGBE_PTC511);
257 IXGBE_READ_REG(hw, IXGBE_PTC1023);
258 IXGBE_READ_REG(hw, IXGBE_PTC1522);
259 IXGBE_READ_REG(hw, IXGBE_MPTC);
260 IXGBE_READ_REG(hw, IXGBE_BPTC);
261 for (i = 0; i < 16; i++) {
262 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
263 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
264 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
265 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
268 return IXGBE_SUCCESS;
272 * ixgbe_read_pba_num - Reads part number from EEPROM
273 * @hw: pointer to hardware structure
274 * @pba_num: stores the part number from the EEPROM
276 * Reads the part number from the EEPROM.
278 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
283 DEBUGFUNC("ixgbe_read_pba_num_generic");
285 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
287 DEBUGOUT("NVM Read Error\n");
290 *pba_num = (u32)(data << 16);
292 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
294 DEBUGOUT("NVM Read Error\n");
299 return IXGBE_SUCCESS;
303 * ixgbe_get_mac_addr_generic - Generic get MAC address
304 * @hw: pointer to hardware structure
305 * @mac_addr: Adapter MAC address
307 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
308 * A reset of the adapter must be performed prior to calling this function
309 * in order for the MAC address to have been loaded from the EEPROM into RAR0
311 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
317 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
318 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
320 for (i = 0; i < 4; i++)
321 mac_addr[i] = (u8)(rar_low >> (i*8));
323 for (i = 0; i < 2; i++)
324 mac_addr[i+4] = (u8)(rar_high >> (i*8));
326 return IXGBE_SUCCESS;
330 * ixgbe_get_bus_info_generic - Generic set PCI bus info
331 * @hw: pointer to hardware structure
333 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
335 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
339 hw->bus.type = ixgbe_bus_type_pci_express;
341 /* Get the negotiated link width and speed from PCI config space */
342 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
344 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
345 case IXGBE_PCI_LINK_WIDTH_1:
346 hw->bus.width = ixgbe_bus_width_pcie_x1;
348 case IXGBE_PCI_LINK_WIDTH_2:
349 hw->bus.width = ixgbe_bus_width_pcie_x2;
351 case IXGBE_PCI_LINK_WIDTH_4:
352 hw->bus.width = ixgbe_bus_width_pcie_x4;
354 case IXGBE_PCI_LINK_WIDTH_8:
355 hw->bus.width = ixgbe_bus_width_pcie_x8;
358 hw->bus.width = ixgbe_bus_width_unknown;
362 switch (link_status & IXGBE_PCI_LINK_SPEED) {
363 case IXGBE_PCI_LINK_SPEED_2500:
364 hw->bus.speed = ixgbe_bus_speed_2500;
366 case IXGBE_PCI_LINK_SPEED_5000:
367 hw->bus.speed = ixgbe_bus_speed_5000;
370 hw->bus.speed = ixgbe_bus_speed_unknown;
374 return IXGBE_SUCCESS;
378 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
379 * @hw: pointer to hardware structure
381 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
382 * disables transmit and receive units. The adapter_stopped flag is used by
383 * the shared code and drivers to determine if the adapter is in a stopped
384 * state and should not touch the hardware.
386 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
388 u32 number_of_queues;
393 * Set the adapter_stopped flag so other driver functions stop touching
396 hw->adapter_stopped = TRUE;
398 /* Disable the receive unit */
399 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
400 reg_val &= ~(IXGBE_RXCTRL_RXEN);
401 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
402 IXGBE_WRITE_FLUSH(hw);
405 /* Clear interrupt mask to stop from interrupts being generated */
406 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
408 /* Clear any pending interrupts */
409 IXGBE_READ_REG(hw, IXGBE_EICR);
411 /* Disable the transmit unit. Each queue must be disabled. */
412 number_of_queues = hw->mac.max_tx_queues;
413 for (i = 0; i < number_of_queues; i++) {
414 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
415 if (reg_val & IXGBE_TXDCTL_ENABLE) {
416 reg_val &= ~IXGBE_TXDCTL_ENABLE;
417 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
422 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
423 * access and verify no pending requests
425 if (ixgbe_disable_pcie_master(hw) != IXGBE_SUCCESS) {
426 DEBUGOUT("PCI-E Master disable polling has failed.\n");
429 return IXGBE_SUCCESS;
433 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
434 * @hw: pointer to hardware structure
435 * @index: led number to turn on
437 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
439 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
441 /* To turn on the LED, set mode to ON. */
442 led_reg &= ~IXGBE_LED_MODE_MASK(index);
443 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
444 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
445 IXGBE_WRITE_FLUSH(hw);
447 return IXGBE_SUCCESS;
451 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
452 * @hw: pointer to hardware structure
453 * @index: led number to turn off
455 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
457 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
459 /* To turn off the LED, set mode to OFF. */
460 led_reg &= ~IXGBE_LED_MODE_MASK(index);
461 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
462 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
463 IXGBE_WRITE_FLUSH(hw);
465 return IXGBE_SUCCESS;
469 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
470 * @hw: pointer to hardware structure
472 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
473 * ixgbe_hw struct in order to set up EEPROM access.
475 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
477 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
481 if (eeprom->type == ixgbe_eeprom_uninitialized) {
482 eeprom->type = ixgbe_eeprom_none;
485 * Check for EEPROM present first.
486 * If not present leave as none
488 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
489 if (eec & IXGBE_EEC_PRES) {
490 eeprom->type = ixgbe_eeprom_spi;
493 * SPI EEPROM is assumed here. This code would need to
494 * change if a future EEPROM is not SPI.
496 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
497 IXGBE_EEC_SIZE_SHIFT);
498 eeprom->word_size = 1 << (eeprom_size +
499 IXGBE_EEPROM_WORD_SIZE_SHIFT);
502 if (eec & IXGBE_EEC_ADDR_SIZE)
503 eeprom->address_bits = 16;
505 eeprom->address_bits = 8;
506 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
507 "%d\n", eeprom->type, eeprom->word_size,
508 eeprom->address_bits);
511 return IXGBE_SUCCESS;
515 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
516 * @hw: pointer to hardware structure
517 * @offset: offset within the EEPROM to be written to
518 * @data: 16 bit word to be written to the EEPROM
520 * If ixgbe_eeprom_update_checksum is not called after this function, the
521 * EEPROM will most likely contain an invalid checksum.
523 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
526 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
528 hw->eeprom.ops.init_params(hw);
530 if (offset >= hw->eeprom.word_size) {
531 status = IXGBE_ERR_EEPROM;
535 /* Prepare the EEPROM for writing */
536 status = ixgbe_acquire_eeprom(hw);
538 if (status == IXGBE_SUCCESS) {
539 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
540 ixgbe_release_eeprom(hw);
541 status = IXGBE_ERR_EEPROM;
545 if (status == IXGBE_SUCCESS) {
546 ixgbe_standby_eeprom(hw);
548 /* Send the WRITE ENABLE command (8 bit opcode ) */
549 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
550 IXGBE_EEPROM_OPCODE_BITS);
552 ixgbe_standby_eeprom(hw);
555 * Some SPI eeproms use the 8th address bit embedded in the
558 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
559 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
561 /* Send the Write command (8-bit opcode + addr) */
562 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
563 IXGBE_EEPROM_OPCODE_BITS);
564 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
565 hw->eeprom.address_bits);
568 data = (data >> 8) | (data << 8);
569 ixgbe_shift_out_eeprom_bits(hw, data, 16);
570 ixgbe_standby_eeprom(hw);
574 /* Done with writing - release the EEPROM */
575 ixgbe_release_eeprom(hw);
583 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
584 * @hw: pointer to hardware structure
585 * @offset: offset within the EEPROM to be read
586 * @data: read 16 bit value from EEPROM
588 * Reads 16 bit value from EEPROM through bit-bang method
590 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
595 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
597 hw->eeprom.ops.init_params(hw);
599 if (offset >= hw->eeprom.word_size) {
600 status = IXGBE_ERR_EEPROM;
604 /* Prepare the EEPROM for reading */
605 status = ixgbe_acquire_eeprom(hw);
607 if (status == IXGBE_SUCCESS) {
608 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
609 ixgbe_release_eeprom(hw);
610 status = IXGBE_ERR_EEPROM;
614 if (status == IXGBE_SUCCESS) {
615 ixgbe_standby_eeprom(hw);
618 * Some SPI eeproms use the 8th address bit embedded in the
621 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
622 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
624 /* Send the READ command (opcode + addr) */
625 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
626 IXGBE_EEPROM_OPCODE_BITS);
627 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
628 hw->eeprom.address_bits);
631 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
632 *data = (word_in >> 8) | (word_in << 8);
634 /* End this read operation */
635 ixgbe_release_eeprom(hw);
643 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
644 * @hw: pointer to hardware structure
645 * @offset: offset of word in the EEPROM to read
646 * @data: word read from the EEPROM
648 * Reads a 16 bit word from the EEPROM using the EERD register.
650 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
655 hw->eeprom.ops.init_params(hw);
657 if (offset >= hw->eeprom.word_size) {
658 status = IXGBE_ERR_EEPROM;
662 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
663 IXGBE_EEPROM_READ_REG_START;
665 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
666 status = ixgbe_poll_eeprom_eerd_done(hw);
668 if (status == IXGBE_SUCCESS)
669 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
670 IXGBE_EEPROM_READ_REG_DATA);
672 DEBUGOUT("Eeprom read timed out\n");
679 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
680 * @hw: pointer to hardware structure
682 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
684 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
688 s32 status = IXGBE_ERR_EEPROM;
690 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
691 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
692 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
693 status = IXGBE_SUCCESS;
702 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
703 * @hw: pointer to hardware structure
705 * Prepares EEPROM for access using bit-bang method. This function should
706 * be called before issuing a command to the EEPROM.
708 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
710 s32 status = IXGBE_SUCCESS;
714 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
715 status = IXGBE_ERR_SWFW_SYNC;
717 if (status == IXGBE_SUCCESS) {
718 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
720 /* Request EEPROM Access */
721 eec |= IXGBE_EEC_REQ;
722 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
724 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
725 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
726 if (eec & IXGBE_EEC_GNT)
731 /* Release if grant not acquired */
732 if (!(eec & IXGBE_EEC_GNT)) {
733 eec &= ~IXGBE_EEC_REQ;
734 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
735 DEBUGOUT("Could not acquire EEPROM grant\n");
737 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
738 status = IXGBE_ERR_EEPROM;
742 /* Setup EEPROM for Read/Write */
743 if (status == IXGBE_SUCCESS) {
744 /* Clear CS and SK */
745 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
746 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
747 IXGBE_WRITE_FLUSH(hw);
754 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
755 * @hw: pointer to hardware structure
757 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
759 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
761 s32 status = IXGBE_ERR_EEPROM;
766 /* Set timeout value based on size of EEPROM */
767 timeout = hw->eeprom.word_size + 1;
769 /* Get SMBI software semaphore between device drivers first */
770 for (i = 0; i < timeout; i++) {
772 * If the SMBI bit is 0 when we read it, then the bit will be
773 * set and we have the semaphore
775 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
776 if (!(swsm & IXGBE_SWSM_SMBI)) {
777 status = IXGBE_SUCCESS;
783 /* Now get the semaphore between SW/FW through the SWESMBI bit */
784 if (status == IXGBE_SUCCESS) {
785 for (i = 0; i < timeout; i++) {
786 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
788 /* Set the SW EEPROM semaphore bit to request access */
789 swsm |= IXGBE_SWSM_SWESMBI;
790 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
793 * If we set the bit successfully then we got the
796 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
797 if (swsm & IXGBE_SWSM_SWESMBI)
804 * Release semaphores and return error if SW EEPROM semaphore
805 * was not granted because we don't have access to the EEPROM
808 DEBUGOUT("Driver can't access the Eeprom - Semaphore "
810 ixgbe_release_eeprom_semaphore(hw);
811 status = IXGBE_ERR_EEPROM;
819 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
820 * @hw: pointer to hardware structure
822 * This function clears hardware semaphore bits.
824 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
828 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
830 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
831 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
832 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
833 IXGBE_WRITE_FLUSH(hw);
837 * ixgbe_ready_eeprom - Polls for EEPROM ready
838 * @hw: pointer to hardware structure
840 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
842 s32 status = IXGBE_SUCCESS;
847 * Read "Status Register" repeatedly until the LSB is cleared. The
848 * EEPROM will signal that the command has been completed by clearing
849 * bit 0 of the internal status register. If it's not cleared within
850 * 5 milliseconds, then error out.
852 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
853 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
854 IXGBE_EEPROM_OPCODE_BITS);
855 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
856 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
860 ixgbe_standby_eeprom(hw);
864 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
865 * devices (and only 0-5mSec on 5V devices)
867 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
868 DEBUGOUT("SPI EEPROM Status error\n");
869 status = IXGBE_ERR_EEPROM;
876 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
877 * @hw: pointer to hardware structure
879 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
883 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
885 /* Toggle CS to flush commands */
887 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
888 IXGBE_WRITE_FLUSH(hw);
890 eec &= ~IXGBE_EEC_CS;
891 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
892 IXGBE_WRITE_FLUSH(hw);
897 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
898 * @hw: pointer to hardware structure
899 * @data: data to send to the EEPROM
900 * @count: number of bits to shift out
902 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
909 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
912 * Mask is used to shift "count" bits of "data" out to the EEPROM
913 * one bit at a time. Determine the starting bit based on count
915 mask = 0x01 << (count - 1);
917 for (i = 0; i < count; i++) {
919 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
920 * "1", and then raising and then lowering the clock (the SK
921 * bit controls the clock input to the EEPROM). A "0" is
922 * shifted out to the EEPROM by setting "DI" to "0" and then
923 * raising and then lowering the clock.
928 eec &= ~IXGBE_EEC_DI;
930 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
931 IXGBE_WRITE_FLUSH(hw);
935 ixgbe_raise_eeprom_clk(hw, &eec);
936 ixgbe_lower_eeprom_clk(hw, &eec);
939 * Shift mask to signify next bit of data to shift in to the
945 /* We leave the "DI" bit set to "0" when we leave this routine. */
946 eec &= ~IXGBE_EEC_DI;
947 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
948 IXGBE_WRITE_FLUSH(hw);
952 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
953 * @hw: pointer to hardware structure
955 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
962 * In order to read a register from the EEPROM, we need to shift
963 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
964 * the clock input to the EEPROM (setting the SK bit), and then reading
965 * the value of the "DO" bit. During this "shifting in" process the
966 * "DI" bit should always be clear.
968 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
970 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
972 for (i = 0; i < count; i++) {
974 ixgbe_raise_eeprom_clk(hw, &eec);
976 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
978 eec &= ~(IXGBE_EEC_DI);
979 if (eec & IXGBE_EEC_DO)
982 ixgbe_lower_eeprom_clk(hw, &eec);
989 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
990 * @hw: pointer to hardware structure
991 * @eec: EEC register's current value
993 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
996 * Raise the clock input to the EEPROM
997 * (setting the SK bit), then delay
999 *eec = *eec | IXGBE_EEC_SK;
1000 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1001 IXGBE_WRITE_FLUSH(hw);
1006 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1007 * @hw: pointer to hardware structure
1008 * @eecd: EECD's current value
1010 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1013 * Lower the clock input to the EEPROM (clearing the SK bit), then
1016 *eec = *eec & ~IXGBE_EEC_SK;
1017 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1018 IXGBE_WRITE_FLUSH(hw);
1023 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1024 * @hw: pointer to hardware structure
1026 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1030 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1032 eec |= IXGBE_EEC_CS; /* Pull CS high */
1033 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1035 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1036 IXGBE_WRITE_FLUSH(hw);
1040 /* Stop requesting EEPROM access */
1041 eec &= ~IXGBE_EEC_REQ;
1042 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1044 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1048 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1049 * @hw: pointer to hardware structure
1051 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1060 /* Include 0x0-0x3F in the checksum */
1061 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1062 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1063 DEBUGOUT("EEPROM read failed\n");
1069 /* Include all data from pointers except for the fw pointer */
1070 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1071 hw->eeprom.ops.read(hw, i, &pointer);
1073 /* Make sure the pointer seems valid */
1074 if (pointer != 0xFFFF && pointer != 0) {
1075 hw->eeprom.ops.read(hw, pointer, &length);
1077 if (length != 0xFFFF && length != 0) {
1078 for (j = pointer+1; j <= pointer+length; j++) {
1079 hw->eeprom.ops.read(hw, j, &word);
1086 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1092 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1093 * @hw: pointer to hardware structure
1094 * @checksum_val: calculated checksum
1096 * Performs checksum calculation and validates the EEPROM checksum. If the
1097 * caller does not need checksum_val, the value can be NULL.
1099 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1104 u16 read_checksum = 0;
1107 * Read the first word from the EEPROM. If this times out or fails, do
1108 * not continue or we could be in for a very long wait while every
1111 status = hw->eeprom.ops.read(hw, 0, &checksum);
1113 if (status == IXGBE_SUCCESS) {
1114 checksum = ixgbe_calc_eeprom_checksum(hw);
1116 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1119 * Verify read checksum from EEPROM is the same as
1120 * calculated checksum
1122 if (read_checksum != checksum)
1123 status = IXGBE_ERR_EEPROM_CHECKSUM;
1125 /* If the user cares, return the calculated checksum */
1127 *checksum_val = checksum;
1129 DEBUGOUT("EEPROM read failed\n");
1136 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1137 * @hw: pointer to hardware structure
1139 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1145 * Read the first word from the EEPROM. If this times out or fails, do
1146 * not continue or we could be in for a very long wait while every
1149 status = hw->eeprom.ops.read(hw, 0, &checksum);
1151 if (status == IXGBE_SUCCESS) {
1152 checksum = ixgbe_calc_eeprom_checksum(hw);
1153 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1156 DEBUGOUT("EEPROM read failed\n");
1163 * ixgbe_validate_mac_addr - Validate MAC address
1164 * @mac_addr: pointer to MAC address.
1166 * Tests a MAC address to ensure it is a valid Individual Address
1168 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1170 s32 status = IXGBE_SUCCESS;
1172 /* Make sure it is not a multicast address */
1173 if (IXGBE_IS_MULTICAST(mac_addr)) {
1174 DEBUGOUT("MAC address is multicast\n");
1175 status = IXGBE_ERR_INVALID_MAC_ADDR;
1176 /* Not a broadcast address */
1177 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1178 DEBUGOUT("MAC address is broadcast\n");
1179 status = IXGBE_ERR_INVALID_MAC_ADDR;
1180 /* Reject the zero address */
1181 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1182 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1183 DEBUGOUT("MAC address is all zeros\n");
1184 status = IXGBE_ERR_INVALID_MAC_ADDR;
1190 * ixgbe_set_rar_generic - Set Rx address register
1191 * @hw: pointer to hardware structure
1192 * @index: Receive address register to write
1193 * @addr: Address to put into receive address register
1194 * @vmdq: VMDq "set" or "pool" index
1195 * @enable_addr: set flag that address is active
1197 * Puts an ethernet address into a receive address register.
1199 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1202 u32 rar_low, rar_high;
1203 u32 rar_entries = hw->mac.num_rar_entries;
1205 /* setup VMDq pool selection before this RAR gets enabled */
1206 hw->mac.ops.set_vmdq(hw, index, vmdq);
1208 /* Make sure we are using a valid rar index range */
1209 if (index < rar_entries) {
1211 * HW expects these in little endian so we reverse the byte
1212 * order from network order (big endian) to little endian
1214 rar_low = ((u32)addr[0] |
1215 ((u32)addr[1] << 8) |
1216 ((u32)addr[2] << 16) |
1217 ((u32)addr[3] << 24));
1219 * Some parts put the VMDq setting in the extra RAH bits,
1220 * so save everything except the lower 16 bits that hold part
1221 * of the address and the address valid bit.
1223 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1224 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1225 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1227 if (enable_addr != 0)
1228 rar_high |= IXGBE_RAH_AV;
1230 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1231 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1233 DEBUGOUT("Current RAR index is out of range.");
1236 return IXGBE_SUCCESS;
1240 * ixgbe_enable_rar - Enable Rx address register
1241 * @hw: pointer to hardware structure
1242 * @index: index into the RAR table
1244 * Enables the select receive address register.
1246 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1250 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1251 rar_high |= IXGBE_RAH_AV;
1252 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1256 * ixgbe_disable_rar - Disable Rx address register
1257 * @hw: pointer to hardware structure
1258 * @index: index into the RAR table
1260 * Disables the select receive address register.
1262 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1266 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1267 rar_high &= (~IXGBE_RAH_AV);
1268 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1272 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1273 * @hw: pointer to hardware structure
1275 * Places the MAC address in receive address register 0 and clears the rest
1276 * of the receive address registers. Clears the multicast table. Assumes
1277 * the receiver is in reset when the routine is called.
1279 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1282 u32 rar_entries = hw->mac.num_rar_entries;
1285 * If the current mac address is valid, assume it is a software override
1286 * to the permanent address.
1287 * Otherwise, use the permanent address from the eeprom.
1289 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1290 IXGBE_ERR_INVALID_MAC_ADDR) {
1291 /* Get the MAC address from the RAR0 for later reference */
1292 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1294 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1295 hw->mac.addr[0], hw->mac.addr[1],
1297 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1298 hw->mac.addr[4], hw->mac.addr[5]);
1300 /* Setup the receive address. */
1301 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
1302 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
1303 hw->mac.addr[0], hw->mac.addr[1],
1305 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1306 hw->mac.addr[4], hw->mac.addr[5]);
1308 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1310 hw->addr_ctrl.overflow_promisc = 0;
1312 hw->addr_ctrl.rar_used_count = 1;
1314 /* Zero out the other receive addresses. */
1315 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
1316 for (i = 1; i < rar_entries; i++) {
1317 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1318 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1322 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1323 hw->addr_ctrl.mta_in_use = 0;
1324 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1326 DEBUGOUT(" Clearing MTA\n");
1327 for (i = 0; i < hw->mac.mcft_size; i++)
1328 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1330 return IXGBE_SUCCESS;
1334 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1335 * @hw: pointer to hardware structure
1336 * @addr: new address
1338 * Adds it to unused receive address register or goes into promiscuous mode.
1340 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1342 u32 rar_entries = hw->mac.num_rar_entries;
1345 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1346 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1349 * Place this address in the RAR if there is room,
1350 * else put the controller into promiscuous mode
1352 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1353 rar = hw->addr_ctrl.rar_used_count -
1354 hw->addr_ctrl.mc_addr_in_rar_count;
1355 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1356 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
1357 hw->addr_ctrl.rar_used_count++;
1359 hw->addr_ctrl.overflow_promisc++;
1362 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
1366 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1367 * @hw: pointer to hardware structure
1368 * @addr_list: the list of new addresses
1369 * @addr_count: number of addresses
1370 * @next: iterator function to walk the address list
1372 * The given list replaces any existing list. Clears the secondary addrs from
1373 * receive address registers. Uses unused receive address registers for the
1374 * first secondary addresses, and falls back to promiscuous mode as needed.
1376 * Drivers using secondary unicast addresses must set user_set_promisc when
1377 * manually putting the device into promiscuous mode.
1379 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
1380 u32 addr_count, ixgbe_mc_addr_itr next)
1384 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1390 * Clear accounting of old secondary address list,
1391 * don't count RAR[0]
1393 uc_addr_in_use = hw->addr_ctrl.rar_used_count -
1394 hw->addr_ctrl.mc_addr_in_rar_count - 1;
1395 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1396 hw->addr_ctrl.overflow_promisc = 0;
1398 /* Zero out the other receive addresses */
1399 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use);
1400 for (i = 1; i <= uc_addr_in_use; i++) {
1401 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1402 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1405 /* Add the new addresses */
1406 for (i = 0; i < addr_count; i++) {
1407 DEBUGOUT(" Adding the secondary addresses:\n");
1408 addr = next(hw, &addr_list, &vmdq);
1409 ixgbe_add_uc_addr(hw, addr, vmdq);
1412 if (hw->addr_ctrl.overflow_promisc) {
1413 /* enable promisc if not already in overflow or set by user */
1414 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1415 DEBUGOUT( " Entering address overflow promisc mode\n");
1416 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1417 fctrl |= IXGBE_FCTRL_UPE;
1418 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1421 /* only disable if set by overflow, not by user */
1422 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1423 DEBUGOUT(" Leaving address overflow promisc mode\n");
1424 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1425 fctrl &= ~IXGBE_FCTRL_UPE;
1426 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1430 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
1431 return IXGBE_SUCCESS;
1435 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1436 * @hw: pointer to hardware structure
1437 * @mc_addr: the multicast address
1439 * Extracts the 12 bits, from a multicast address, to determine which
1440 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1441 * incoming rx multicast addresses, to determine the bit-vector to check in
1442 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1443 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1444 * to mc_filter_type.
1446 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1450 switch (hw->mac.mc_filter_type) {
1451 case 0: /* use bits [47:36] of the address */
1452 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1454 case 1: /* use bits [46:35] of the address */
1455 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1457 case 2: /* use bits [45:34] of the address */
1458 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1460 case 3: /* use bits [43:32] of the address */
1461 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1463 default: /* Invalid mc_filter_type */
1464 DEBUGOUT("MC filter type param set incorrectly\n");
1469 /* vector can only be 12-bits or boundary will be exceeded */
1475 * ixgbe_set_mta - Set bit-vector in multicast table
1476 * @hw: pointer to hardware structure
1477 * @hash_value: Multicast address hash value
1479 * Sets the bit-vector in the multicast table.
1481 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1488 hw->addr_ctrl.mta_in_use++;
1490 vector = ixgbe_mta_vector(hw, mc_addr);
1491 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
1494 * The MTA is a register array of 128 32-bit registers. It is treated
1495 * like an array of 4096 bits. We want to set bit
1496 * BitArray[vector_value]. So we figure out what register the bit is
1497 * in, read it, OR in the new bit, then write back the new value. The
1498 * register is determined by the upper 7 bits of the vector value and
1499 * the bit within that register are determined by the lower 5 bits of
1502 vector_reg = (vector >> 5) & 0x7F;
1503 vector_bit = vector & 0x1F;
1504 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1505 mta_reg |= (1 << vector_bit);
1506 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1510 * ixgbe_add_mc_addr - Adds a multicast address.
1511 * @hw: pointer to hardware structure
1512 * @mc_addr: new multicast address
1514 * Adds it to unused receive address register or to the multicast table.
1516 void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
1518 u32 rar_entries = hw->mac.num_rar_entries;
1521 DEBUGOUT6(" MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
1522 mc_addr[0], mc_addr[1], mc_addr[2],
1523 mc_addr[3], mc_addr[4], mc_addr[5]);
1526 * Place this multicast address in the RAR if there is room,
1527 * else put it in the MTA
1529 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1530 /* use RAR from the end up for multicast */
1531 rar = rar_entries - hw->addr_ctrl.mc_addr_in_rar_count - 1;
1532 hw->mac.ops.set_rar(hw, rar, mc_addr, 0, IXGBE_RAH_AV);
1533 DEBUGOUT1("Added a multicast address to RAR[%d]\n", rar);
1534 hw->addr_ctrl.rar_used_count++;
1535 hw->addr_ctrl.mc_addr_in_rar_count++;
1537 ixgbe_set_mta(hw, mc_addr);
1540 DEBUGOUT("ixgbe_add_mc_addr Complete\n");
1544 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1545 * @hw: pointer to hardware structure
1546 * @mc_addr_list: the list of new multicast addresses
1547 * @mc_addr_count: number of addresses
1548 * @next: iterator function to walk the multicast address list
1550 * The given list replaces any existing list. Clears the MC addrs from receive
1551 * address registers and the multicast table. Uses unused receive address
1552 * registers for the first multicast addresses, and hashes the rest into the
1555 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1556 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1559 u32 rar_entries = hw->mac.num_rar_entries;
1563 * Set the new number of MC addresses that we are being requested to
1566 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1567 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count;
1568 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1569 hw->addr_ctrl.mta_in_use = 0;
1571 /* Zero out the other receive addresses. */
1572 DEBUGOUT2("Clearing RAR[%d-%d]\n", hw->addr_ctrl.rar_used_count,
1574 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
1575 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1576 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1580 DEBUGOUT(" Clearing MTA\n");
1581 for (i = 0; i < hw->mac.mcft_size; i++)
1582 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1584 /* Add the new addresses */
1585 for (i = 0; i < mc_addr_count; i++) {
1586 DEBUGOUT(" Adding the multicast addresses:\n");
1587 ixgbe_add_mc_addr(hw, next(hw, &mc_addr_list, &vmdq));
1591 if (hw->addr_ctrl.mta_in_use > 0)
1592 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1593 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1595 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
1596 return IXGBE_SUCCESS;
1600 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1601 * @hw: pointer to hardware structure
1603 * Enables multicast address in RAR and the use of the multicast hash table.
1605 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1608 u32 rar_entries = hw->mac.num_rar_entries;
1609 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1611 if (a->mc_addr_in_rar_count > 0)
1612 for (i = (rar_entries - a->mc_addr_in_rar_count);
1613 i < rar_entries; i++)
1614 ixgbe_enable_rar(hw, i);
1616 if (a->mta_in_use > 0)
1617 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1618 hw->mac.mc_filter_type);
1620 return IXGBE_SUCCESS;
1624 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1625 * @hw: pointer to hardware structure
1627 * Disables multicast address in RAR and the use of the multicast hash table.
1629 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1632 u32 rar_entries = hw->mac.num_rar_entries;
1633 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1635 if (a->mc_addr_in_rar_count > 0)
1636 for (i = (rar_entries - a->mc_addr_in_rar_count);
1637 i < rar_entries; i++)
1638 ixgbe_disable_rar(hw, i);
1640 if (a->mta_in_use > 0)
1641 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1643 return IXGBE_SUCCESS;
1647 * ixgbe_clear_vfta_generic - Clear VLAN filter table
1648 * @hw: pointer to hardware structure
1650 * Clears the VLAN filer table, and the VMDq index associated with the filter
1652 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
1657 for (offset = 0; offset < hw->mac.vft_size; offset++)
1658 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1660 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1661 for (offset = 0; offset < hw->mac.vft_size; offset++)
1662 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1665 return IXGBE_SUCCESS;
1669 * ixgbe_set_vfta_generic - Set VLAN filter table
1670 * @hw: pointer to hardware structure
1671 * @vlan: VLAN id to write to VLAN filter
1672 * @vind: VMDq output index that maps queue to VLAN id in VFTA
1673 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1675 * Turn on/off specified VLAN in the VLAN filter table.
1677 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1685 /* Determine 32-bit word position in array */
1686 VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */
1688 /* Determine the location of the (VMD) queue index */
1689 VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1690 BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1692 /* Set the nibble for VMD queue index */
1693 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex));
1694 VftaReg &= (~(0x0F << BitOffset));
1695 VftaReg |= (vind << BitOffset);
1696 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg);
1698 /* Determine the location of the bit for this VLAN id */
1699 BitOffset = vlan & 0x1F; /* lower five bits */
1701 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex));
1703 /* Turn on this VLAN id */
1704 VftaReg |= (1 << BitOffset);
1706 /* Turn off this VLAN id */
1707 VftaReg &= ~(1 << BitOffset);
1708 IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg);
1710 return IXGBE_SUCCESS;
1714 * ixgbe_disable_pcie_master - Disable PCI-express master access
1715 * @hw: pointer to hardware structure
1717 * Disables PCI-Express master access and verifies there are no pending
1718 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1719 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
1720 * is returned signifying master requests disabled.
1722 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1726 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1728 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1729 ctrl |= IXGBE_CTRL_GIO_DIS;
1730 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1732 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1733 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1734 status = IXGBE_SUCCESS;
1745 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
1746 * @hw: pointer to hardware structure
1747 * @mask: Mask to specify which semaphore to acquire
1749 * Acquires the SWFW semaphore thought the GSSR register for the specified
1750 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1752 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1756 u32 fwmask = mask << 5;
1760 if (ixgbe_get_eeprom_semaphore(hw))
1761 return -IXGBE_ERR_SWFW_SYNC;
1763 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1764 if (!(gssr & (fwmask | swmask)))
1768 * Firmware currently using resource (fwmask) or other software
1769 * thread currently using resource (swmask)
1771 ixgbe_release_eeprom_semaphore(hw);
1777 DEBUGOUT("Driver can't access resource, GSSR timeout.\n");
1778 return -IXGBE_ERR_SWFW_SYNC;
1782 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1784 ixgbe_release_eeprom_semaphore(hw);
1785 return IXGBE_SUCCESS;
1789 * ixgbe_release_swfw_sync - Release SWFW semaphore
1790 * @hw: pointer to hardware structure
1791 * @mask: Mask to specify which semaphore to release
1793 * Releases the SWFW semaphore thought the GSSR register for the specified
1794 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1796 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1801 ixgbe_get_eeprom_semaphore(hw);
1803 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1805 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1807 ixgbe_release_eeprom_semaphore(hw);
1811 * ixgbe_read_analog_reg8_generic - Reads 8 bit Atlas analog register
1812 * @hw: pointer to hardware structure
1813 * @reg: analog register to read
1816 * Performs read operation to Atlas analog register specified.
1818 s32 ixgbe_read_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 *val)
1822 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1823 IXGBE_WRITE_FLUSH(hw);
1825 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1826 *val = (u8)atlas_ctl;
1828 return IXGBE_SUCCESS;
1832 * ixgbe_write_analog_reg8_generic - Writes 8 bit Atlas analog register
1833 * @hw: pointer to hardware structure
1834 * @reg: atlas register to write
1835 * @val: value to write
1837 * Performs write operation to Atlas analog register specified.
1839 s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val)
1843 atlas_ctl = (reg << 8) | val;
1844 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1845 IXGBE_WRITE_FLUSH(hw);
1848 return IXGBE_SUCCESS;