1 /******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_api.h"
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
51 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
54 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
62 * ixgbe_init_ops_generic - Inits function ptrs
63 * @hw: pointer to the hardware structure
65 * Initialize the function pointers.
67 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
69 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
70 struct ixgbe_mac_info *mac = &hw->mac;
71 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
73 DEBUGFUNC("ixgbe_init_ops_generic");
76 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
77 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
78 if (eec & IXGBE_EEC_PRES) {
79 eeprom->ops.read = &ixgbe_read_eerd_generic;
80 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
82 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
83 eeprom->ops.read_buffer =
84 &ixgbe_read_eeprom_buffer_bit_bang_generic;
86 eeprom->ops.write = &ixgbe_write_eeprom_generic;
87 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.validate_checksum =
89 &ixgbe_validate_eeprom_checksum_generic;
90 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
91 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
94 mac->ops.init_hw = &ixgbe_init_hw_generic;
95 mac->ops.reset_hw = NULL;
96 mac->ops.start_hw = &ixgbe_start_hw_generic;
97 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
98 mac->ops.get_media_type = NULL;
99 mac->ops.get_supported_physical_layer = NULL;
100 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
101 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
102 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
103 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
104 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
105 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
106 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
109 mac->ops.led_on = &ixgbe_led_on_generic;
110 mac->ops.led_off = &ixgbe_led_off_generic;
111 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
112 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
114 /* RAR, Multicast, VLAN */
115 mac->ops.set_rar = &ixgbe_set_rar_generic;
116 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
117 mac->ops.insert_mac_addr = NULL;
118 mac->ops.set_vmdq = NULL;
119 mac->ops.clear_vmdq = NULL;
120 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
121 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
122 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
123 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
124 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
125 mac->ops.clear_vfta = NULL;
126 mac->ops.set_vfta = NULL;
127 mac->ops.set_vlvf = NULL;
128 mac->ops.init_uta_tables = NULL;
131 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
134 mac->ops.get_link_capabilities = NULL;
135 mac->ops.setup_link = NULL;
136 mac->ops.check_link = NULL;
138 return IXGBE_SUCCESS;
142 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
144 * @hw: pointer to hardware structure
146 * There are several phys that do not support autoneg flow control. This
147 * function check the device id to see if the associated phy supports
148 * autoneg flow control.
150 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
153 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
155 switch (hw->device_id) {
156 case IXGBE_DEV_ID_X540T:
157 case IXGBE_DEV_ID_X540T1:
158 return IXGBE_SUCCESS;
159 case IXGBE_DEV_ID_82599_T3_LOM:
160 return IXGBE_SUCCESS;
162 return IXGBE_ERR_FC_NOT_SUPPORTED;
167 * ixgbe_setup_fc - Set up flow control
168 * @hw: pointer to hardware structure
170 * Called at init time to set up flow control.
172 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
174 s32 ret_val = IXGBE_SUCCESS;
175 u32 reg = 0, reg_bp = 0;
178 DEBUGFUNC("ixgbe_setup_fc");
181 * Validate the requested mode. Strict IEEE mode does not allow
182 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
184 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
185 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
186 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
191 * 10gig parts do not have a word in the EEPROM to determine the
192 * default flow control setting, so we explicitly set it to full.
194 if (hw->fc.requested_mode == ixgbe_fc_default)
195 hw->fc.requested_mode = ixgbe_fc_full;
198 * Set up the 1G and 10G flow control advertisement registers so the
199 * HW will be able to do fc autoneg once the cable is plugged in. If
200 * we link at 10G, the 1G advertisement is harmless and vice versa.
202 switch (hw->phy.media_type) {
203 case ixgbe_media_type_fiber:
204 case ixgbe_media_type_backplane:
205 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
206 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
208 case ixgbe_media_type_copper:
209 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
210 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
217 * The possible values of fc.requested_mode are:
218 * 0: Flow control is completely disabled
219 * 1: Rx flow control is enabled (we can receive pause frames,
220 * but not send pause frames).
221 * 2: Tx flow control is enabled (we can send pause frames but
222 * we do not support receiving pause frames).
223 * 3: Both Rx and Tx flow control (symmetric) are enabled.
226 switch (hw->fc.requested_mode) {
228 /* Flow control completely disabled by software override. */
229 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
230 if (hw->phy.media_type == ixgbe_media_type_backplane)
231 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
232 IXGBE_AUTOC_ASM_PAUSE);
233 else if (hw->phy.media_type == ixgbe_media_type_copper)
234 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
236 case ixgbe_fc_tx_pause:
238 * Tx Flow control is enabled, and Rx Flow control is
239 * disabled by software override.
241 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
242 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
243 if (hw->phy.media_type == ixgbe_media_type_backplane) {
244 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
245 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
246 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
247 reg_cu |= IXGBE_TAF_ASM_PAUSE;
248 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
251 case ixgbe_fc_rx_pause:
253 * Rx Flow control is enabled and Tx Flow control is
254 * disabled by software override. Since there really
255 * isn't a way to advertise that we are capable of RX
256 * Pause ONLY, we will advertise that we support both
257 * symmetric and asymmetric Rx PAUSE, as such we fall
258 * through to the fc_full statement. Later, we will
259 * disable the adapter's ability to send PAUSE frames.
262 /* Flow control (both Rx and Tx) is enabled by SW override. */
263 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
264 if (hw->phy.media_type == ixgbe_media_type_backplane)
265 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
266 IXGBE_AUTOC_ASM_PAUSE;
267 else if (hw->phy.media_type == ixgbe_media_type_copper)
268 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
271 DEBUGOUT("Flow control param set incorrectly\n");
272 ret_val = IXGBE_ERR_CONFIG;
277 if (hw->mac.type != ixgbe_mac_X540) {
279 * Enable auto-negotiation between the MAC & PHY;
280 * the MAC will advertise clause 37 flow control.
282 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
283 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
285 /* Disable AN timeout */
286 if (hw->fc.strict_ieee)
287 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
289 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
290 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
294 * AUTOC restart handles negotiation of 1G and 10G on backplane
295 * and copper. There is no need to set the PCS1GCTL register.
298 if (hw->phy.media_type == ixgbe_media_type_backplane) {
299 reg_bp |= IXGBE_AUTOC_AN_RESTART;
300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
301 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
302 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
303 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
304 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
307 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
313 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
314 * @hw: pointer to hardware structure
316 * Starts the hardware by filling the bus info structure and media type, clears
317 * all on chip counters, initializes receive address registers, multicast
318 * table, VLAN filter table, calls routine to set up link and flow control
319 * settings, and leaves transmit and receive units disabled and uninitialized
321 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
326 DEBUGFUNC("ixgbe_start_hw_generic");
328 /* Set the media type */
329 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
331 /* PHY ops initialization must be done in reset_hw() */
333 /* Clear the VLAN filter table */
334 hw->mac.ops.clear_vfta(hw);
336 /* Clear statistics registers */
337 hw->mac.ops.clear_hw_cntrs(hw);
339 /* Set No Snoop Disable */
340 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
341 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
342 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
343 IXGBE_WRITE_FLUSH(hw);
345 /* Setup flow control */
346 ret_val = ixgbe_setup_fc(hw);
347 if (ret_val != IXGBE_SUCCESS)
350 /* Clear adapter stopped flag */
351 hw->adapter_stopped = FALSE;
358 * ixgbe_start_hw_gen2 - Init sequence for common device family
359 * @hw: pointer to hw structure
361 * Performs the init sequence common to the second generation
363 * Devices in the second generation:
367 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
372 /* Clear the rate limiters */
373 for (i = 0; i < hw->mac.max_tx_queues; i++) {
374 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
375 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
377 IXGBE_WRITE_FLUSH(hw);
379 /* Disable relaxed ordering */
380 for (i = 0; i < hw->mac.max_tx_queues; i++) {
381 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
382 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
383 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
386 for (i = 0; i < hw->mac.max_rx_queues; i++) {
387 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
388 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
389 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
390 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
393 return IXGBE_SUCCESS;
397 * ixgbe_init_hw_generic - Generic hardware initialization
398 * @hw: pointer to hardware structure
400 * Initialize the hardware by resetting the hardware, filling the bus info
401 * structure and media type, clears all on chip counters, initializes receive
402 * address registers, multicast table, VLAN filter table, calls routine to set
403 * up link and flow control settings, and leaves transmit and receive units
404 * disabled and uninitialized
406 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
410 DEBUGFUNC("ixgbe_init_hw_generic");
412 /* Reset the hardware */
413 status = hw->mac.ops.reset_hw(hw);
415 if (status == IXGBE_SUCCESS) {
417 status = hw->mac.ops.start_hw(hw);
424 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
425 * @hw: pointer to hardware structure
427 * Clears all hardware statistics counters by reading them from the hardware
428 * Statistics counters are clear on read.
430 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
434 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
436 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
437 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
438 IXGBE_READ_REG(hw, IXGBE_ERRBC);
439 IXGBE_READ_REG(hw, IXGBE_MSPDC);
440 for (i = 0; i < 8; i++)
441 IXGBE_READ_REG(hw, IXGBE_MPC(i));
443 IXGBE_READ_REG(hw, IXGBE_MLFC);
444 IXGBE_READ_REG(hw, IXGBE_MRFC);
445 IXGBE_READ_REG(hw, IXGBE_RLEC);
446 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
447 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
448 if (hw->mac.type >= ixgbe_mac_82599EB) {
449 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
450 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
452 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
453 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
456 for (i = 0; i < 8; i++) {
457 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
458 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
459 if (hw->mac.type >= ixgbe_mac_82599EB) {
460 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
461 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
463 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
464 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
467 if (hw->mac.type >= ixgbe_mac_82599EB)
468 for (i = 0; i < 8; i++)
469 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
470 IXGBE_READ_REG(hw, IXGBE_PRC64);
471 IXGBE_READ_REG(hw, IXGBE_PRC127);
472 IXGBE_READ_REG(hw, IXGBE_PRC255);
473 IXGBE_READ_REG(hw, IXGBE_PRC511);
474 IXGBE_READ_REG(hw, IXGBE_PRC1023);
475 IXGBE_READ_REG(hw, IXGBE_PRC1522);
476 IXGBE_READ_REG(hw, IXGBE_GPRC);
477 IXGBE_READ_REG(hw, IXGBE_BPRC);
478 IXGBE_READ_REG(hw, IXGBE_MPRC);
479 IXGBE_READ_REG(hw, IXGBE_GPTC);
480 IXGBE_READ_REG(hw, IXGBE_GORCL);
481 IXGBE_READ_REG(hw, IXGBE_GORCH);
482 IXGBE_READ_REG(hw, IXGBE_GOTCL);
483 IXGBE_READ_REG(hw, IXGBE_GOTCH);
484 if (hw->mac.type == ixgbe_mac_82598EB)
485 for (i = 0; i < 8; i++)
486 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
487 IXGBE_READ_REG(hw, IXGBE_RUC);
488 IXGBE_READ_REG(hw, IXGBE_RFC);
489 IXGBE_READ_REG(hw, IXGBE_ROC);
490 IXGBE_READ_REG(hw, IXGBE_RJC);
491 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
492 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
493 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
494 IXGBE_READ_REG(hw, IXGBE_TORL);
495 IXGBE_READ_REG(hw, IXGBE_TORH);
496 IXGBE_READ_REG(hw, IXGBE_TPR);
497 IXGBE_READ_REG(hw, IXGBE_TPT);
498 IXGBE_READ_REG(hw, IXGBE_PTC64);
499 IXGBE_READ_REG(hw, IXGBE_PTC127);
500 IXGBE_READ_REG(hw, IXGBE_PTC255);
501 IXGBE_READ_REG(hw, IXGBE_PTC511);
502 IXGBE_READ_REG(hw, IXGBE_PTC1023);
503 IXGBE_READ_REG(hw, IXGBE_PTC1522);
504 IXGBE_READ_REG(hw, IXGBE_MPTC);
505 IXGBE_READ_REG(hw, IXGBE_BPTC);
506 for (i = 0; i < 16; i++) {
507 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
508 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
509 if (hw->mac.type >= ixgbe_mac_82599EB) {
510 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
511 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
512 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
513 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
514 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
516 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
517 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
521 if (hw->mac.type == ixgbe_mac_X540) {
523 ixgbe_identify_phy(hw);
524 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
525 IXGBE_MDIO_PCS_DEV_TYPE, &i);
526 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
527 IXGBE_MDIO_PCS_DEV_TYPE, &i);
528 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
529 IXGBE_MDIO_PCS_DEV_TYPE, &i);
530 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
531 IXGBE_MDIO_PCS_DEV_TYPE, &i);
534 return IXGBE_SUCCESS;
538 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
539 * @hw: pointer to hardware structure
540 * @pba_num: stores the part number string from the EEPROM
541 * @pba_num_size: part number string buffer length
543 * Reads the part number string from the EEPROM.
545 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
554 DEBUGFUNC("ixgbe_read_pba_string_generic");
556 if (pba_num == NULL) {
557 DEBUGOUT("PBA string buffer was null\n");
558 return IXGBE_ERR_INVALID_ARGUMENT;
561 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
563 DEBUGOUT("NVM Read Error\n");
567 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
569 DEBUGOUT("NVM Read Error\n");
574 * if data is not ptr guard the PBA must be in legacy format which
575 * means pba_ptr is actually our second data word for the PBA number
576 * and we can decode it into an ascii string
578 if (data != IXGBE_PBANUM_PTR_GUARD) {
579 DEBUGOUT("NVM PBA number is not stored as string\n");
581 /* we will need 11 characters to store the PBA */
582 if (pba_num_size < 11) {
583 DEBUGOUT("PBA string buffer too small\n");
584 return IXGBE_ERR_NO_SPACE;
587 /* extract hex string from data and pba_ptr */
588 pba_num[0] = (data >> 12) & 0xF;
589 pba_num[1] = (data >> 8) & 0xF;
590 pba_num[2] = (data >> 4) & 0xF;
591 pba_num[3] = data & 0xF;
592 pba_num[4] = (pba_ptr >> 12) & 0xF;
593 pba_num[5] = (pba_ptr >> 8) & 0xF;
596 pba_num[8] = (pba_ptr >> 4) & 0xF;
597 pba_num[9] = pba_ptr & 0xF;
599 /* put a null character on the end of our string */
602 /* switch all the data but the '-' to hex char */
603 for (offset = 0; offset < 10; offset++) {
604 if (pba_num[offset] < 0xA)
605 pba_num[offset] += '0';
606 else if (pba_num[offset] < 0x10)
607 pba_num[offset] += 'A' - 0xA;
610 return IXGBE_SUCCESS;
613 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
615 DEBUGOUT("NVM Read Error\n");
619 if (length == 0xFFFF || length == 0) {
620 DEBUGOUT("NVM PBA number section invalid length\n");
621 return IXGBE_ERR_PBA_SECTION;
624 /* check if pba_num buffer is big enough */
625 if (pba_num_size < (((u32)length * 2) - 1)) {
626 DEBUGOUT("PBA string buffer too small\n");
627 return IXGBE_ERR_NO_SPACE;
630 /* trim pba length from start of string */
634 for (offset = 0; offset < length; offset++) {
635 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
637 DEBUGOUT("NVM Read Error\n");
640 pba_num[offset * 2] = (u8)(data >> 8);
641 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
643 pba_num[offset * 2] = '\0';
645 return IXGBE_SUCCESS;
649 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
650 * @hw: pointer to hardware structure
651 * @pba_num: stores the part number from the EEPROM
653 * Reads the part number from the EEPROM.
655 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
660 DEBUGFUNC("ixgbe_read_pba_num_generic");
662 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
664 DEBUGOUT("NVM Read Error\n");
666 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
667 DEBUGOUT("NVM Not supported\n");
668 return IXGBE_NOT_IMPLEMENTED;
670 *pba_num = (u32)(data << 16);
672 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
674 DEBUGOUT("NVM Read Error\n");
679 return IXGBE_SUCCESS;
683 * ixgbe_get_mac_addr_generic - Generic get MAC address
684 * @hw: pointer to hardware structure
685 * @mac_addr: Adapter MAC address
687 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
688 * A reset of the adapter must be performed prior to calling this function
689 * in order for the MAC address to have been loaded from the EEPROM into RAR0
691 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
697 DEBUGFUNC("ixgbe_get_mac_addr_generic");
699 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
700 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
702 for (i = 0; i < 4; i++)
703 mac_addr[i] = (u8)(rar_low >> (i*8));
705 for (i = 0; i < 2; i++)
706 mac_addr[i+4] = (u8)(rar_high >> (i*8));
708 return IXGBE_SUCCESS;
712 * ixgbe_get_bus_info_generic - Generic set PCI bus info
713 * @hw: pointer to hardware structure
715 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
717 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
719 struct ixgbe_mac_info *mac = &hw->mac;
722 DEBUGFUNC("ixgbe_get_bus_info_generic");
724 hw->bus.type = ixgbe_bus_type_pci_express;
726 /* Get the negotiated link width and speed from PCI config space */
727 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
729 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
730 case IXGBE_PCI_LINK_WIDTH_1:
731 hw->bus.width = ixgbe_bus_width_pcie_x1;
733 case IXGBE_PCI_LINK_WIDTH_2:
734 hw->bus.width = ixgbe_bus_width_pcie_x2;
736 case IXGBE_PCI_LINK_WIDTH_4:
737 hw->bus.width = ixgbe_bus_width_pcie_x4;
739 case IXGBE_PCI_LINK_WIDTH_8:
740 hw->bus.width = ixgbe_bus_width_pcie_x8;
743 hw->bus.width = ixgbe_bus_width_unknown;
747 switch (link_status & IXGBE_PCI_LINK_SPEED) {
748 case IXGBE_PCI_LINK_SPEED_2500:
749 hw->bus.speed = ixgbe_bus_speed_2500;
751 case IXGBE_PCI_LINK_SPEED_5000:
752 hw->bus.speed = ixgbe_bus_speed_5000;
754 case IXGBE_PCI_LINK_SPEED_8000:
755 hw->bus.speed = ixgbe_bus_speed_8000;
758 hw->bus.speed = ixgbe_bus_speed_unknown;
762 mac->ops.set_lan_id(hw);
764 return IXGBE_SUCCESS;
768 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
769 * @hw: pointer to the HW structure
771 * Determines the LAN function id by reading memory-mapped registers
772 * and swaps the port value if requested.
774 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
776 struct ixgbe_bus_info *bus = &hw->bus;
779 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
781 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
782 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
783 bus->lan_id = bus->func;
785 /* check for a port swap */
786 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
787 if (reg & IXGBE_FACTPS_LFS)
792 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
793 * @hw: pointer to hardware structure
795 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
796 * disables transmit and receive units. The adapter_stopped flag is used by
797 * the shared code and drivers to determine if the adapter is in a stopped
798 * state and should not touch the hardware.
800 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
805 DEBUGFUNC("ixgbe_stop_adapter_generic");
808 * Set the adapter_stopped flag so other driver functions stop touching
811 hw->adapter_stopped = TRUE;
813 /* Disable the receive unit */
814 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
816 /* Clear interrupt mask to stop interrupts from being generated */
817 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
819 /* Clear any pending interrupts, flush previous writes */
820 IXGBE_READ_REG(hw, IXGBE_EICR);
822 /* Disable the transmit unit. Each queue must be disabled. */
823 for (i = 0; i < hw->mac.max_tx_queues; i++)
824 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
826 /* Disable the receive unit by stopping each queue */
827 for (i = 0; i < hw->mac.max_rx_queues; i++) {
828 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
829 reg_val &= ~IXGBE_RXDCTL_ENABLE;
830 reg_val |= IXGBE_RXDCTL_SWFLSH;
831 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
834 /* flush all queues disables */
835 IXGBE_WRITE_FLUSH(hw);
839 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
840 * access and verify no pending requests
842 return ixgbe_disable_pcie_master(hw);
846 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
847 * @hw: pointer to hardware structure
848 * @index: led number to turn on
850 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
852 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
854 DEBUGFUNC("ixgbe_led_on_generic");
856 /* To turn on the LED, set mode to ON. */
857 led_reg &= ~IXGBE_LED_MODE_MASK(index);
858 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
859 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
860 IXGBE_WRITE_FLUSH(hw);
862 return IXGBE_SUCCESS;
866 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
867 * @hw: pointer to hardware structure
868 * @index: led number to turn off
870 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
872 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
874 DEBUGFUNC("ixgbe_led_off_generic");
876 /* To turn off the LED, set mode to OFF. */
877 led_reg &= ~IXGBE_LED_MODE_MASK(index);
878 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
879 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
880 IXGBE_WRITE_FLUSH(hw);
882 return IXGBE_SUCCESS;
886 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
887 * @hw: pointer to hardware structure
889 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
890 * ixgbe_hw struct in order to set up EEPROM access.
892 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
894 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
898 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
900 if (eeprom->type == ixgbe_eeprom_uninitialized) {
901 eeprom->type = ixgbe_eeprom_none;
902 /* Set default semaphore delay to 10ms which is a well
904 eeprom->semaphore_delay = 10;
905 /* Clear EEPROM page size, it will be initialized as needed */
906 eeprom->word_page_size = 0;
909 * Check for EEPROM present first.
910 * If not present leave as none
912 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
913 if (eec & IXGBE_EEC_PRES) {
914 eeprom->type = ixgbe_eeprom_spi;
917 * SPI EEPROM is assumed here. This code would need to
918 * change if a future EEPROM is not SPI.
920 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
921 IXGBE_EEC_SIZE_SHIFT);
922 eeprom->word_size = 1 << (eeprom_size +
923 IXGBE_EEPROM_WORD_SIZE_SHIFT);
926 if (eec & IXGBE_EEC_ADDR_SIZE)
927 eeprom->address_bits = 16;
929 eeprom->address_bits = 8;
930 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
931 "%d\n", eeprom->type, eeprom->word_size,
932 eeprom->address_bits);
935 return IXGBE_SUCCESS;
939 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
940 * @hw: pointer to hardware structure
941 * @offset: offset within the EEPROM to write
942 * @words: number of word(s)
943 * @data: 16 bit word(s) to write to EEPROM
945 * Reads 16 bit word(s) from EEPROM through bit-bang method
947 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
948 u16 words, u16 *data)
950 s32 status = IXGBE_SUCCESS;
953 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
955 hw->eeprom.ops.init_params(hw);
958 status = IXGBE_ERR_INVALID_ARGUMENT;
962 if (offset + words > hw->eeprom.word_size) {
963 status = IXGBE_ERR_EEPROM;
968 * The EEPROM page size cannot be queried from the chip. We do lazy
969 * initialization. It is worth to do that when we write large buffer.
971 if ((hw->eeprom.word_page_size == 0) &&
972 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
973 ixgbe_detect_eeprom_page_size_generic(hw, offset);
976 * We cannot hold synchronization semaphores for too long
977 * to avoid other entity starvation. However it is more efficient
978 * to read in bursts than synchronizing access for each word.
980 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
981 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
982 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
983 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
986 if (status != IXGBE_SUCCESS)
995 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
996 * @hw: pointer to hardware structure
997 * @offset: offset within the EEPROM to be written to
998 * @words: number of word(s)
999 * @data: 16 bit word(s) to be written to the EEPROM
1001 * If ixgbe_eeprom_update_checksum is not called after this function, the
1002 * EEPROM will most likely contain an invalid checksum.
1004 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1005 u16 words, u16 *data)
1011 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1013 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1015 /* Prepare the EEPROM for writing */
1016 status = ixgbe_acquire_eeprom(hw);
1018 if (status == IXGBE_SUCCESS) {
1019 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1020 ixgbe_release_eeprom(hw);
1021 status = IXGBE_ERR_EEPROM;
1025 if (status == IXGBE_SUCCESS) {
1026 for (i = 0; i < words; i++) {
1027 ixgbe_standby_eeprom(hw);
1029 /* Send the WRITE ENABLE command (8 bit opcode ) */
1030 ixgbe_shift_out_eeprom_bits(hw,
1031 IXGBE_EEPROM_WREN_OPCODE_SPI,
1032 IXGBE_EEPROM_OPCODE_BITS);
1034 ixgbe_standby_eeprom(hw);
1037 * Some SPI eeproms use the 8th address bit embedded
1040 if ((hw->eeprom.address_bits == 8) &&
1041 ((offset + i) >= 128))
1042 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1044 /* Send the Write command (8-bit opcode + addr) */
1045 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1046 IXGBE_EEPROM_OPCODE_BITS);
1047 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1048 hw->eeprom.address_bits);
1050 page_size = hw->eeprom.word_page_size;
1052 /* Send the data in burst via SPI*/
1055 word = (word >> 8) | (word << 8);
1056 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1061 /* do not wrap around page */
1062 if (((offset + i) & (page_size - 1)) ==
1065 } while (++i < words);
1067 ixgbe_standby_eeprom(hw);
1070 /* Done with writing - release the EEPROM */
1071 ixgbe_release_eeprom(hw);
1078 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1079 * @hw: pointer to hardware structure
1080 * @offset: offset within the EEPROM to be written to
1081 * @data: 16 bit word to be written to the EEPROM
1083 * If ixgbe_eeprom_update_checksum is not called after this function, the
1084 * EEPROM will most likely contain an invalid checksum.
1086 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1090 DEBUGFUNC("ixgbe_write_eeprom_generic");
1092 hw->eeprom.ops.init_params(hw);
1094 if (offset >= hw->eeprom.word_size) {
1095 status = IXGBE_ERR_EEPROM;
1099 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1106 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1107 * @hw: pointer to hardware structure
1108 * @offset: offset within the EEPROM to be read
1109 * @data: read 16 bit words(s) from EEPROM
1110 * @words: number of word(s)
1112 * Reads 16 bit word(s) from EEPROM through bit-bang method
1114 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1115 u16 words, u16 *data)
1117 s32 status = IXGBE_SUCCESS;
1120 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1122 hw->eeprom.ops.init_params(hw);
1125 status = IXGBE_ERR_INVALID_ARGUMENT;
1129 if (offset + words > hw->eeprom.word_size) {
1130 status = IXGBE_ERR_EEPROM;
1135 * We cannot hold synchronization semaphores for too long
1136 * to avoid other entity starvation. However it is more efficient
1137 * to read in bursts than synchronizing access for each word.
1139 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1140 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1141 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1143 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1146 if (status != IXGBE_SUCCESS)
1155 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1156 * @hw: pointer to hardware structure
1157 * @offset: offset within the EEPROM to be read
1158 * @words: number of word(s)
1159 * @data: read 16 bit word(s) from EEPROM
1161 * Reads 16 bit word(s) from EEPROM through bit-bang method
1163 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1164 u16 words, u16 *data)
1168 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1171 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1173 /* Prepare the EEPROM for reading */
1174 status = ixgbe_acquire_eeprom(hw);
1176 if (status == IXGBE_SUCCESS) {
1177 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1178 ixgbe_release_eeprom(hw);
1179 status = IXGBE_ERR_EEPROM;
1183 if (status == IXGBE_SUCCESS) {
1184 for (i = 0; i < words; i++) {
1185 ixgbe_standby_eeprom(hw);
1187 * Some SPI eeproms use the 8th address bit embedded
1190 if ((hw->eeprom.address_bits == 8) &&
1191 ((offset + i) >= 128))
1192 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1194 /* Send the READ command (opcode + addr) */
1195 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1196 IXGBE_EEPROM_OPCODE_BITS);
1197 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1198 hw->eeprom.address_bits);
1200 /* Read the data. */
1201 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1202 data[i] = (word_in >> 8) | (word_in << 8);
1205 /* End this read operation */
1206 ixgbe_release_eeprom(hw);
1213 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1214 * @hw: pointer to hardware structure
1215 * @offset: offset within the EEPROM to be read
1216 * @data: read 16 bit value from EEPROM
1218 * Reads 16 bit value from EEPROM through bit-bang method
1220 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1225 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1227 hw->eeprom.ops.init_params(hw);
1229 if (offset >= hw->eeprom.word_size) {
1230 status = IXGBE_ERR_EEPROM;
1234 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1241 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1242 * @hw: pointer to hardware structure
1243 * @offset: offset of word in the EEPROM to read
1244 * @words: number of word(s)
1245 * @data: 16 bit word(s) from the EEPROM
1247 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1249 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1250 u16 words, u16 *data)
1253 s32 status = IXGBE_SUCCESS;
1256 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1258 hw->eeprom.ops.init_params(hw);
1261 status = IXGBE_ERR_INVALID_ARGUMENT;
1265 if (offset >= hw->eeprom.word_size) {
1266 status = IXGBE_ERR_EEPROM;
1270 for (i = 0; i < words; i++) {
1271 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1272 IXGBE_EEPROM_RW_REG_START;
1274 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1275 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1277 if (status == IXGBE_SUCCESS) {
1278 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1279 IXGBE_EEPROM_RW_REG_DATA);
1281 DEBUGOUT("Eeprom read timed out\n");
1290 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1291 * @hw: pointer to hardware structure
1292 * @offset: offset within the EEPROM to be used as a scratch pad
1294 * Discover EEPROM page size by writing marching data at given offset.
1295 * This function is called only when we are writing a new large buffer
1296 * at given offset so the data would be overwritten anyway.
1298 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1301 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1302 s32 status = IXGBE_SUCCESS;
1305 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1307 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1310 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1311 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1312 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1313 hw->eeprom.word_page_size = 0;
1314 if (status != IXGBE_SUCCESS)
1317 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1318 if (status != IXGBE_SUCCESS)
1322 * When writing in burst more than the actual page size
1323 * EEPROM address wraps around current page.
1325 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1327 DEBUGOUT1("Detected EEPROM page size = %d words.",
1328 hw->eeprom.word_page_size);
1334 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1335 * @hw: pointer to hardware structure
1336 * @offset: offset of word in the EEPROM to read
1337 * @data: word read from the EEPROM
1339 * Reads a 16 bit word from the EEPROM using the EERD register.
1341 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1343 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1347 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1348 * @hw: pointer to hardware structure
1349 * @offset: offset of word in the EEPROM to write
1350 * @words: number of word(s)
1351 * @data: word(s) write to the EEPROM
1353 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1355 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1356 u16 words, u16 *data)
1359 s32 status = IXGBE_SUCCESS;
1362 DEBUGFUNC("ixgbe_write_eewr_generic");
1364 hw->eeprom.ops.init_params(hw);
1367 status = IXGBE_ERR_INVALID_ARGUMENT;
1371 if (offset >= hw->eeprom.word_size) {
1372 status = IXGBE_ERR_EEPROM;
1376 for (i = 0; i < words; i++) {
1377 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1378 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1379 IXGBE_EEPROM_RW_REG_START;
1381 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1382 if (status != IXGBE_SUCCESS) {
1383 DEBUGOUT("Eeprom write EEWR timed out\n");
1387 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1389 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1390 if (status != IXGBE_SUCCESS) {
1391 DEBUGOUT("Eeprom write EEWR timed out\n");
1401 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1402 * @hw: pointer to hardware structure
1403 * @offset: offset of word in the EEPROM to write
1404 * @data: word write to the EEPROM
1406 * Write a 16 bit word to the EEPROM using the EEWR register.
1408 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1410 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1414 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1415 * @hw: pointer to hardware structure
1416 * @ee_reg: EEPROM flag for polling
1418 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1419 * read or write is done respectively.
1421 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1425 s32 status = IXGBE_ERR_EEPROM;
1427 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1429 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1430 if (ee_reg == IXGBE_NVM_POLL_READ)
1431 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1433 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1435 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1436 status = IXGBE_SUCCESS;
1445 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1446 * @hw: pointer to hardware structure
1448 * Prepares EEPROM for access using bit-bang method. This function should
1449 * be called before issuing a command to the EEPROM.
1451 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1453 s32 status = IXGBE_SUCCESS;
1457 DEBUGFUNC("ixgbe_acquire_eeprom");
1459 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1461 status = IXGBE_ERR_SWFW_SYNC;
1463 if (status == IXGBE_SUCCESS) {
1464 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1466 /* Request EEPROM Access */
1467 eec |= IXGBE_EEC_REQ;
1468 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1470 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1471 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1472 if (eec & IXGBE_EEC_GNT)
1477 /* Release if grant not acquired */
1478 if (!(eec & IXGBE_EEC_GNT)) {
1479 eec &= ~IXGBE_EEC_REQ;
1480 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1481 DEBUGOUT("Could not acquire EEPROM grant\n");
1483 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1484 status = IXGBE_ERR_EEPROM;
1487 /* Setup EEPROM for Read/Write */
1488 if (status == IXGBE_SUCCESS) {
1489 /* Clear CS and SK */
1490 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1491 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1492 IXGBE_WRITE_FLUSH(hw);
1500 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1501 * @hw: pointer to hardware structure
1503 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1505 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1507 s32 status = IXGBE_ERR_EEPROM;
1512 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1515 /* Get SMBI software semaphore between device drivers first */
1516 for (i = 0; i < timeout; i++) {
1518 * If the SMBI bit is 0 when we read it, then the bit will be
1519 * set and we have the semaphore
1521 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1522 if (!(swsm & IXGBE_SWSM_SMBI)) {
1523 status = IXGBE_SUCCESS;
1530 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1533 * this release is particularly important because our attempts
1534 * above to get the semaphore may have succeeded, and if there
1535 * was a timeout, we should unconditionally clear the semaphore
1536 * bits to free the driver to make progress
1538 ixgbe_release_eeprom_semaphore(hw);
1543 * If the SMBI bit is 0 when we read it, then the bit will be
1544 * set and we have the semaphore
1546 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1547 if (!(swsm & IXGBE_SWSM_SMBI))
1548 status = IXGBE_SUCCESS;
1551 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1552 if (status == IXGBE_SUCCESS) {
1553 for (i = 0; i < timeout; i++) {
1554 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1556 /* Set the SW EEPROM semaphore bit to request access */
1557 swsm |= IXGBE_SWSM_SWESMBI;
1558 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1561 * If we set the bit successfully then we got the
1564 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1565 if (swsm & IXGBE_SWSM_SWESMBI)
1572 * Release semaphores and return error if SW EEPROM semaphore
1573 * was not granted because we don't have access to the EEPROM
1576 DEBUGOUT("SWESMBI Software EEPROM semaphore "
1578 ixgbe_release_eeprom_semaphore(hw);
1579 status = IXGBE_ERR_EEPROM;
1582 DEBUGOUT("Software semaphore SMBI between device drivers "
1590 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1591 * @hw: pointer to hardware structure
1593 * This function clears hardware semaphore bits.
1595 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1599 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1601 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1603 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1604 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1605 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1606 IXGBE_WRITE_FLUSH(hw);
1610 * ixgbe_ready_eeprom - Polls for EEPROM ready
1611 * @hw: pointer to hardware structure
1613 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1615 s32 status = IXGBE_SUCCESS;
1619 DEBUGFUNC("ixgbe_ready_eeprom");
1622 * Read "Status Register" repeatedly until the LSB is cleared. The
1623 * EEPROM will signal that the command has been completed by clearing
1624 * bit 0 of the internal status register. If it's not cleared within
1625 * 5 milliseconds, then error out.
1627 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1628 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1629 IXGBE_EEPROM_OPCODE_BITS);
1630 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1631 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1635 ixgbe_standby_eeprom(hw);
1639 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1640 * devices (and only 0-5mSec on 5V devices)
1642 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1643 DEBUGOUT("SPI EEPROM Status error\n");
1644 status = IXGBE_ERR_EEPROM;
1651 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1652 * @hw: pointer to hardware structure
1654 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1658 DEBUGFUNC("ixgbe_standby_eeprom");
1660 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1662 /* Toggle CS to flush commands */
1663 eec |= IXGBE_EEC_CS;
1664 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1665 IXGBE_WRITE_FLUSH(hw);
1667 eec &= ~IXGBE_EEC_CS;
1668 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1669 IXGBE_WRITE_FLUSH(hw);
1674 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1675 * @hw: pointer to hardware structure
1676 * @data: data to send to the EEPROM
1677 * @count: number of bits to shift out
1679 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1686 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1688 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1691 * Mask is used to shift "count" bits of "data" out to the EEPROM
1692 * one bit at a time. Determine the starting bit based on count
1694 mask = 0x01 << (count - 1);
1696 for (i = 0; i < count; i++) {
1698 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1699 * "1", and then raising and then lowering the clock (the SK
1700 * bit controls the clock input to the EEPROM). A "0" is
1701 * shifted out to the EEPROM by setting "DI" to "0" and then
1702 * raising and then lowering the clock.
1705 eec |= IXGBE_EEC_DI;
1707 eec &= ~IXGBE_EEC_DI;
1709 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1710 IXGBE_WRITE_FLUSH(hw);
1714 ixgbe_raise_eeprom_clk(hw, &eec);
1715 ixgbe_lower_eeprom_clk(hw, &eec);
1718 * Shift mask to signify next bit of data to shift in to the
1724 /* We leave the "DI" bit set to "0" when we leave this routine. */
1725 eec &= ~IXGBE_EEC_DI;
1726 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1727 IXGBE_WRITE_FLUSH(hw);
1731 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1732 * @hw: pointer to hardware structure
1734 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1740 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1743 * In order to read a register from the EEPROM, we need to shift
1744 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1745 * the clock input to the EEPROM (setting the SK bit), and then reading
1746 * the value of the "DO" bit. During this "shifting in" process the
1747 * "DI" bit should always be clear.
1749 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1751 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1753 for (i = 0; i < count; i++) {
1755 ixgbe_raise_eeprom_clk(hw, &eec);
1757 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1759 eec &= ~(IXGBE_EEC_DI);
1760 if (eec & IXGBE_EEC_DO)
1763 ixgbe_lower_eeprom_clk(hw, &eec);
1770 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1771 * @hw: pointer to hardware structure
1772 * @eec: EEC register's current value
1774 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1776 DEBUGFUNC("ixgbe_raise_eeprom_clk");
1779 * Raise the clock input to the EEPROM
1780 * (setting the SK bit), then delay
1782 *eec = *eec | IXGBE_EEC_SK;
1783 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1784 IXGBE_WRITE_FLUSH(hw);
1789 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1790 * @hw: pointer to hardware structure
1791 * @eecd: EECD's current value
1793 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1795 DEBUGFUNC("ixgbe_lower_eeprom_clk");
1798 * Lower the clock input to the EEPROM (clearing the SK bit), then
1801 *eec = *eec & ~IXGBE_EEC_SK;
1802 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1803 IXGBE_WRITE_FLUSH(hw);
1808 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1809 * @hw: pointer to hardware structure
1811 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1815 DEBUGFUNC("ixgbe_release_eeprom");
1817 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1819 eec |= IXGBE_EEC_CS; /* Pull CS high */
1820 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1822 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1823 IXGBE_WRITE_FLUSH(hw);
1827 /* Stop requesting EEPROM access */
1828 eec &= ~IXGBE_EEC_REQ;
1829 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1831 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1833 /* Delay before attempt to obtain semaphore again to allow FW access */
1834 msec_delay(hw->eeprom.semaphore_delay);
1838 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1839 * @hw: pointer to hardware structure
1841 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1850 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1852 /* Include 0x0-0x3F in the checksum */
1853 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1854 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1855 DEBUGOUT("EEPROM read failed\n");
1861 /* Include all data from pointers except for the fw pointer */
1862 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1863 hw->eeprom.ops.read(hw, i, &pointer);
1865 /* Make sure the pointer seems valid */
1866 if (pointer != 0xFFFF && pointer != 0) {
1867 hw->eeprom.ops.read(hw, pointer, &length);
1869 if (length != 0xFFFF && length != 0) {
1870 for (j = pointer+1; j <= pointer+length; j++) {
1871 hw->eeprom.ops.read(hw, j, &word);
1878 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1884 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1885 * @hw: pointer to hardware structure
1886 * @checksum_val: calculated checksum
1888 * Performs checksum calculation and validates the EEPROM checksum. If the
1889 * caller does not need checksum_val, the value can be NULL.
1891 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1896 u16 read_checksum = 0;
1898 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
1901 * Read the first word from the EEPROM. If this times out or fails, do
1902 * not continue or we could be in for a very long wait while every
1905 status = hw->eeprom.ops.read(hw, 0, &checksum);
1907 if (status == IXGBE_SUCCESS) {
1908 checksum = hw->eeprom.ops.calc_checksum(hw);
1910 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1913 * Verify read checksum from EEPROM is the same as
1914 * calculated checksum
1916 if (read_checksum != checksum)
1917 status = IXGBE_ERR_EEPROM_CHECKSUM;
1919 /* If the user cares, return the calculated checksum */
1921 *checksum_val = checksum;
1923 DEBUGOUT("EEPROM read failed\n");
1930 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1931 * @hw: pointer to hardware structure
1933 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1938 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
1941 * Read the first word from the EEPROM. If this times out or fails, do
1942 * not continue or we could be in for a very long wait while every
1945 status = hw->eeprom.ops.read(hw, 0, &checksum);
1947 if (status == IXGBE_SUCCESS) {
1948 checksum = hw->eeprom.ops.calc_checksum(hw);
1949 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1952 DEBUGOUT("EEPROM read failed\n");
1959 * ixgbe_validate_mac_addr - Validate MAC address
1960 * @mac_addr: pointer to MAC address.
1962 * Tests a MAC address to ensure it is a valid Individual Address
1964 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1966 s32 status = IXGBE_SUCCESS;
1968 DEBUGFUNC("ixgbe_validate_mac_addr");
1970 /* Make sure it is not a multicast address */
1971 if (IXGBE_IS_MULTICAST(mac_addr)) {
1972 DEBUGOUT("MAC address is multicast\n");
1973 status = IXGBE_ERR_INVALID_MAC_ADDR;
1974 /* Not a broadcast address */
1975 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1976 DEBUGOUT("MAC address is broadcast\n");
1977 status = IXGBE_ERR_INVALID_MAC_ADDR;
1978 /* Reject the zero address */
1979 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1980 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1981 DEBUGOUT("MAC address is all zeros\n");
1982 status = IXGBE_ERR_INVALID_MAC_ADDR;
1988 * ixgbe_set_rar_generic - Set Rx address register
1989 * @hw: pointer to hardware structure
1990 * @index: Receive address register to write
1991 * @addr: Address to put into receive address register
1992 * @vmdq: VMDq "set" or "pool" index
1993 * @enable_addr: set flag that address is active
1995 * Puts an ethernet address into a receive address register.
1997 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2000 u32 rar_low, rar_high;
2001 u32 rar_entries = hw->mac.num_rar_entries;
2003 DEBUGFUNC("ixgbe_set_rar_generic");
2005 /* Make sure we are using a valid rar index range */
2006 if (index >= rar_entries) {
2007 DEBUGOUT1("RAR index %d is out of range.\n", index);
2008 return IXGBE_ERR_INVALID_ARGUMENT;
2011 /* setup VMDq pool selection before this RAR gets enabled */
2012 hw->mac.ops.set_vmdq(hw, index, vmdq);
2015 * HW expects these in little endian so we reverse the byte
2016 * order from network order (big endian) to little endian
2018 rar_low = ((u32)addr[0] |
2019 ((u32)addr[1] << 8) |
2020 ((u32)addr[2] << 16) |
2021 ((u32)addr[3] << 24));
2023 * Some parts put the VMDq setting in the extra RAH bits,
2024 * so save everything except the lower 16 bits that hold part
2025 * of the address and the address valid bit.
2027 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2028 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2029 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2031 if (enable_addr != 0)
2032 rar_high |= IXGBE_RAH_AV;
2034 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2035 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2037 return IXGBE_SUCCESS;
2041 * ixgbe_clear_rar_generic - Remove Rx address register
2042 * @hw: pointer to hardware structure
2043 * @index: Receive address register to write
2045 * Clears an ethernet address from a receive address register.
2047 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2050 u32 rar_entries = hw->mac.num_rar_entries;
2052 DEBUGFUNC("ixgbe_clear_rar_generic");
2054 /* Make sure we are using a valid rar index range */
2055 if (index >= rar_entries) {
2056 DEBUGOUT1("RAR index %d is out of range.\n", index);
2057 return IXGBE_ERR_INVALID_ARGUMENT;
2061 * Some parts put the VMDq setting in the extra RAH bits,
2062 * so save everything except the lower 16 bits that hold part
2063 * of the address and the address valid bit.
2065 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2066 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2068 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2069 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2071 /* clear VMDq pool/queue selection for this RAR */
2072 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2074 return IXGBE_SUCCESS;
2078 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2079 * @hw: pointer to hardware structure
2081 * Places the MAC address in receive address register 0 and clears the rest
2082 * of the receive address registers. Clears the multicast table. Assumes
2083 * the receiver is in reset when the routine is called.
2085 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2088 u32 rar_entries = hw->mac.num_rar_entries;
2090 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2093 * If the current mac address is valid, assume it is a software override
2094 * to the permanent address.
2095 * Otherwise, use the permanent address from the eeprom.
2097 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2098 IXGBE_ERR_INVALID_MAC_ADDR) {
2099 /* Get the MAC address from the RAR0 for later reference */
2100 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2102 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2103 hw->mac.addr[0], hw->mac.addr[1],
2105 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2106 hw->mac.addr[4], hw->mac.addr[5]);
2108 /* Setup the receive address. */
2109 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2110 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2111 hw->mac.addr[0], hw->mac.addr[1],
2113 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2114 hw->mac.addr[4], hw->mac.addr[5]);
2116 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2118 /* clear VMDq pool/queue selection for RAR 0 */
2119 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2121 hw->addr_ctrl.overflow_promisc = 0;
2123 hw->addr_ctrl.rar_used_count = 1;
2125 /* Zero out the other receive addresses. */
2126 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2127 for (i = 1; i < rar_entries; i++) {
2128 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2129 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2133 hw->addr_ctrl.mta_in_use = 0;
2134 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2136 DEBUGOUT(" Clearing MTA\n");
2137 for (i = 0; i < hw->mac.mcft_size; i++)
2138 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2140 ixgbe_init_uta_tables(hw);
2142 return IXGBE_SUCCESS;
2146 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2147 * @hw: pointer to hardware structure
2148 * @addr: new address
2150 * Adds it to unused receive address register or goes into promiscuous mode.
2152 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2154 u32 rar_entries = hw->mac.num_rar_entries;
2157 DEBUGFUNC("ixgbe_add_uc_addr");
2159 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2160 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2163 * Place this address in the RAR if there is room,
2164 * else put the controller into promiscuous mode
2166 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2167 rar = hw->addr_ctrl.rar_used_count;
2168 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2169 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2170 hw->addr_ctrl.rar_used_count++;
2172 hw->addr_ctrl.overflow_promisc++;
2175 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2179 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2180 * @hw: pointer to hardware structure
2181 * @addr_list: the list of new addresses
2182 * @addr_count: number of addresses
2183 * @next: iterator function to walk the address list
2185 * The given list replaces any existing list. Clears the secondary addrs from
2186 * receive address registers. Uses unused receive address registers for the
2187 * first secondary addresses, and falls back to promiscuous mode as needed.
2189 * Drivers using secondary unicast addresses must set user_set_promisc when
2190 * manually putting the device into promiscuous mode.
2192 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2193 u32 addr_count, ixgbe_mc_addr_itr next)
2197 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2202 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2205 * Clear accounting of old secondary address list,
2206 * don't count RAR[0]
2208 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2209 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2210 hw->addr_ctrl.overflow_promisc = 0;
2212 /* Zero out the other receive addresses */
2213 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2214 for (i = 0; i < uc_addr_in_use; i++) {
2215 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2216 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2219 /* Add the new addresses */
2220 for (i = 0; i < addr_count; i++) {
2221 DEBUGOUT(" Adding the secondary addresses:\n");
2222 addr = next(hw, &addr_list, &vmdq);
2223 ixgbe_add_uc_addr(hw, addr, vmdq);
2226 if (hw->addr_ctrl.overflow_promisc) {
2227 /* enable promisc if not already in overflow or set by user */
2228 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2229 DEBUGOUT(" Entering address overflow promisc mode\n");
2230 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2231 fctrl |= IXGBE_FCTRL_UPE;
2232 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2235 /* only disable if set by overflow, not by user */
2236 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2237 DEBUGOUT(" Leaving address overflow promisc mode\n");
2238 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2239 fctrl &= ~IXGBE_FCTRL_UPE;
2240 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2244 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2245 return IXGBE_SUCCESS;
2249 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2250 * @hw: pointer to hardware structure
2251 * @mc_addr: the multicast address
2253 * Extracts the 12 bits, from a multicast address, to determine which
2254 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2255 * incoming rx multicast addresses, to determine the bit-vector to check in
2256 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2257 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2258 * to mc_filter_type.
2260 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2264 DEBUGFUNC("ixgbe_mta_vector");
2266 switch (hw->mac.mc_filter_type) {
2267 case 0: /* use bits [47:36] of the address */
2268 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2270 case 1: /* use bits [46:35] of the address */
2271 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2273 case 2: /* use bits [45:34] of the address */
2274 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2276 case 3: /* use bits [43:32] of the address */
2277 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2279 default: /* Invalid mc_filter_type */
2280 DEBUGOUT("MC filter type param set incorrectly\n");
2285 /* vector can only be 12-bits or boundary will be exceeded */
2291 * ixgbe_set_mta - Set bit-vector in multicast table
2292 * @hw: pointer to hardware structure
2293 * @hash_value: Multicast address hash value
2295 * Sets the bit-vector in the multicast table.
2297 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2303 DEBUGFUNC("ixgbe_set_mta");
2305 hw->addr_ctrl.mta_in_use++;
2307 vector = ixgbe_mta_vector(hw, mc_addr);
2308 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2311 * The MTA is a register array of 128 32-bit registers. It is treated
2312 * like an array of 4096 bits. We want to set bit
2313 * BitArray[vector_value]. So we figure out what register the bit is
2314 * in, read it, OR in the new bit, then write back the new value. The
2315 * register is determined by the upper 7 bits of the vector value and
2316 * the bit within that register are determined by the lower 5 bits of
2319 vector_reg = (vector >> 5) & 0x7F;
2320 vector_bit = vector & 0x1F;
2321 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2325 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2326 * @hw: pointer to hardware structure
2327 * @mc_addr_list: the list of new multicast addresses
2328 * @mc_addr_count: number of addresses
2329 * @next: iterator function to walk the multicast address list
2330 * @clear: flag, when set clears the table beforehand
2332 * When the clear flag is set, the given list replaces any existing list.
2333 * Hashes the given addresses into the multicast table.
2335 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2336 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2342 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2345 * Set the new number of MC addresses that we are being requested to
2348 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2349 hw->addr_ctrl.mta_in_use = 0;
2351 /* Clear mta_shadow */
2353 DEBUGOUT(" Clearing MTA\n");
2354 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2357 /* Update mta_shadow */
2358 for (i = 0; i < mc_addr_count; i++) {
2359 DEBUGOUT(" Adding the multicast addresses:\n");
2360 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2364 for (i = 0; i < hw->mac.mcft_size; i++)
2365 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2366 hw->mac.mta_shadow[i]);
2368 if (hw->addr_ctrl.mta_in_use > 0)
2369 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2370 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2372 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2373 return IXGBE_SUCCESS;
2377 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2378 * @hw: pointer to hardware structure
2380 * Enables multicast address in RAR and the use of the multicast hash table.
2382 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2384 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2386 DEBUGFUNC("ixgbe_enable_mc_generic");
2388 if (a->mta_in_use > 0)
2389 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2390 hw->mac.mc_filter_type);
2392 return IXGBE_SUCCESS;
2396 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2397 * @hw: pointer to hardware structure
2399 * Disables multicast address in RAR and the use of the multicast hash table.
2401 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2403 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2405 DEBUGFUNC("ixgbe_disable_mc_generic");
2407 if (a->mta_in_use > 0)
2408 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2410 return IXGBE_SUCCESS;
2414 * ixgbe_fc_enable_generic - Enable flow control
2415 * @hw: pointer to hardware structure
2417 * Enable flow control according to the current settings.
2419 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2421 s32 ret_val = IXGBE_SUCCESS;
2422 u32 mflcn_reg, fccfg_reg;
2427 DEBUGFUNC("ixgbe_fc_enable_generic");
2429 /* Validate the water mark configuration */
2430 if (!hw->fc.pause_time) {
2431 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2435 /* Low water mark of zero causes XOFF floods */
2436 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2437 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2438 hw->fc.high_water[i]) {
2439 if (!hw->fc.low_water[i] ||
2440 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2441 DEBUGOUT("Invalid water mark configuration\n");
2442 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2448 /* Negotiate the fc mode to use */
2449 ixgbe_fc_autoneg(hw);
2451 /* Disable any previous flow control settings */
2452 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2453 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2455 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2456 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2459 * The possible values of fc.current_mode are:
2460 * 0: Flow control is completely disabled
2461 * 1: Rx flow control is enabled (we can receive pause frames,
2462 * but not send pause frames).
2463 * 2: Tx flow control is enabled (we can send pause frames but
2464 * we do not support receiving pause frames).
2465 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2468 switch (hw->fc.current_mode) {
2471 * Flow control is disabled by software override or autoneg.
2472 * The code below will actually disable it in the HW.
2475 case ixgbe_fc_rx_pause:
2477 * Rx Flow control is enabled and Tx Flow control is
2478 * disabled by software override. Since there really
2479 * isn't a way to advertise that we are capable of RX
2480 * Pause ONLY, we will advertise that we support both
2481 * symmetric and asymmetric Rx PAUSE. Later, we will
2482 * disable the adapter's ability to send PAUSE frames.
2484 mflcn_reg |= IXGBE_MFLCN_RFCE;
2486 case ixgbe_fc_tx_pause:
2488 * Tx Flow control is enabled, and Rx Flow control is
2489 * disabled by software override.
2491 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2494 /* Flow control (both Rx and Tx) is enabled by SW override. */
2495 mflcn_reg |= IXGBE_MFLCN_RFCE;
2496 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2499 DEBUGOUT("Flow control param set incorrectly\n");
2500 ret_val = IXGBE_ERR_CONFIG;
2505 /* Set 802.3x based flow control settings. */
2506 mflcn_reg |= IXGBE_MFLCN_DPF;
2507 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2508 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2511 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2512 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2513 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2514 hw->fc.high_water[i]) {
2515 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2516 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2517 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2519 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2521 * In order to prevent Tx hangs when the internal Tx
2522 * switch is enabled we must set the high water mark
2523 * to the maximum FCRTH value. This allows the Tx
2524 * switch to function even under heavy Rx workloads.
2526 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2529 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2532 /* Configure pause time (2 TCs per register) */
2533 reg = hw->fc.pause_time * 0x00010001;
2534 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2535 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2537 /* Configure flow control refresh threshold value */
2538 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2545 * ixgbe_negotiate_fc - Negotiate flow control
2546 * @hw: pointer to hardware structure
2547 * @adv_reg: flow control advertised settings
2548 * @lp_reg: link partner's flow control settings
2549 * @adv_sym: symmetric pause bit in advertisement
2550 * @adv_asm: asymmetric pause bit in advertisement
2551 * @lp_sym: symmetric pause bit in link partner advertisement
2552 * @lp_asm: asymmetric pause bit in link partner advertisement
2554 * Find the intersection between advertised settings and link partner's
2555 * advertised settings
2557 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2558 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2560 if ((!(adv_reg)) || (!(lp_reg)))
2561 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2563 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2565 * Now we need to check if the user selected Rx ONLY
2566 * of pause frames. In this case, we had to advertise
2567 * FULL flow control because we could not advertise RX
2568 * ONLY. Hence, we must now check to see if we need to
2569 * turn OFF the TRANSMISSION of PAUSE frames.
2571 if (hw->fc.requested_mode == ixgbe_fc_full) {
2572 hw->fc.current_mode = ixgbe_fc_full;
2573 DEBUGOUT("Flow Control = FULL.\n");
2575 hw->fc.current_mode = ixgbe_fc_rx_pause;
2576 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2578 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2579 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2580 hw->fc.current_mode = ixgbe_fc_tx_pause;
2581 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2582 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2583 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2584 hw->fc.current_mode = ixgbe_fc_rx_pause;
2585 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2587 hw->fc.current_mode = ixgbe_fc_none;
2588 DEBUGOUT("Flow Control = NONE.\n");
2590 return IXGBE_SUCCESS;
2594 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2595 * @hw: pointer to hardware structure
2597 * Enable flow control according on 1 gig fiber.
2599 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2601 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2602 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2605 * On multispeed fiber at 1g, bail out if
2606 * - link is up but AN did not complete, or if
2607 * - link is up and AN completed but timed out
2610 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2611 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2612 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2615 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2616 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2618 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2619 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2620 IXGBE_PCS1GANA_ASM_PAUSE,
2621 IXGBE_PCS1GANA_SYM_PAUSE,
2622 IXGBE_PCS1GANA_ASM_PAUSE);
2629 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2630 * @hw: pointer to hardware structure
2632 * Enable flow control according to IEEE clause 37.
2634 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2636 u32 links2, anlp1_reg, autoc_reg, links;
2637 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2640 * On backplane, bail out if
2641 * - backplane autoneg was not completed, or if
2642 * - we are 82599 and link partner is not AN enabled
2644 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2645 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2648 if (hw->mac.type == ixgbe_mac_82599EB) {
2649 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2650 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2654 * Read the 10g AN autoc and LP ability registers and resolve
2655 * local flow control settings accordingly
2657 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2658 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2660 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2661 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2662 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2669 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2670 * @hw: pointer to hardware structure
2672 * Enable flow control according to IEEE clause 37.
2674 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2676 u16 technology_ability_reg = 0;
2677 u16 lp_technology_ability_reg = 0;
2679 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2680 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2681 &technology_ability_reg);
2682 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2683 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2684 &lp_technology_ability_reg);
2686 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2687 (u32)lp_technology_ability_reg,
2688 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2689 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2693 * ixgbe_fc_autoneg - Configure flow control
2694 * @hw: pointer to hardware structure
2696 * Compares our advertised flow control capabilities to those advertised by
2697 * our link partner, and determines the proper flow control mode to use.
2699 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2701 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2702 ixgbe_link_speed speed;
2705 DEBUGFUNC("ixgbe_fc_autoneg");
2708 * AN should have completed when the cable was plugged in.
2709 * Look for reasons to bail out. Bail out if:
2710 * - FC autoneg is disabled, or if
2713 if (hw->fc.disable_fc_autoneg)
2716 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2720 switch (hw->phy.media_type) {
2721 /* Autoneg flow control on fiber adapters */
2722 case ixgbe_media_type_fiber:
2723 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2724 ret_val = ixgbe_fc_autoneg_fiber(hw);
2727 /* Autoneg flow control on backplane adapters */
2728 case ixgbe_media_type_backplane:
2729 ret_val = ixgbe_fc_autoneg_backplane(hw);
2732 /* Autoneg flow control on copper adapters */
2733 case ixgbe_media_type_copper:
2734 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2735 ret_val = ixgbe_fc_autoneg_copper(hw);
2743 if (ret_val == IXGBE_SUCCESS) {
2744 hw->fc.fc_was_autonegged = TRUE;
2746 hw->fc.fc_was_autonegged = FALSE;
2747 hw->fc.current_mode = hw->fc.requested_mode;
2752 * ixgbe_disable_pcie_master - Disable PCI-express master access
2753 * @hw: pointer to hardware structure
2755 * Disables PCI-Express master access and verifies there are no pending
2756 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2757 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2758 * is returned signifying master requests disabled.
2760 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2762 s32 status = IXGBE_SUCCESS;
2765 DEBUGFUNC("ixgbe_disable_pcie_master");
2767 /* Always set this bit to ensure any future transactions are blocked */
2768 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2770 /* Exit if master requets are blocked */
2771 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2774 /* Poll for master request bit to clear */
2775 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2777 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2782 * Two consecutive resets are required via CTRL.RST per datasheet
2783 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2784 * of this need. The first reset prevents new master requests from
2785 * being issued by our device. We then must wait 1usec or more for any
2786 * remaining completions from the PCIe bus to trickle in, and then reset
2787 * again to clear out any effects they may have had on our device.
2789 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2790 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2793 * Before proceeding, make sure that the PCIe block does not have
2794 * transactions pending.
2796 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2798 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2799 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2803 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2804 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2811 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2812 * @hw: pointer to hardware structure
2813 * @mask: Mask to specify which semaphore to acquire
2815 * Acquires the SWFW semaphore through the GSSR register for the specified
2816 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2818 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2822 u32 fwmask = mask << 5;
2825 DEBUGFUNC("ixgbe_acquire_swfw_sync");
2829 * SW EEPROM semaphore bit is used for access to all
2830 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2832 if (ixgbe_get_eeprom_semaphore(hw))
2833 return IXGBE_ERR_SWFW_SYNC;
2835 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2836 if (!(gssr & (fwmask | swmask)))
2840 * Firmware currently using resource (fwmask) or other software
2841 * thread currently using resource (swmask)
2843 ixgbe_release_eeprom_semaphore(hw);
2849 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2850 return IXGBE_ERR_SWFW_SYNC;
2854 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2856 ixgbe_release_eeprom_semaphore(hw);
2857 return IXGBE_SUCCESS;
2861 * ixgbe_release_swfw_sync - Release SWFW semaphore
2862 * @hw: pointer to hardware structure
2863 * @mask: Mask to specify which semaphore to release
2865 * Releases the SWFW semaphore through the GSSR register for the specified
2866 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2868 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2873 DEBUGFUNC("ixgbe_release_swfw_sync");
2875 ixgbe_get_eeprom_semaphore(hw);
2877 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2879 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2881 ixgbe_release_eeprom_semaphore(hw);
2885 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2886 * @hw: pointer to hardware structure
2888 * Stops the receive data path and waits for the HW to internally empty
2889 * the Rx security block
2891 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2893 #define IXGBE_MAX_SECRX_POLL 40
2898 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
2901 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2902 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2903 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2904 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2905 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2906 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2909 /* Use interrupt-safe sleep just in case */
2913 /* For informational purposes only */
2914 if (i >= IXGBE_MAX_SECRX_POLL)
2915 DEBUGOUT("Rx unit being enabled before security "
2916 "path fully disabled. Continuing with init.\n");
2918 return IXGBE_SUCCESS;
2922 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2923 * @hw: pointer to hardware structure
2925 * Enables the receive data path.
2927 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2931 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
2933 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2934 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2935 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2936 IXGBE_WRITE_FLUSH(hw);
2938 return IXGBE_SUCCESS;
2942 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2943 * @hw: pointer to hardware structure
2944 * @regval: register value to write to RXCTRL
2946 * Enables the Rx DMA unit
2948 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2950 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2952 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2954 return IXGBE_SUCCESS;
2958 * ixgbe_blink_led_start_generic - Blink LED based on index.
2959 * @hw: pointer to hardware structure
2960 * @index: led number to blink
2962 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2964 ixgbe_link_speed speed = 0;
2966 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2967 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2969 DEBUGFUNC("ixgbe_blink_led_start_generic");
2972 * Link must be up to auto-blink the LEDs;
2973 * Force it if link is down.
2975 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2978 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2979 autoc_reg |= IXGBE_AUTOC_FLU;
2980 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2981 IXGBE_WRITE_FLUSH(hw);
2985 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2986 led_reg |= IXGBE_LED_BLINK(index);
2987 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2988 IXGBE_WRITE_FLUSH(hw);
2990 return IXGBE_SUCCESS;
2994 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2995 * @hw: pointer to hardware structure
2996 * @index: led number to stop blinking
2998 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3000 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3001 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3003 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3006 autoc_reg &= ~IXGBE_AUTOC_FLU;
3007 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3008 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3010 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3011 led_reg &= ~IXGBE_LED_BLINK(index);
3012 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3013 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3014 IXGBE_WRITE_FLUSH(hw);
3016 return IXGBE_SUCCESS;
3020 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3021 * @hw: pointer to hardware structure
3022 * @san_mac_offset: SAN MAC address offset
3024 * This function will read the EEPROM location for the SAN MAC address
3025 * pointer, and returns the value at that location. This is used in both
3026 * get and set mac_addr routines.
3028 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3029 u16 *san_mac_offset)
3031 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3034 * First read the EEPROM pointer to see if the MAC addresses are
3037 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
3039 return IXGBE_SUCCESS;
3043 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3044 * @hw: pointer to hardware structure
3045 * @san_mac_addr: SAN MAC address
3047 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3048 * per-port, so set_lan_id() must be called before reading the addresses.
3049 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3050 * upon for non-SFP connections, so we must call it here.
3052 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3054 u16 san_mac_data, san_mac_offset;
3057 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3060 * First read the EEPROM pointer to see if the MAC addresses are
3061 * available. If they're not, no point in calling set_lan_id() here.
3063 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3065 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3067 * No addresses available in this EEPROM. It's not an
3068 * error though, so just wipe the local address and return.
3070 for (i = 0; i < 6; i++)
3071 san_mac_addr[i] = 0xFF;
3073 goto san_mac_addr_out;
3076 /* make sure we know which port we need to program */
3077 hw->mac.ops.set_lan_id(hw);
3078 /* apply the port offset to the address offset */
3079 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3080 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3081 for (i = 0; i < 3; i++) {
3082 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
3083 san_mac_addr[i * 2] = (u8)(san_mac_data);
3084 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3089 return IXGBE_SUCCESS;
3093 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3094 * @hw: pointer to hardware structure
3095 * @san_mac_addr: SAN MAC address
3097 * Write a SAN MAC address to the EEPROM.
3099 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3101 s32 status = IXGBE_SUCCESS;
3102 u16 san_mac_data, san_mac_offset;
3105 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3107 /* Look for SAN mac address pointer. If not defined, return */
3108 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3110 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3111 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
3112 goto san_mac_addr_out;
3115 /* Make sure we know which port we need to write */
3116 hw->mac.ops.set_lan_id(hw);
3117 /* Apply the port offset to the address offset */
3118 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3119 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3121 for (i = 0; i < 3; i++) {
3122 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3123 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3124 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3133 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3134 * @hw: pointer to hardware structure
3136 * Read PCIe configuration space, and get the MSI-X vector count from
3137 * the capabilities table.
3139 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3145 switch (hw->mac.type) {
3146 case ixgbe_mac_82598EB:
3147 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3148 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3150 case ixgbe_mac_82599EB:
3151 case ixgbe_mac_X540:
3152 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3153 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3159 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3160 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3161 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3163 /* MSI-X count is zero-based in HW */
3166 if (msix_count > max_msix_count)
3167 msix_count = max_msix_count;
3173 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3174 * @hw: pointer to hardware structure
3175 * @addr: Address to put into receive address register
3176 * @vmdq: VMDq pool to assign
3178 * Puts an ethernet address into a receive address register, or
3179 * finds the rar that it is aleady in; adds to the pool list
3181 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3183 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3184 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3186 u32 rar_low, rar_high;
3187 u32 addr_low, addr_high;
3189 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3191 /* swap bytes for HW little endian */
3192 addr_low = addr[0] | (addr[1] << 8)
3195 addr_high = addr[4] | (addr[5] << 8);
3198 * Either find the mac_id in rar or find the first empty space.
3199 * rar_highwater points to just after the highest currently used
3200 * rar in order to shorten the search. It grows when we add a new
3203 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3204 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3206 if (((IXGBE_RAH_AV & rar_high) == 0)
3207 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3208 first_empty_rar = rar;
3209 } else if ((rar_high & 0xFFFF) == addr_high) {
3210 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3211 if (rar_low == addr_low)
3212 break; /* found it already in the rars */
3216 if (rar < hw->mac.rar_highwater) {
3217 /* already there so just add to the pool bits */
3218 ixgbe_set_vmdq(hw, rar, vmdq);
3219 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3220 /* stick it into first empty RAR slot we found */
3221 rar = first_empty_rar;
3222 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3223 } else if (rar == hw->mac.rar_highwater) {
3224 /* add it to the top of the list and inc the highwater mark */
3225 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3226 hw->mac.rar_highwater++;
3227 } else if (rar >= hw->mac.num_rar_entries) {
3228 return IXGBE_ERR_INVALID_MAC_ADDR;
3232 * If we found rar[0], make sure the default pool bit (we use pool 0)
3233 * remains cleared to be sure default pool packets will get delivered
3236 ixgbe_clear_vmdq(hw, rar, 0);
3242 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3243 * @hw: pointer to hardware struct
3244 * @rar: receive address register index to disassociate
3245 * @vmdq: VMDq pool index to remove from the rar
3247 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3249 u32 mpsar_lo, mpsar_hi;
3250 u32 rar_entries = hw->mac.num_rar_entries;
3252 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3254 /* Make sure we are using a valid rar index range */
3255 if (rar >= rar_entries) {
3256 DEBUGOUT1("RAR index %d is out of range.\n", rar);
3257 return IXGBE_ERR_INVALID_ARGUMENT;
3260 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3261 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3263 if (!mpsar_lo && !mpsar_hi)
3266 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3268 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3272 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3275 } else if (vmdq < 32) {
3276 mpsar_lo &= ~(1 << vmdq);
3277 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3279 mpsar_hi &= ~(1 << (vmdq - 32));
3280 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3283 /* was that the last pool using this rar? */
3284 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3285 hw->mac.ops.clear_rar(hw, rar);
3287 return IXGBE_SUCCESS;
3291 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3292 * @hw: pointer to hardware struct
3293 * @rar: receive address register index to associate with a VMDq index
3294 * @vmdq: VMDq pool index
3296 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3299 u32 rar_entries = hw->mac.num_rar_entries;
3301 DEBUGFUNC("ixgbe_set_vmdq_generic");
3303 /* Make sure we are using a valid rar index range */
3304 if (rar >= rar_entries) {
3305 DEBUGOUT1("RAR index %d is out of range.\n", rar);
3306 return IXGBE_ERR_INVALID_ARGUMENT;
3310 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3312 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3314 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3315 mpsar |= 1 << (vmdq - 32);
3316 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3318 return IXGBE_SUCCESS;
3322 * This function should only be involved in the IOV mode.
3323 * In IOV mode, Default pool is next pool after the number of
3324 * VFs advertized and not 0.
3325 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3327 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3328 * @hw: pointer to hardware struct
3329 * @vmdq: VMDq pool index
3331 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3333 u32 rar = hw->mac.san_mac_rar_index;
3335 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3338 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3339 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3341 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3342 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3345 return IXGBE_SUCCESS;
3349 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3350 * @hw: pointer to hardware structure
3352 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3356 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3357 DEBUGOUT(" Clearing UTA\n");
3359 for (i = 0; i < 128; i++)
3360 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3362 return IXGBE_SUCCESS;
3366 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3367 * @hw: pointer to hardware structure
3368 * @vlan: VLAN id to write to VLAN filter
3370 * return the VLVF index where this VLAN id should be placed
3373 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3376 u32 first_empty_slot = 0;
3379 /* short cut the special case */
3384 * Search for the vlan id in the VLVF entries. Save off the first empty
3385 * slot found along the way
3387 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3388 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3389 if (!bits && !(first_empty_slot))
3390 first_empty_slot = regindex;
3391 else if ((bits & 0x0FFF) == vlan)
3396 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3397 * in the VLVF. Else use the first empty VLVF register for this
3400 if (regindex >= IXGBE_VLVF_ENTRIES) {
3401 if (first_empty_slot)
3402 regindex = first_empty_slot;
3404 DEBUGOUT("No space in VLVF.\n");
3405 regindex = IXGBE_ERR_NO_SPACE;
3413 * ixgbe_set_vfta_generic - Set VLAN filter table
3414 * @hw: pointer to hardware structure
3415 * @vlan: VLAN id to write to VLAN filter
3416 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3417 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3419 * Turn on/off specified VLAN in the VLAN filter table.
3421 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3428 s32 ret_val = IXGBE_SUCCESS;
3429 bool vfta_changed = FALSE;
3431 DEBUGFUNC("ixgbe_set_vfta_generic");
3434 return IXGBE_ERR_PARAM;
3437 * this is a 2 part operation - first the VFTA, then the
3438 * VLVF and VLVFB if VT Mode is set
3439 * We don't write the VFTA until we know the VLVF part succeeded.
3443 * The VFTA is a bitstring made up of 128 32-bit registers
3444 * that enable the particular VLAN id, much like the MTA:
3445 * bits[11-5]: which register
3446 * bits[4-0]: which bit in the register
3448 regindex = (vlan >> 5) & 0x7F;
3449 bitindex = vlan & 0x1F;
3450 targetbit = (1 << bitindex);
3451 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3454 if (!(vfta & targetbit)) {
3456 vfta_changed = TRUE;
3459 if ((vfta & targetbit)) {
3461 vfta_changed = TRUE;
3466 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3468 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3470 if (ret_val != IXGBE_SUCCESS)
3474 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3476 return IXGBE_SUCCESS;
3480 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3481 * @hw: pointer to hardware structure
3482 * @vlan: VLAN id to write to VLAN filter
3483 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3484 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3485 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3488 * Turn on/off specified bit in VLVF table.
3490 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3491 bool vlan_on, bool *vfta_changed)
3495 DEBUGFUNC("ixgbe_set_vlvf_generic");
3498 return IXGBE_ERR_PARAM;
3500 /* If VT Mode is set
3502 * make sure the vlan is in VLVF
3503 * set the vind bit in the matching VLVFB
3505 * clear the pool bit and possibly the vind
3507 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3508 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3512 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3517 /* set the pool bit */
3519 bits = IXGBE_READ_REG(hw,
3520 IXGBE_VLVFB(vlvf_index * 2));
3521 bits |= (1 << vind);
3523 IXGBE_VLVFB(vlvf_index * 2),
3526 bits = IXGBE_READ_REG(hw,
3527 IXGBE_VLVFB((vlvf_index * 2) + 1));
3528 bits |= (1 << (vind - 32));
3530 IXGBE_VLVFB((vlvf_index * 2) + 1),
3534 /* clear the pool bit */
3536 bits = IXGBE_READ_REG(hw,
3537 IXGBE_VLVFB(vlvf_index * 2));
3538 bits &= ~(1 << vind);
3540 IXGBE_VLVFB(vlvf_index * 2),
3542 bits |= IXGBE_READ_REG(hw,
3543 IXGBE_VLVFB((vlvf_index * 2) + 1));
3545 bits = IXGBE_READ_REG(hw,
3546 IXGBE_VLVFB((vlvf_index * 2) + 1));
3547 bits &= ~(1 << (vind - 32));
3549 IXGBE_VLVFB((vlvf_index * 2) + 1),
3551 bits |= IXGBE_READ_REG(hw,
3552 IXGBE_VLVFB(vlvf_index * 2));
3557 * If there are still bits set in the VLVFB registers
3558 * for the VLAN ID indicated we need to see if the
3559 * caller is requesting that we clear the VFTA entry bit.
3560 * If the caller has requested that we clear the VFTA
3561 * entry bit but there are still pools/VFs using this VLAN
3562 * ID entry then ignore the request. We're not worried
3563 * about the case where we're turning the VFTA VLAN ID
3564 * entry bit on, only when requested to turn it off as
3565 * there may be multiple pools and/or VFs using the
3566 * VLAN ID entry. In that case we cannot clear the
3567 * VFTA bit until all pools/VFs using that VLAN ID have also
3568 * been cleared. This will be indicated by "bits" being
3572 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3573 (IXGBE_VLVF_VIEN | vlan));
3574 if ((!vlan_on) && (vfta_changed != NULL)) {
3575 /* someone wants to clear the vfta entry
3576 * but some pools/VFs are still using it.
3578 *vfta_changed = FALSE;
3581 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3584 return IXGBE_SUCCESS;
3588 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3589 * @hw: pointer to hardware structure
3591 * Clears the VLAN filer table, and the VMDq index associated with the filter
3593 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3597 DEBUGFUNC("ixgbe_clear_vfta_generic");
3599 for (offset = 0; offset < hw->mac.vft_size; offset++)
3600 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3602 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3603 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3604 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3605 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3608 return IXGBE_SUCCESS;
3612 * ixgbe_check_mac_link_generic - Determine link and speed status
3613 * @hw: pointer to hardware structure
3614 * @speed: pointer to link speed
3615 * @link_up: TRUE when link is up
3616 * @link_up_wait_to_complete: bool used to wait for link up or not
3618 * Reads the links register to determine if link is up and the current speed
3620 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3621 bool *link_up, bool link_up_wait_to_complete)
3623 u32 links_reg, links_orig;
3626 DEBUGFUNC("ixgbe_check_mac_link_generic");
3628 /* clear the old state */
3629 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3631 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3633 if (links_orig != links_reg) {
3634 DEBUGOUT2("LINKS changed from %08X to %08X\n",
3635 links_orig, links_reg);
3638 if (link_up_wait_to_complete) {
3639 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3640 if (links_reg & IXGBE_LINKS_UP) {
3647 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3650 if (links_reg & IXGBE_LINKS_UP)
3656 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3657 IXGBE_LINKS_SPEED_10G_82599)
3658 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3659 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3660 IXGBE_LINKS_SPEED_1G_82599)
3661 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3662 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3663 IXGBE_LINKS_SPEED_100_82599)
3664 *speed = IXGBE_LINK_SPEED_100_FULL;
3666 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3668 return IXGBE_SUCCESS;
3672 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3674 * @hw: pointer to hardware structure
3675 * @wwnn_prefix: the alternative WWNN prefix
3676 * @wwpn_prefix: the alternative WWPN prefix
3678 * This function will read the EEPROM from the alternative SAN MAC address
3679 * block to check the support for the alternative WWNN/WWPN prefix support.
3681 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3685 u16 alt_san_mac_blk_offset;
3687 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3689 /* clear output first */
3690 *wwnn_prefix = 0xFFFF;
3691 *wwpn_prefix = 0xFFFF;
3693 /* check if alternative SAN MAC is supported */
3694 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3695 &alt_san_mac_blk_offset);
3697 if ((alt_san_mac_blk_offset == 0) ||
3698 (alt_san_mac_blk_offset == 0xFFFF))
3699 goto wwn_prefix_out;
3701 /* check capability in alternative san mac address block */
3702 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3703 hw->eeprom.ops.read(hw, offset, &caps);
3704 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3705 goto wwn_prefix_out;
3707 /* get the corresponding prefix for WWNN/WWPN */
3708 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3709 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3711 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3712 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3715 return IXGBE_SUCCESS;
3719 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3720 * @hw: pointer to hardware structure
3721 * @bs: the fcoe boot status
3723 * This function will read the FCOE boot status from the iSCSI FCOE block
3725 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3727 u16 offset, caps, flags;
3730 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
3732 /* clear output first */
3733 *bs = ixgbe_fcoe_bootstatus_unavailable;
3735 /* check if FCOE IBA block is present */
3736 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3737 status = hw->eeprom.ops.read(hw, offset, &caps);
3738 if (status != IXGBE_SUCCESS)
3741 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3744 /* check if iSCSI FCOE block is populated */
3745 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3746 if (status != IXGBE_SUCCESS)
3749 if ((offset == 0) || (offset == 0xFFFF))
3752 /* read fcoe flags in iSCSI FCOE block */
3753 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3754 status = hw->eeprom.ops.read(hw, offset, &flags);
3755 if (status != IXGBE_SUCCESS)
3758 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3759 *bs = ixgbe_fcoe_bootstatus_enabled;
3761 *bs = ixgbe_fcoe_bootstatus_disabled;
3768 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3769 * @hw: pointer to hardware structure
3770 * @enable: enable or disable switch for anti-spoofing
3771 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3774 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3777 int pf_target_reg = pf >> 3;
3778 int pf_target_shift = pf % 8;
3781 if (hw->mac.type == ixgbe_mac_82598EB)
3785 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3788 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3789 * MAC anti-spoof enables in each register array element.
3791 for (j = 0; j < pf_target_reg; j++)
3792 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3795 * The PF should be allowed to spoof so that it can support
3796 * emulation mode NICs. Do not set the bits assigned to the PF
3798 pfvfspoof &= (1 << pf_target_shift) - 1;
3799 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3802 * Remaining pools belong to the PF so they do not need to have
3803 * anti-spoofing enabled.
3805 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3806 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3810 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3811 * @hw: pointer to hardware structure
3812 * @enable: enable or disable switch for VLAN anti-spoofing
3813 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3816 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3818 int vf_target_reg = vf >> 3;
3819 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3822 if (hw->mac.type == ixgbe_mac_82598EB)
3825 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3827 pfvfspoof |= (1 << vf_target_shift);
3829 pfvfspoof &= ~(1 << vf_target_shift);
3830 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3834 * ixgbe_get_device_caps_generic - Get additional device capabilities
3835 * @hw: pointer to hardware structure
3836 * @device_caps: the EEPROM word with the extra device capabilities
3838 * This function will read the EEPROM location for the device capabilities,
3839 * and return the word through device_caps.
3841 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3843 DEBUGFUNC("ixgbe_get_device_caps_generic");
3845 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3847 return IXGBE_SUCCESS;
3851 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
3852 * @hw: pointer to hardware structure
3855 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
3860 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
3862 /* Enable relaxed ordering */
3863 for (i = 0; i < hw->mac.max_tx_queues; i++) {
3864 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
3865 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3866 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
3869 for (i = 0; i < hw->mac.max_rx_queues; i++) {
3870 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
3871 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
3872 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
3873 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
3879 * ixgbe_calculate_checksum - Calculate checksum for buffer
3880 * @buffer: pointer to EEPROM
3881 * @length: size of EEPROM to calculate a checksum for
3882 * Calculates the checksum for some buffer on a specified length. The
3883 * checksum calculated is returned.
3885 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3890 DEBUGFUNC("ixgbe_calculate_checksum");
3895 for (i = 0; i < length; i++)
3898 return (u8) (0 - sum);
3902 * ixgbe_host_interface_command - Issue command to manageability block
3903 * @hw: pointer to the HW structure
3904 * @buffer: contains the command to write and where the return status will
3906 * @length: length of buffer, must be multiple of 4 bytes
3908 * Communicates with the manageability block. On success return IXGBE_SUCCESS
3909 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3911 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3915 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3916 u8 buf_len, dword_len;
3918 s32 ret_val = IXGBE_SUCCESS;
3920 DEBUGFUNC("ixgbe_host_interface_command");
3922 if (length == 0 || length & 0x3 ||
3923 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3924 DEBUGOUT("Buffer length failure.\n");
3925 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3929 /* Check that the host interface is enabled. */
3930 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3931 if ((hicr & IXGBE_HICR_EN) == 0) {
3932 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
3933 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3937 /* Calculate length in DWORDs */
3938 dword_len = length >> 2;
3941 * The device driver writes the relevant command block
3942 * into the ram area.
3944 for (i = 0; i < dword_len; i++)
3945 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3946 i, IXGBE_CPU_TO_LE32(buffer[i]));
3948 /* Setting this bit tells the ARC that a new command is pending. */
3949 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3951 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3952 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3953 if (!(hicr & IXGBE_HICR_C))
3958 /* Check command successful completion. */
3959 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3960 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3961 DEBUGOUT("Command has failed with no status valid.\n");
3962 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3966 /* Calculate length in DWORDs */
3967 dword_len = hdr_size >> 2;
3969 /* first pull in the header so we know the buffer length */
3970 for (bi = 0; bi < dword_len; bi++) {
3971 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3972 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3975 /* If there is any thing in data position pull it in */
3976 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3980 if (length < (buf_len + hdr_size)) {
3981 DEBUGOUT("Buffer not large enough for reply message.\n");
3982 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3986 /* Calculate length in DWORDs, add 3 for odd lengths */
3987 dword_len = (buf_len + 3) >> 2;
3989 /* Pull in the rest of the buffer (bi is where we left off)*/
3990 for (; bi <= dword_len; bi++) {
3991 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3992 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4000 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4001 * @hw: pointer to the HW structure
4002 * @maj: driver version major number
4003 * @min: driver version minor number
4004 * @build: driver version build number
4005 * @sub: driver version sub build number
4007 * Sends driver version number to firmware through the manageability
4008 * block. On success return IXGBE_SUCCESS
4009 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4010 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4012 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4015 struct ixgbe_hic_drv_info fw_cmd;
4017 s32 ret_val = IXGBE_SUCCESS;
4019 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4021 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4023 ret_val = IXGBE_ERR_SWFW_SYNC;
4027 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4028 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4029 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4030 fw_cmd.port_num = (u8)hw->bus.func;
4031 fw_cmd.ver_maj = maj;
4032 fw_cmd.ver_min = min;
4033 fw_cmd.ver_build = build;
4034 fw_cmd.ver_sub = sub;
4035 fw_cmd.hdr.checksum = 0;
4036 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4037 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4041 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4042 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4044 if (ret_val != IXGBE_SUCCESS)
4047 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4048 FW_CEM_RESP_STATUS_SUCCESS)
4049 ret_val = IXGBE_SUCCESS;
4051 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4056 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4062 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4063 * @hw: pointer to hardware structure
4064 * @num_pb: number of packet buffers to allocate
4065 * @headroom: reserve n KB of headroom
4066 * @strategy: packet buffer allocation strategy
4068 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4071 u32 pbsize = hw->mac.rx_pb_size;
4073 u32 rxpktsize, txpktsize, txpbthresh;
4075 /* Reserve headroom */
4081 /* Divide remaining packet buffer space amongst the number of packet
4082 * buffers requested using supplied strategy.
4085 case PBA_STRATEGY_WEIGHTED:
4086 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4087 * buffer with 5/8 of the packet buffer space.
4089 rxpktsize = (pbsize * 5) / (num_pb * 4);
4090 pbsize -= rxpktsize * (num_pb / 2);
4091 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4092 for (; i < (num_pb / 2); i++)
4093 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4094 /* Fall through to configure remaining packet buffers */
4095 case PBA_STRATEGY_EQUAL:
4096 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4097 for (; i < num_pb; i++)
4098 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4104 /* Only support an equally distributed Tx packet buffer strategy. */
4105 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4106 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4107 for (i = 0; i < num_pb; i++) {
4108 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4109 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4112 /* Clear unused TCs, if any, to zero buffer size*/
4113 for (; i < IXGBE_MAX_PB; i++) {
4114 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4115 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4116 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4121 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4122 * @hw: pointer to the hardware structure
4124 * The 82599 and x540 MACs can experience issues if TX work is still pending
4125 * when a reset occurs. This function prevents this by flushing the PCIe
4126 * buffers on the system.
4128 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4130 u32 gcr_ext, hlreg0;
4133 * If double reset is not requested then all transactions should
4134 * already be clear and as such there is no work to do
4136 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4140 * Set loopback enable to prevent any transmits from being sent
4141 * should the link come up. This assumes that the RXCTRL.RXEN bit
4142 * has already been cleared.
4144 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4145 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4147 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4148 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4149 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4150 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4152 /* Flush all writes and allow 20usec for all transactions to clear */
4153 IXGBE_WRITE_FLUSH(hw);
4156 /* restore previous register values */
4157 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4158 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);