1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_api.h"
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
51 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
54 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
55 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
56 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
57 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
58 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
59 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
61 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
83 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.write = &ixgbe_write_eeprom_generic;
85 eeprom->ops.validate_checksum =
86 &ixgbe_validate_eeprom_checksum_generic;
87 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
88 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
91 mac->ops.init_hw = &ixgbe_init_hw_generic;
92 mac->ops.reset_hw = NULL;
93 mac->ops.start_hw = &ixgbe_start_hw_generic;
94 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
95 mac->ops.get_media_type = NULL;
96 mac->ops.get_supported_physical_layer = NULL;
97 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
98 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
99 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
100 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
101 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
102 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
103 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
106 mac->ops.led_on = &ixgbe_led_on_generic;
107 mac->ops.led_off = &ixgbe_led_off_generic;
108 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
109 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
111 /* RAR, Multicast, VLAN */
112 mac->ops.set_rar = &ixgbe_set_rar_generic;
113 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
114 mac->ops.insert_mac_addr = NULL;
115 mac->ops.set_vmdq = NULL;
116 mac->ops.clear_vmdq = NULL;
117 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
118 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
119 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
120 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
121 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
122 mac->ops.clear_vfta = NULL;
123 mac->ops.set_vfta = NULL;
124 mac->ops.init_uta_tables = NULL;
127 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
130 mac->ops.get_link_capabilities = NULL;
131 mac->ops.setup_link = NULL;
132 mac->ops.check_link = NULL;
134 return IXGBE_SUCCESS;
138 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
139 * @hw: pointer to hardware structure
141 * Starts the hardware by filling the bus info structure and media type, clears
142 * all on chip counters, initializes receive address registers, multicast
143 * table, VLAN filter table, calls routine to set up link and flow control
144 * settings, and leaves transmit and receive units disabled and uninitialized
146 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
150 DEBUGFUNC("ixgbe_start_hw_generic");
152 /* Set the media type */
153 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
155 /* PHY ops initialization must be done in reset_hw() */
157 /* Clear the VLAN filter table */
158 hw->mac.ops.clear_vfta(hw);
160 /* Clear statistics registers */
161 hw->mac.ops.clear_hw_cntrs(hw);
163 /* Set No Snoop Disable */
164 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
165 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
166 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
167 IXGBE_WRITE_FLUSH(hw);
169 /* Setup flow control */
170 ixgbe_setup_fc(hw, 0);
172 /* Clear adapter stopped flag */
173 hw->adapter_stopped = FALSE;
175 return IXGBE_SUCCESS;
179 * ixgbe_start_hw_gen2 - Init sequence for common device family
180 * @hw: pointer to hw structure
182 * Performs the init sequence common to the second generation
184 * Devices in the second generation:
187 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
192 /* Clear the rate limiters */
193 for (i = 0; i < hw->mac.max_tx_queues; i++) {
194 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
195 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
197 IXGBE_WRITE_FLUSH(hw);
199 /* Disable relaxed ordering */
200 for (i = 0; i < hw->mac.max_tx_queues; i++) {
201 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
202 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
203 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
206 for (i = 0; i < hw->mac.max_rx_queues; i++) {
207 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
208 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
209 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
210 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
213 return IXGBE_SUCCESS;
217 * ixgbe_init_hw_generic - Generic hardware initialization
218 * @hw: pointer to hardware structure
220 * Initialize the hardware by resetting the hardware, filling the bus info
221 * structure and media type, clears all on chip counters, initializes receive
222 * address registers, multicast table, VLAN filter table, calls routine to set
223 * up link and flow control settings, and leaves transmit and receive units
224 * disabled and uninitialized
226 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
230 DEBUGFUNC("ixgbe_init_hw_generic");
232 /* Reset the hardware */
233 status = hw->mac.ops.reset_hw(hw);
235 if (status == IXGBE_SUCCESS) {
237 status = hw->mac.ops.start_hw(hw);
244 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
245 * @hw: pointer to hardware structure
247 * Clears all hardware statistics counters by reading them from the hardware
248 * Statistics counters are clear on read.
250 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
254 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
256 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
257 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
258 IXGBE_READ_REG(hw, IXGBE_ERRBC);
259 IXGBE_READ_REG(hw, IXGBE_MSPDC);
260 for (i = 0; i < 8; i++)
261 IXGBE_READ_REG(hw, IXGBE_MPC(i));
263 IXGBE_READ_REG(hw, IXGBE_MLFC);
264 IXGBE_READ_REG(hw, IXGBE_MRFC);
265 IXGBE_READ_REG(hw, IXGBE_RLEC);
266 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
267 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
268 if (hw->mac.type >= ixgbe_mac_82599EB) {
269 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
270 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
272 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
273 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
276 for (i = 0; i < 8; i++) {
277 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
278 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
279 if (hw->mac.type >= ixgbe_mac_82599EB) {
280 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
281 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
283 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
284 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
287 if (hw->mac.type >= ixgbe_mac_82599EB)
288 for (i = 0; i < 8; i++)
289 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
290 IXGBE_READ_REG(hw, IXGBE_PRC64);
291 IXGBE_READ_REG(hw, IXGBE_PRC127);
292 IXGBE_READ_REG(hw, IXGBE_PRC255);
293 IXGBE_READ_REG(hw, IXGBE_PRC511);
294 IXGBE_READ_REG(hw, IXGBE_PRC1023);
295 IXGBE_READ_REG(hw, IXGBE_PRC1522);
296 IXGBE_READ_REG(hw, IXGBE_GPRC);
297 IXGBE_READ_REG(hw, IXGBE_BPRC);
298 IXGBE_READ_REG(hw, IXGBE_MPRC);
299 IXGBE_READ_REG(hw, IXGBE_GPTC);
300 IXGBE_READ_REG(hw, IXGBE_GORCL);
301 IXGBE_READ_REG(hw, IXGBE_GORCH);
302 IXGBE_READ_REG(hw, IXGBE_GOTCL);
303 IXGBE_READ_REG(hw, IXGBE_GOTCH);
304 for (i = 0; i < 8; i++)
305 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
306 IXGBE_READ_REG(hw, IXGBE_RUC);
307 IXGBE_READ_REG(hw, IXGBE_RFC);
308 IXGBE_READ_REG(hw, IXGBE_ROC);
309 IXGBE_READ_REG(hw, IXGBE_RJC);
310 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
311 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
312 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
313 IXGBE_READ_REG(hw, IXGBE_TORL);
314 IXGBE_READ_REG(hw, IXGBE_TORH);
315 IXGBE_READ_REG(hw, IXGBE_TPR);
316 IXGBE_READ_REG(hw, IXGBE_TPT);
317 IXGBE_READ_REG(hw, IXGBE_PTC64);
318 IXGBE_READ_REG(hw, IXGBE_PTC127);
319 IXGBE_READ_REG(hw, IXGBE_PTC255);
320 IXGBE_READ_REG(hw, IXGBE_PTC511);
321 IXGBE_READ_REG(hw, IXGBE_PTC1023);
322 IXGBE_READ_REG(hw, IXGBE_PTC1522);
323 IXGBE_READ_REG(hw, IXGBE_MPTC);
324 IXGBE_READ_REG(hw, IXGBE_BPTC);
325 for (i = 0; i < 16; i++) {
326 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
327 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
328 if (hw->mac.type >= ixgbe_mac_82599EB) {
329 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
330 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
331 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
332 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
333 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
335 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
336 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
340 return IXGBE_SUCCESS;
344 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
345 * @hw: pointer to hardware structure
346 * @pba_num: stores the part number string from the EEPROM
347 * @pba_num_size: part number string buffer length
349 * Reads the part number string from the EEPROM.
351 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
360 DEBUGFUNC("ixgbe_read_pba_string_generic");
362 if (pba_num == NULL) {
363 DEBUGOUT("PBA string buffer was null\n");
364 return IXGBE_ERR_INVALID_ARGUMENT;
367 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
369 DEBUGOUT("NVM Read Error\n");
373 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
375 DEBUGOUT("NVM Read Error\n");
380 * if data is not ptr guard the PBA must be in legacy format which
381 * means pba_ptr is actually our second data word for the PBA number
382 * and we can decode it into an ascii string
384 if (data != IXGBE_PBANUM_PTR_GUARD) {
385 DEBUGOUT("NVM PBA number is not stored as string\n");
387 /* we will need 11 characters to store the PBA */
388 if (pba_num_size < 11) {
389 DEBUGOUT("PBA string buffer too small\n");
390 return IXGBE_ERR_NO_SPACE;
393 /* extract hex string from data and pba_ptr */
394 pba_num[0] = (data >> 12) & 0xF;
395 pba_num[1] = (data >> 8) & 0xF;
396 pba_num[2] = (data >> 4) & 0xF;
397 pba_num[3] = data & 0xF;
398 pba_num[4] = (pba_ptr >> 12) & 0xF;
399 pba_num[5] = (pba_ptr >> 8) & 0xF;
402 pba_num[8] = (pba_ptr >> 4) & 0xF;
403 pba_num[9] = pba_ptr & 0xF;
405 /* put a null character on the end of our string */
408 /* switch all the data but the '-' to hex char */
409 for (offset = 0; offset < 10; offset++) {
410 if (pba_num[offset] < 0xA)
411 pba_num[offset] += '0';
412 else if (pba_num[offset] < 0x10)
413 pba_num[offset] += 'A' - 0xA;
416 return IXGBE_SUCCESS;
419 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
421 DEBUGOUT("NVM Read Error\n");
425 if (length == 0xFFFF || length == 0) {
426 DEBUGOUT("NVM PBA number section invalid length\n");
427 return IXGBE_ERR_PBA_SECTION;
430 /* check if pba_num buffer is big enough */
431 if (pba_num_size < (((u32)length * 2) - 1)) {
432 DEBUGOUT("PBA string buffer too small\n");
433 return IXGBE_ERR_NO_SPACE;
436 /* trim pba length from start of string */
440 for (offset = 0; offset < length; offset++) {
441 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
443 DEBUGOUT("NVM Read Error\n");
446 pba_num[offset * 2] = (u8)(data >> 8);
447 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
449 pba_num[offset * 2] = '\0';
451 return IXGBE_SUCCESS;
455 * ixgbe_read_pba_length_generic - Reads part number length from EEPROM
456 * @hw: pointer to hardware structure
457 * @pba_num_size: part number string buffer length
459 * Reads the part number length from the EEPROM.
460 * Returns expected buffer size in pba_num_size
462 s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size)
469 DEBUGFUNC("ixgbe_read_pba_length_generic");
471 if (pba_num_size == NULL) {
472 DEBUGOUT("PBA buffer size was null\n");
473 return IXGBE_ERR_INVALID_ARGUMENT;
476 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
478 DEBUGOUT("NVM Read Error\n");
482 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
484 DEBUGOUT("NVM Read Error\n");
488 /* if data is not ptr guard the PBA must be in legacy format */
489 if (data != IXGBE_PBANUM_PTR_GUARD) {
491 return IXGBE_SUCCESS;
494 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
496 DEBUGOUT("NVM Read Error\n");
500 if (length == 0xFFFF || length == 0) {
501 DEBUGOUT("NVM PBA number section invalid length\n");
502 return IXGBE_ERR_PBA_SECTION;
506 * Convert from length in u16 values to u8 chars, add 1 for NULL,
507 * and subtract 2 because length field is included in length.
509 *pba_num_size = ((u32)length * 2) - 1;
511 return IXGBE_SUCCESS;
515 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
516 * @hw: pointer to hardware structure
517 * @pba_num: stores the part number from the EEPROM
519 * Reads the part number from the EEPROM.
521 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
526 DEBUGFUNC("ixgbe_read_pba_num_generic");
528 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
530 DEBUGOUT("NVM Read Error\n");
532 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
533 DEBUGOUT("NVM Not supported\n");
534 return IXGBE_NOT_IMPLEMENTED;
536 *pba_num = (u32)(data << 16);
538 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
540 DEBUGOUT("NVM Read Error\n");
545 return IXGBE_SUCCESS;
549 * ixgbe_get_mac_addr_generic - Generic get MAC address
550 * @hw: pointer to hardware structure
551 * @mac_addr: Adapter MAC address
553 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
554 * A reset of the adapter must be performed prior to calling this function
555 * in order for the MAC address to have been loaded from the EEPROM into RAR0
557 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
563 DEBUGFUNC("ixgbe_get_mac_addr_generic");
565 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
566 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
568 for (i = 0; i < 4; i++)
569 mac_addr[i] = (u8)(rar_low >> (i*8));
571 for (i = 0; i < 2; i++)
572 mac_addr[i+4] = (u8)(rar_high >> (i*8));
574 return IXGBE_SUCCESS;
578 * ixgbe_get_bus_info_generic - Generic set PCI bus info
579 * @hw: pointer to hardware structure
581 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
583 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
585 struct ixgbe_mac_info *mac = &hw->mac;
588 DEBUGFUNC("ixgbe_get_bus_info_generic");
590 hw->bus.type = ixgbe_bus_type_pci_express;
592 /* Get the negotiated link width and speed from PCI config space */
593 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
595 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
596 case IXGBE_PCI_LINK_WIDTH_1:
597 hw->bus.width = ixgbe_bus_width_pcie_x1;
599 case IXGBE_PCI_LINK_WIDTH_2:
600 hw->bus.width = ixgbe_bus_width_pcie_x2;
602 case IXGBE_PCI_LINK_WIDTH_4:
603 hw->bus.width = ixgbe_bus_width_pcie_x4;
605 case IXGBE_PCI_LINK_WIDTH_8:
606 hw->bus.width = ixgbe_bus_width_pcie_x8;
609 hw->bus.width = ixgbe_bus_width_unknown;
613 switch (link_status & IXGBE_PCI_LINK_SPEED) {
614 case IXGBE_PCI_LINK_SPEED_2500:
615 hw->bus.speed = ixgbe_bus_speed_2500;
617 case IXGBE_PCI_LINK_SPEED_5000:
618 hw->bus.speed = ixgbe_bus_speed_5000;
621 hw->bus.speed = ixgbe_bus_speed_unknown;
625 mac->ops.set_lan_id(hw);
627 return IXGBE_SUCCESS;
631 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
632 * @hw: pointer to the HW structure
634 * Determines the LAN function id by reading memory-mapped registers
635 * and swaps the port value if requested.
637 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
639 struct ixgbe_bus_info *bus = &hw->bus;
642 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
644 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
645 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
646 bus->lan_id = bus->func;
648 /* check for a port swap */
649 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
650 if (reg & IXGBE_FACTPS_LFS)
655 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
656 * @hw: pointer to hardware structure
658 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
659 * disables transmit and receive units. The adapter_stopped flag is used by
660 * the shared code and drivers to determine if the adapter is in a stopped
661 * state and should not touch the hardware.
663 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
665 u32 number_of_queues;
669 DEBUGFUNC("ixgbe_stop_adapter_generic");
672 * Set the adapter_stopped flag so other driver functions stop touching
675 hw->adapter_stopped = TRUE;
677 /* Disable the receive unit */
678 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
679 reg_val &= ~(IXGBE_RXCTRL_RXEN);
680 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
681 IXGBE_WRITE_FLUSH(hw);
684 /* Clear interrupt mask to stop from interrupts being generated */
685 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
687 /* Clear any pending interrupts */
688 IXGBE_READ_REG(hw, IXGBE_EICR);
690 /* Disable the transmit unit. Each queue must be disabled. */
691 number_of_queues = hw->mac.max_tx_queues;
692 for (i = 0; i < number_of_queues; i++) {
693 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
694 if (reg_val & IXGBE_TXDCTL_ENABLE) {
695 reg_val &= ~IXGBE_TXDCTL_ENABLE;
696 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
701 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
702 * access and verify no pending requests
704 ixgbe_disable_pcie_master(hw);
706 return IXGBE_SUCCESS;
710 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
711 * @hw: pointer to hardware structure
712 * @index: led number to turn on
714 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
716 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
718 DEBUGFUNC("ixgbe_led_on_generic");
720 /* To turn on the LED, set mode to ON. */
721 led_reg &= ~IXGBE_LED_MODE_MASK(index);
722 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
723 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
724 IXGBE_WRITE_FLUSH(hw);
726 return IXGBE_SUCCESS;
730 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
731 * @hw: pointer to hardware structure
732 * @index: led number to turn off
734 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
736 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
738 DEBUGFUNC("ixgbe_led_off_generic");
740 /* To turn off the LED, set mode to OFF. */
741 led_reg &= ~IXGBE_LED_MODE_MASK(index);
742 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
743 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
744 IXGBE_WRITE_FLUSH(hw);
746 return IXGBE_SUCCESS;
750 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
751 * @hw: pointer to hardware structure
753 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
754 * ixgbe_hw struct in order to set up EEPROM access.
756 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
758 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
762 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
764 if (eeprom->type == ixgbe_eeprom_uninitialized) {
765 eeprom->type = ixgbe_eeprom_none;
766 /* Set default semaphore delay to 10ms which is a well
768 eeprom->semaphore_delay = 10;
771 * Check for EEPROM present first.
772 * If not present leave as none
774 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
775 if (eec & IXGBE_EEC_PRES) {
776 eeprom->type = ixgbe_eeprom_spi;
779 * SPI EEPROM is assumed here. This code would need to
780 * change if a future EEPROM is not SPI.
782 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
783 IXGBE_EEC_SIZE_SHIFT);
784 eeprom->word_size = 1 << (eeprom_size +
785 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
788 if (eec & IXGBE_EEC_ADDR_SIZE)
789 eeprom->address_bits = 16;
791 eeprom->address_bits = 8;
792 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
793 "%d\n", eeprom->type, eeprom->word_size,
794 eeprom->address_bits);
797 return IXGBE_SUCCESS;
801 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
802 * @hw: pointer to hardware structure
803 * @offset: offset within the EEPROM to be written to
804 * @data: 16 bit word to be written to the EEPROM
806 * If ixgbe_eeprom_update_checksum is not called after this function, the
807 * EEPROM will most likely contain an invalid checksum.
809 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
812 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
814 DEBUGFUNC("ixgbe_write_eeprom_generic");
816 hw->eeprom.ops.init_params(hw);
818 if (offset >= hw->eeprom.word_size) {
819 status = IXGBE_ERR_EEPROM;
823 /* Prepare the EEPROM for writing */
824 status = ixgbe_acquire_eeprom(hw);
826 if (status == IXGBE_SUCCESS) {
827 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
828 ixgbe_release_eeprom(hw);
829 status = IXGBE_ERR_EEPROM;
833 if (status == IXGBE_SUCCESS) {
834 ixgbe_standby_eeprom(hw);
836 /* Send the WRITE ENABLE command (8 bit opcode ) */
837 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
838 IXGBE_EEPROM_OPCODE_BITS);
840 ixgbe_standby_eeprom(hw);
843 * Some SPI eeproms use the 8th address bit embedded in the
846 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
847 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
849 /* Send the Write command (8-bit opcode + addr) */
850 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
851 IXGBE_EEPROM_OPCODE_BITS);
852 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
853 hw->eeprom.address_bits);
856 data = (data >> 8) | (data << 8);
857 ixgbe_shift_out_eeprom_bits(hw, data, 16);
858 ixgbe_standby_eeprom(hw);
860 /* Done with writing - release the EEPROM */
861 ixgbe_release_eeprom(hw);
869 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
870 * @hw: pointer to hardware structure
871 * @offset: offset within the EEPROM to be read
872 * @data: read 16 bit value from EEPROM
874 * Reads 16 bit value from EEPROM through bit-bang method
876 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
881 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
883 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
885 hw->eeprom.ops.init_params(hw);
887 if (offset >= hw->eeprom.word_size) {
888 status = IXGBE_ERR_EEPROM;
892 /* Prepare the EEPROM for reading */
893 status = ixgbe_acquire_eeprom(hw);
895 if (status == IXGBE_SUCCESS) {
896 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
897 ixgbe_release_eeprom(hw);
898 status = IXGBE_ERR_EEPROM;
902 if (status == IXGBE_SUCCESS) {
903 ixgbe_standby_eeprom(hw);
906 * Some SPI eeproms use the 8th address bit embedded in the
909 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
910 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
912 /* Send the READ command (opcode + addr) */
913 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
914 IXGBE_EEPROM_OPCODE_BITS);
915 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
916 hw->eeprom.address_bits);
919 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
920 *data = (word_in >> 8) | (word_in << 8);
922 /* End this read operation */
923 ixgbe_release_eeprom(hw);
931 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
932 * @hw: pointer to hardware structure
933 * @offset: offset of word in the EEPROM to read
934 * @data: word read from the EEPROM
936 * Reads a 16 bit word from the EEPROM using the EERD register.
938 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
943 DEBUGFUNC("ixgbe_read_eerd_generic");
945 hw->eeprom.ops.init_params(hw);
947 if (offset >= hw->eeprom.word_size) {
948 status = IXGBE_ERR_EEPROM;
952 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
953 IXGBE_EEPROM_RW_REG_START;
955 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
956 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
958 if (status == IXGBE_SUCCESS)
959 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
960 IXGBE_EEPROM_RW_REG_DATA);
962 DEBUGOUT("Eeprom read timed out\n");
969 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
970 * @hw: pointer to hardware structure
971 * @offset: offset of word in the EEPROM to write
972 * @data: word write to the EEPROM
974 * Write a 16 bit word to the EEPROM using the EEWR register.
976 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
981 DEBUGFUNC("ixgbe_write_eewr_generic");
983 hw->eeprom.ops.init_params(hw);
985 if (offset >= hw->eeprom.word_size) {
986 status = IXGBE_ERR_EEPROM;
990 eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
991 (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START;
993 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
994 if (status != IXGBE_SUCCESS) {
995 DEBUGOUT("Eeprom write EEWR timed out\n");
999 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1001 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1002 if (status != IXGBE_SUCCESS) {
1003 DEBUGOUT("Eeprom write EEWR timed out\n");
1012 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1013 * @hw: pointer to hardware structure
1014 * @ee_reg: EEPROM flag for polling
1016 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1017 * read or write is done respectively.
1019 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1023 s32 status = IXGBE_ERR_EEPROM;
1025 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1027 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1028 if (ee_reg == IXGBE_NVM_POLL_READ)
1029 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1031 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1033 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1034 status = IXGBE_SUCCESS;
1043 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1044 * @hw: pointer to hardware structure
1046 * Prepares EEPROM for access using bit-bang method. This function should
1047 * be called before issuing a command to the EEPROM.
1049 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1051 s32 status = IXGBE_SUCCESS;
1055 DEBUGFUNC("ixgbe_acquire_eeprom");
1057 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
1058 status = IXGBE_ERR_SWFW_SYNC;
1060 if (status == IXGBE_SUCCESS) {
1061 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1063 /* Request EEPROM Access */
1064 eec |= IXGBE_EEC_REQ;
1065 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1067 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1068 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1069 if (eec & IXGBE_EEC_GNT)
1074 /* Release if grant not acquired */
1075 if (!(eec & IXGBE_EEC_GNT)) {
1076 eec &= ~IXGBE_EEC_REQ;
1077 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1078 DEBUGOUT("Could not acquire EEPROM grant\n");
1080 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1081 status = IXGBE_ERR_EEPROM;
1084 /* Setup EEPROM for Read/Write */
1085 if (status == IXGBE_SUCCESS) {
1086 /* Clear CS and SK */
1087 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1088 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1089 IXGBE_WRITE_FLUSH(hw);
1097 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1098 * @hw: pointer to hardware structure
1100 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1102 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1104 s32 status = IXGBE_ERR_EEPROM;
1109 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1112 /* Get SMBI software semaphore between device drivers first */
1113 for (i = 0; i < timeout; i++) {
1115 * If the SMBI bit is 0 when we read it, then the bit will be
1116 * set and we have the semaphore
1118 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1119 if (!(swsm & IXGBE_SWSM_SMBI)) {
1120 status = IXGBE_SUCCESS;
1126 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1127 if (status == IXGBE_SUCCESS) {
1128 for (i = 0; i < timeout; i++) {
1129 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1131 /* Set the SW EEPROM semaphore bit to request access */
1132 swsm |= IXGBE_SWSM_SWESMBI;
1133 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1136 * If we set the bit successfully then we got the
1139 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1140 if (swsm & IXGBE_SWSM_SWESMBI)
1147 * Release semaphores and return error if SW EEPROM semaphore
1148 * was not granted because we don't have access to the EEPROM
1151 DEBUGOUT("SWESMBI Software EEPROM semaphore "
1153 ixgbe_release_eeprom_semaphore(hw);
1154 status = IXGBE_ERR_EEPROM;
1157 DEBUGOUT("Software semaphore SMBI between device drivers "
1165 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1166 * @hw: pointer to hardware structure
1168 * This function clears hardware semaphore bits.
1170 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1174 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1176 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1178 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1179 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1180 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1181 IXGBE_WRITE_FLUSH(hw);
1185 * ixgbe_ready_eeprom - Polls for EEPROM ready
1186 * @hw: pointer to hardware structure
1188 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1190 s32 status = IXGBE_SUCCESS;
1194 DEBUGFUNC("ixgbe_ready_eeprom");
1197 * Read "Status Register" repeatedly until the LSB is cleared. The
1198 * EEPROM will signal that the command has been completed by clearing
1199 * bit 0 of the internal status register. If it's not cleared within
1200 * 5 milliseconds, then error out.
1202 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1203 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1204 IXGBE_EEPROM_OPCODE_BITS);
1205 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1206 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1210 ixgbe_standby_eeprom(hw);
1214 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1215 * devices (and only 0-5mSec on 5V devices)
1217 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1218 DEBUGOUT("SPI EEPROM Status error\n");
1219 status = IXGBE_ERR_EEPROM;
1226 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1227 * @hw: pointer to hardware structure
1229 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1233 DEBUGFUNC("ixgbe_standby_eeprom");
1235 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1237 /* Toggle CS to flush commands */
1238 eec |= IXGBE_EEC_CS;
1239 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1240 IXGBE_WRITE_FLUSH(hw);
1242 eec &= ~IXGBE_EEC_CS;
1243 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1244 IXGBE_WRITE_FLUSH(hw);
1249 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1250 * @hw: pointer to hardware structure
1251 * @data: data to send to the EEPROM
1252 * @count: number of bits to shift out
1254 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1261 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1263 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1266 * Mask is used to shift "count" bits of "data" out to the EEPROM
1267 * one bit at a time. Determine the starting bit based on count
1269 mask = 0x01 << (count - 1);
1271 for (i = 0; i < count; i++) {
1273 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1274 * "1", and then raising and then lowering the clock (the SK
1275 * bit controls the clock input to the EEPROM). A "0" is
1276 * shifted out to the EEPROM by setting "DI" to "0" and then
1277 * raising and then lowering the clock.
1280 eec |= IXGBE_EEC_DI;
1282 eec &= ~IXGBE_EEC_DI;
1284 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1285 IXGBE_WRITE_FLUSH(hw);
1289 ixgbe_raise_eeprom_clk(hw, &eec);
1290 ixgbe_lower_eeprom_clk(hw, &eec);
1293 * Shift mask to signify next bit of data to shift in to the
1299 /* We leave the "DI" bit set to "0" when we leave this routine. */
1300 eec &= ~IXGBE_EEC_DI;
1301 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1302 IXGBE_WRITE_FLUSH(hw);
1306 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1307 * @hw: pointer to hardware structure
1309 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1315 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1318 * In order to read a register from the EEPROM, we need to shift
1319 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1320 * the clock input to the EEPROM (setting the SK bit), and then reading
1321 * the value of the "DO" bit. During this "shifting in" process the
1322 * "DI" bit should always be clear.
1324 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1326 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1328 for (i = 0; i < count; i++) {
1330 ixgbe_raise_eeprom_clk(hw, &eec);
1332 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1334 eec &= ~(IXGBE_EEC_DI);
1335 if (eec & IXGBE_EEC_DO)
1338 ixgbe_lower_eeprom_clk(hw, &eec);
1345 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1346 * @hw: pointer to hardware structure
1347 * @eec: EEC register's current value
1349 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1351 DEBUGFUNC("ixgbe_raise_eeprom_clk");
1354 * Raise the clock input to the EEPROM
1355 * (setting the SK bit), then delay
1357 *eec = *eec | IXGBE_EEC_SK;
1358 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1359 IXGBE_WRITE_FLUSH(hw);
1364 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1365 * @hw: pointer to hardware structure
1366 * @eecd: EECD's current value
1368 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1370 DEBUGFUNC("ixgbe_lower_eeprom_clk");
1373 * Lower the clock input to the EEPROM (clearing the SK bit), then
1376 *eec = *eec & ~IXGBE_EEC_SK;
1377 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1378 IXGBE_WRITE_FLUSH(hw);
1383 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1384 * @hw: pointer to hardware structure
1386 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1390 DEBUGFUNC("ixgbe_release_eeprom");
1392 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1394 eec |= IXGBE_EEC_CS; /* Pull CS high */
1395 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1397 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1398 IXGBE_WRITE_FLUSH(hw);
1402 /* Stop requesting EEPROM access */
1403 eec &= ~IXGBE_EEC_REQ;
1404 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1406 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1408 /* Delay before attempt to obtain semaphore again to allow FW access */
1409 msec_delay(hw->eeprom.semaphore_delay);
1413 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1414 * @hw: pointer to hardware structure
1416 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1425 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1427 /* Include 0x0-0x3F in the checksum */
1428 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1429 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
1430 DEBUGOUT("EEPROM read failed\n");
1436 /* Include all data from pointers except for the fw pointer */
1437 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1438 hw->eeprom.ops.read(hw, i, &pointer);
1440 /* Make sure the pointer seems valid */
1441 if (pointer != 0xFFFF && pointer != 0) {
1442 hw->eeprom.ops.read(hw, pointer, &length);
1444 if (length != 0xFFFF && length != 0) {
1445 for (j = pointer+1; j <= pointer+length; j++) {
1446 hw->eeprom.ops.read(hw, j, &word);
1453 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1459 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1460 * @hw: pointer to hardware structure
1461 * @checksum_val: calculated checksum
1463 * Performs checksum calculation and validates the EEPROM checksum. If the
1464 * caller does not need checksum_val, the value can be NULL.
1466 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1471 u16 read_checksum = 0;
1473 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
1476 * Read the first word from the EEPROM. If this times out or fails, do
1477 * not continue or we could be in for a very long wait while every
1480 status = hw->eeprom.ops.read(hw, 0, &checksum);
1482 if (status == IXGBE_SUCCESS) {
1483 checksum = hw->eeprom.ops.calc_checksum(hw);
1485 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1488 * Verify read checksum from EEPROM is the same as
1489 * calculated checksum
1491 if (read_checksum != checksum)
1492 status = IXGBE_ERR_EEPROM_CHECKSUM;
1494 /* If the user cares, return the calculated checksum */
1496 *checksum_val = checksum;
1498 DEBUGOUT("EEPROM read failed\n");
1505 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1506 * @hw: pointer to hardware structure
1508 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1513 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
1516 * Read the first word from the EEPROM. If this times out or fails, do
1517 * not continue or we could be in for a very long wait while every
1520 status = hw->eeprom.ops.read(hw, 0, &checksum);
1522 if (status == IXGBE_SUCCESS) {
1523 checksum = hw->eeprom.ops.calc_checksum(hw);
1524 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1527 DEBUGOUT("EEPROM read failed\n");
1534 * ixgbe_validate_mac_addr - Validate MAC address
1535 * @mac_addr: pointer to MAC address.
1537 * Tests a MAC address to ensure it is a valid Individual Address
1539 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1541 s32 status = IXGBE_SUCCESS;
1543 DEBUGFUNC("ixgbe_validate_mac_addr");
1545 /* Make sure it is not a multicast address */
1546 if (IXGBE_IS_MULTICAST(mac_addr)) {
1547 DEBUGOUT("MAC address is multicast\n");
1548 status = IXGBE_ERR_INVALID_MAC_ADDR;
1549 /* Not a broadcast address */
1550 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
1551 DEBUGOUT("MAC address is broadcast\n");
1552 status = IXGBE_ERR_INVALID_MAC_ADDR;
1553 /* Reject the zero address */
1554 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1555 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
1556 DEBUGOUT("MAC address is all zeros\n");
1557 status = IXGBE_ERR_INVALID_MAC_ADDR;
1563 * ixgbe_set_rar_generic - Set Rx address register
1564 * @hw: pointer to hardware structure
1565 * @index: Receive address register to write
1566 * @addr: Address to put into receive address register
1567 * @vmdq: VMDq "set" or "pool" index
1568 * @enable_addr: set flag that address is active
1570 * Puts an ethernet address into a receive address register.
1572 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1575 u32 rar_low, rar_high;
1576 u32 rar_entries = hw->mac.num_rar_entries;
1578 DEBUGFUNC("ixgbe_set_rar_generic");
1580 /* Make sure we are using a valid rar index range */
1581 if (index >= rar_entries) {
1582 DEBUGOUT1("RAR index %d is out of range.\n", index);
1583 return IXGBE_ERR_INVALID_ARGUMENT;
1586 /* setup VMDq pool selection before this RAR gets enabled */
1587 hw->mac.ops.set_vmdq(hw, index, vmdq);
1590 * HW expects these in little endian so we reverse the byte
1591 * order from network order (big endian) to little endian
1593 rar_low = ((u32)addr[0] |
1594 ((u32)addr[1] << 8) |
1595 ((u32)addr[2] << 16) |
1596 ((u32)addr[3] << 24));
1598 * Some parts put the VMDq setting in the extra RAH bits,
1599 * so save everything except the lower 16 bits that hold part
1600 * of the address and the address valid bit.
1602 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1603 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1604 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1606 if (enable_addr != 0)
1607 rar_high |= IXGBE_RAH_AV;
1609 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1610 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1612 return IXGBE_SUCCESS;
1616 * ixgbe_clear_rar_generic - Remove Rx address register
1617 * @hw: pointer to hardware structure
1618 * @index: Receive address register to write
1620 * Clears an ethernet address from a receive address register.
1622 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1625 u32 rar_entries = hw->mac.num_rar_entries;
1627 DEBUGFUNC("ixgbe_clear_rar_generic");
1629 /* Make sure we are using a valid rar index range */
1630 if (index >= rar_entries) {
1631 DEBUGOUT1("RAR index %d is out of range.\n", index);
1632 return IXGBE_ERR_INVALID_ARGUMENT;
1636 * Some parts put the VMDq setting in the extra RAH bits,
1637 * so save everything except the lower 16 bits that hold part
1638 * of the address and the address valid bit.
1640 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1641 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1643 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1644 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1646 /* clear VMDq pool/queue selection for this RAR */
1647 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1649 return IXGBE_SUCCESS;
1653 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1654 * @hw: pointer to hardware structure
1656 * Places the MAC address in receive address register 0 and clears the rest
1657 * of the receive address registers. Clears the multicast table. Assumes
1658 * the receiver is in reset when the routine is called.
1660 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1663 u32 rar_entries = hw->mac.num_rar_entries;
1665 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
1668 * If the current mac address is valid, assume it is a software override
1669 * to the permanent address.
1670 * Otherwise, use the permanent address from the eeprom.
1672 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1673 IXGBE_ERR_INVALID_MAC_ADDR) {
1674 /* Get the MAC address from the RAR0 for later reference */
1675 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1677 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1678 hw->mac.addr[0], hw->mac.addr[1],
1680 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1681 hw->mac.addr[4], hw->mac.addr[5]);
1683 /* Setup the receive address. */
1684 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
1685 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
1686 hw->mac.addr[0], hw->mac.addr[1],
1688 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
1689 hw->mac.addr[4], hw->mac.addr[5]);
1691 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1693 hw->addr_ctrl.overflow_promisc = 0;
1695 hw->addr_ctrl.rar_used_count = 1;
1697 /* Zero out the other receive addresses. */
1698 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
1699 for (i = 1; i < rar_entries; i++) {
1700 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1701 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1705 hw->addr_ctrl.mta_in_use = 0;
1706 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1708 DEBUGOUT(" Clearing MTA\n");
1709 for (i = 0; i < hw->mac.mcft_size; i++)
1710 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1712 ixgbe_init_uta_tables(hw);
1714 return IXGBE_SUCCESS;
1718 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1719 * @hw: pointer to hardware structure
1720 * @addr: new address
1722 * Adds it to unused receive address register or goes into promiscuous mode.
1724 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1726 u32 rar_entries = hw->mac.num_rar_entries;
1729 DEBUGFUNC("ixgbe_add_uc_addr");
1731 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1732 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1735 * Place this address in the RAR if there is room,
1736 * else put the controller into promiscuous mode
1738 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1739 rar = hw->addr_ctrl.rar_used_count;
1740 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1741 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
1742 hw->addr_ctrl.rar_used_count++;
1744 hw->addr_ctrl.overflow_promisc++;
1747 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
1751 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1752 * @hw: pointer to hardware structure
1753 * @addr_list: the list of new addresses
1754 * @addr_count: number of addresses
1755 * @next: iterator function to walk the address list
1757 * The given list replaces any existing list. Clears the secondary addrs from
1758 * receive address registers. Uses unused receive address registers for the
1759 * first secondary addresses, and falls back to promiscuous mode as needed.
1761 * Drivers using secondary unicast addresses must set user_set_promisc when
1762 * manually putting the device into promiscuous mode.
1764 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
1765 u32 addr_count, ixgbe_mc_addr_itr next)
1769 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1774 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
1777 * Clear accounting of old secondary address list,
1778 * don't count RAR[0]
1780 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1781 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1782 hw->addr_ctrl.overflow_promisc = 0;
1784 /* Zero out the other receive addresses */
1785 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
1786 for (i = 0; i < uc_addr_in_use; i++) {
1787 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
1788 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
1791 /* Add the new addresses */
1792 for (i = 0; i < addr_count; i++) {
1793 DEBUGOUT(" Adding the secondary addresses:\n");
1794 addr = next(hw, &addr_list, &vmdq);
1795 ixgbe_add_uc_addr(hw, addr, vmdq);
1798 if (hw->addr_ctrl.overflow_promisc) {
1799 /* enable promisc if not already in overflow or set by user */
1800 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1801 DEBUGOUT(" Entering address overflow promisc mode\n");
1802 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1803 fctrl |= IXGBE_FCTRL_UPE;
1804 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1807 /* only disable if set by overflow, not by user */
1808 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1809 DEBUGOUT(" Leaving address overflow promisc mode\n");
1810 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1811 fctrl &= ~IXGBE_FCTRL_UPE;
1812 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1816 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
1817 return IXGBE_SUCCESS;
1821 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1822 * @hw: pointer to hardware structure
1823 * @mc_addr: the multicast address
1825 * Extracts the 12 bits, from a multicast address, to determine which
1826 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1827 * incoming rx multicast addresses, to determine the bit-vector to check in
1828 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1829 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1830 * to mc_filter_type.
1832 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1836 DEBUGFUNC("ixgbe_mta_vector");
1838 switch (hw->mac.mc_filter_type) {
1839 case 0: /* use bits [47:36] of the address */
1840 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1842 case 1: /* use bits [46:35] of the address */
1843 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1845 case 2: /* use bits [45:34] of the address */
1846 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1848 case 3: /* use bits [43:32] of the address */
1849 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1851 default: /* Invalid mc_filter_type */
1852 DEBUGOUT("MC filter type param set incorrectly\n");
1857 /* vector can only be 12-bits or boundary will be exceeded */
1863 * ixgbe_set_mta - Set bit-vector in multicast table
1864 * @hw: pointer to hardware structure
1865 * @hash_value: Multicast address hash value
1867 * Sets the bit-vector in the multicast table.
1869 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1875 DEBUGFUNC("ixgbe_set_mta");
1877 hw->addr_ctrl.mta_in_use++;
1879 vector = ixgbe_mta_vector(hw, mc_addr);
1880 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
1883 * The MTA is a register array of 128 32-bit registers. It is treated
1884 * like an array of 4096 bits. We want to set bit
1885 * BitArray[vector_value]. So we figure out what register the bit is
1886 * in, read it, OR in the new bit, then write back the new value. The
1887 * register is determined by the upper 7 bits of the vector value and
1888 * the bit within that register are determined by the lower 5 bits of
1891 vector_reg = (vector >> 5) & 0x7F;
1892 vector_bit = vector & 0x1F;
1893 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
1897 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1898 * @hw: pointer to hardware structure
1899 * @mc_addr_list: the list of new multicast addresses
1900 * @mc_addr_count: number of addresses
1901 * @next: iterator function to walk the multicast address list
1903 * The given list replaces any existing list. Clears the MC addrs from receive
1904 * address registers and the multicast table. Uses unused receive address
1905 * registers for the first multicast addresses, and hashes the rest into the
1908 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1909 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1914 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
1917 * Set the new number of MC addresses that we are being requested to
1920 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1921 hw->addr_ctrl.mta_in_use = 0;
1923 /* Clear mta_shadow */
1924 DEBUGOUT(" Clearing MTA\n");
1925 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
1927 /* Update mta_shadow */
1928 for (i = 0; i < mc_addr_count; i++) {
1929 DEBUGOUT(" Adding the multicast addresses:\n");
1930 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1934 for (i = 0; i < hw->mac.mcft_size; i++)
1935 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1936 hw->mac.mta_shadow[i]);
1938 if (hw->addr_ctrl.mta_in_use > 0)
1939 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1940 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1942 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
1943 return IXGBE_SUCCESS;
1947 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1948 * @hw: pointer to hardware structure
1950 * Enables multicast address in RAR and the use of the multicast hash table.
1952 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1954 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1956 DEBUGFUNC("ixgbe_enable_mc_generic");
1958 if (a->mta_in_use > 0)
1959 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1960 hw->mac.mc_filter_type);
1962 return IXGBE_SUCCESS;
1966 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1967 * @hw: pointer to hardware structure
1969 * Disables multicast address in RAR and the use of the multicast hash table.
1971 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1973 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1975 DEBUGFUNC("ixgbe_disable_mc_generic");
1977 if (a->mta_in_use > 0)
1978 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1980 return IXGBE_SUCCESS;
1984 * ixgbe_fc_enable_generic - Enable flow control
1985 * @hw: pointer to hardware structure
1986 * @packetbuf_num: packet buffer number (0-7)
1988 * Enable flow control according to the current settings.
1990 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1992 s32 ret_val = IXGBE_SUCCESS;
1993 u32 mflcn_reg, fccfg_reg;
1998 DEBUGFUNC("ixgbe_fc_enable_generic");
2000 /* Negotiate the fc mode to use */
2001 ret_val = ixgbe_fc_autoneg(hw);
2002 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
2005 /* Disable any previous flow control settings */
2006 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2007 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
2009 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2010 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2013 * The possible values of fc.current_mode are:
2014 * 0: Flow control is completely disabled
2015 * 1: Rx flow control is enabled (we can receive pause frames,
2016 * but not send pause frames).
2017 * 2: Tx flow control is enabled (we can send pause frames but
2018 * we do not support receiving pause frames).
2019 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2022 switch (hw->fc.current_mode) {
2025 * Flow control is disabled by software override or autoneg.
2026 * The code below will actually disable it in the HW.
2029 case ixgbe_fc_rx_pause:
2031 * Rx Flow control is enabled and Tx Flow control is
2032 * disabled by software override. Since there really
2033 * isn't a way to advertise that we are capable of RX
2034 * Pause ONLY, we will advertise that we support both
2035 * symmetric and asymmetric Rx PAUSE. Later, we will
2036 * disable the adapter's ability to send PAUSE frames.
2038 mflcn_reg |= IXGBE_MFLCN_RFCE;
2040 case ixgbe_fc_tx_pause:
2042 * Tx Flow control is enabled, and Rx Flow control is
2043 * disabled by software override.
2045 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2048 /* Flow control (both Rx and Tx) is enabled by SW override. */
2049 mflcn_reg |= IXGBE_MFLCN_RFCE;
2050 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2053 DEBUGOUT("Flow control param set incorrectly\n");
2054 ret_val = IXGBE_ERR_CONFIG;
2059 /* Set 802.3x based flow control settings. */
2060 mflcn_reg |= IXGBE_MFLCN_DPF;
2061 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2062 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2064 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
2065 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
2067 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
2068 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
2070 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2071 fcrth |= IXGBE_FCRTH_FCEN;
2072 if (hw->fc.send_xon)
2073 fcrtl |= IXGBE_FCRTL_XONE;
2076 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2077 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2079 /* Configure pause time (2 TCs per register) */
2080 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
2081 if ((packetbuf_num & 1) == 0)
2082 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2084 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2085 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2087 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2094 * ixgbe_fc_autoneg - Configure flow control
2095 * @hw: pointer to hardware structure
2097 * Compares our advertised flow control capabilities to those advertised by
2098 * our link partner, and determines the proper flow control mode to use.
2100 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2102 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2103 ixgbe_link_speed speed;
2106 DEBUGFUNC("ixgbe_fc_autoneg");
2108 if (hw->fc.disable_fc_autoneg)
2112 * AN should have completed when the cable was plugged in.
2113 * Look for reasons to bail out. Bail out if:
2114 * - FC autoneg is disabled, or if
2117 * Since we're being called from an LSC, link is already known to be up.
2118 * So use link_up_wait_to_complete=FALSE.
2120 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2122 ret_val = IXGBE_ERR_FLOW_CONTROL;
2126 switch (hw->phy.media_type) {
2127 /* Autoneg flow control on fiber adapters */
2128 case ixgbe_media_type_fiber:
2129 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2130 ret_val = ixgbe_fc_autoneg_fiber(hw);
2133 /* Autoneg flow control on backplane adapters */
2134 case ixgbe_media_type_backplane:
2135 ret_val = ixgbe_fc_autoneg_backplane(hw);
2138 /* Autoneg flow control on copper adapters */
2139 case ixgbe_media_type_copper:
2140 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2141 ret_val = ixgbe_fc_autoneg_copper(hw);
2149 if (ret_val == IXGBE_SUCCESS) {
2150 hw->fc.fc_was_autonegged = TRUE;
2152 hw->fc.fc_was_autonegged = FALSE;
2153 hw->fc.current_mode = hw->fc.requested_mode;
2159 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2160 * @hw: pointer to hardware structure
2164 * Enable flow control according on 1 gig fiber.
2166 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2168 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2172 * On multispeed fiber at 1g, bail out if
2173 * - link is up but AN did not complete, or if
2174 * - link is up and AN completed but timed out
2177 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2178 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2179 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2180 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2184 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2185 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2187 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2188 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2189 IXGBE_PCS1GANA_ASM_PAUSE,
2190 IXGBE_PCS1GANA_SYM_PAUSE,
2191 IXGBE_PCS1GANA_ASM_PAUSE);
2198 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2199 * @hw: pointer to hardware structure
2201 * Enable flow control according to IEEE clause 37.
2203 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2205 u32 links2, anlp1_reg, autoc_reg, links;
2209 * On backplane, bail out if
2210 * - backplane autoneg was not completed, or if
2211 * - we are 82599 and link partner is not AN enabled
2213 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2214 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2215 hw->fc.fc_was_autonegged = FALSE;
2216 hw->fc.current_mode = hw->fc.requested_mode;
2217 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2221 if (hw->mac.type == ixgbe_mac_82599EB) {
2222 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2223 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2224 hw->fc.fc_was_autonegged = FALSE;
2225 hw->fc.current_mode = hw->fc.requested_mode;
2226 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2231 * Read the 10g AN autoc and LP ability registers and resolve
2232 * local flow control settings accordingly
2234 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2235 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2237 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2238 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2239 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2246 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2247 * @hw: pointer to hardware structure
2249 * Enable flow control according to IEEE clause 37.
2251 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2253 u16 technology_ability_reg = 0;
2254 u16 lp_technology_ability_reg = 0;
2256 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2257 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2258 &technology_ability_reg);
2259 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2260 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2261 &lp_technology_ability_reg);
2263 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2264 (u32)lp_technology_ability_reg,
2265 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2266 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2270 * ixgbe_negotiate_fc - Negotiate flow control
2271 * @hw: pointer to hardware structure
2272 * @adv_reg: flow control advertised settings
2273 * @lp_reg: link partner's flow control settings
2274 * @adv_sym: symmetric pause bit in advertisement
2275 * @adv_asm: asymmetric pause bit in advertisement
2276 * @lp_sym: symmetric pause bit in link partner advertisement
2277 * @lp_asm: asymmetric pause bit in link partner advertisement
2279 * Find the intersection between advertised settings and link partner's
2280 * advertised settings
2282 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2283 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2285 if ((!(adv_reg)) || (!(lp_reg)))
2286 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2288 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2290 * Now we need to check if the user selected Rx ONLY
2291 * of pause frames. In this case, we had to advertise
2292 * FULL flow control because we could not advertise RX
2293 * ONLY. Hence, we must now check to see if we need to
2294 * turn OFF the TRANSMISSION of PAUSE frames.
2296 if (hw->fc.requested_mode == ixgbe_fc_full) {
2297 hw->fc.current_mode = ixgbe_fc_full;
2298 DEBUGOUT("Flow Control = FULL.\n");
2300 hw->fc.current_mode = ixgbe_fc_rx_pause;
2301 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2303 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2304 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2305 hw->fc.current_mode = ixgbe_fc_tx_pause;
2306 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2307 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2308 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2309 hw->fc.current_mode = ixgbe_fc_rx_pause;
2310 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2312 hw->fc.current_mode = ixgbe_fc_none;
2313 DEBUGOUT("Flow Control = NONE.\n");
2315 return IXGBE_SUCCESS;
2319 * ixgbe_setup_fc - Set up flow control
2320 * @hw: pointer to hardware structure
2322 * Called at init time to set up flow control.
2324 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
2326 s32 ret_val = IXGBE_SUCCESS;
2327 u32 reg = 0, reg_bp = 0;
2330 DEBUGFUNC("ixgbe_setup_fc");
2332 /* Validate the packetbuf configuration */
2333 if (packetbuf_num < 0 || packetbuf_num > 7) {
2334 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
2335 " 0-7\n", packetbuf_num);
2336 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2341 * Validate the water mark configuration. Zero water marks are invalid
2342 * because it causes the controller to just blast out fc packets.
2344 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
2345 DEBUGOUT("Invalid water mark configuration\n");
2346 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2351 * Validate the requested mode. Strict IEEE mode does not allow
2352 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
2354 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2355 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2356 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2361 * 10gig parts do not have a word in the EEPROM to determine the
2362 * default flow control setting, so we explicitly set it to full.
2364 if (hw->fc.requested_mode == ixgbe_fc_default)
2365 hw->fc.requested_mode = ixgbe_fc_full;
2368 * Set up the 1G and 10G flow control advertisement registers so the
2369 * HW will be able to do fc autoneg once the cable is plugged in. If
2370 * we link at 10G, the 1G advertisement is harmless and vice versa.
2373 switch (hw->phy.media_type) {
2374 case ixgbe_media_type_fiber:
2375 case ixgbe_media_type_backplane:
2376 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2377 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2380 case ixgbe_media_type_copper:
2381 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2382 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
2390 * The possible values of fc.requested_mode are:
2391 * 0: Flow control is completely disabled
2392 * 1: Rx flow control is enabled (we can receive pause frames,
2393 * but not send pause frames).
2394 * 2: Tx flow control is enabled (we can send pause frames but
2395 * we do not support receiving pause frames).
2396 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2399 switch (hw->fc.requested_mode) {
2401 /* Flow control completely disabled by software override. */
2402 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2403 if (hw->phy.media_type == ixgbe_media_type_backplane)
2404 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2405 IXGBE_AUTOC_ASM_PAUSE);
2406 else if (hw->phy.media_type == ixgbe_media_type_copper)
2407 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2409 case ixgbe_fc_rx_pause:
2411 * Rx Flow control is enabled and Tx Flow control is
2412 * disabled by software override. Since there really
2413 * isn't a way to advertise that we are capable of RX
2414 * Pause ONLY, we will advertise that we support both
2415 * symmetric and asymmetric Rx PAUSE. Later, we will
2416 * disable the adapter's ability to send PAUSE frames.
2418 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2419 if (hw->phy.media_type == ixgbe_media_type_backplane)
2420 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2421 IXGBE_AUTOC_ASM_PAUSE);
2422 else if (hw->phy.media_type == ixgbe_media_type_copper)
2423 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2425 case ixgbe_fc_tx_pause:
2427 * Tx Flow control is enabled, and Rx Flow control is
2428 * disabled by software override.
2430 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2431 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
2432 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2433 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2434 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2435 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2436 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2437 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2441 /* Flow control (both Rx and Tx) is enabled by SW override. */
2442 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2443 if (hw->phy.media_type == ixgbe_media_type_backplane)
2444 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2445 IXGBE_AUTOC_ASM_PAUSE);
2446 else if (hw->phy.media_type == ixgbe_media_type_copper)
2447 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2450 DEBUGOUT("Flow control param set incorrectly\n");
2451 ret_val = IXGBE_ERR_CONFIG;
2457 * Enable auto-negotiation between the MAC & PHY;
2458 * the MAC will advertise clause 37 flow control.
2460 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2461 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2463 /* Disable AN timeout */
2464 if (hw->fc.strict_ieee)
2465 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2467 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2468 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2471 * AUTOC restart handles negotiation of 1G and 10G on backplane
2472 * and copper. There is no need to set the PCS1GCTL register.
2475 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2476 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2477 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2478 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2479 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
2480 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2481 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
2484 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2490 * ixgbe_disable_pcie_master - Disable PCI-express master access
2491 * @hw: pointer to hardware structure
2493 * Disables PCI-Express master access and verifies there are no pending
2494 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2495 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2496 * is returned signifying master requests disabled.
2498 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2502 u32 number_of_queues;
2503 s32 status = IXGBE_SUCCESS;
2505 DEBUGFUNC("ixgbe_disable_pcie_master");
2507 /* Just jump out if bus mastering is already disabled */
2508 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2511 /* Disable the receive unit by stopping each queue */
2512 number_of_queues = hw->mac.max_rx_queues;
2513 for (i = 0; i < number_of_queues; i++) {
2514 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2515 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2516 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2517 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2521 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2522 reg_val |= IXGBE_CTRL_GIO_DIS;
2523 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2525 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2526 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2531 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2532 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2535 * The GIO Master Disable bit didn't clear. There are multiple reasons
2536 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they
2537 * all require a double reset to recover from. Before proceeding, we
2538 * first wait a little more to try to ensure that, at a minimum, the
2539 * PCIe block has no transactions pending.
2541 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2542 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2543 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2548 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2549 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2552 * Two consecutive resets are required via CTRL.RST per datasheet
2553 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2554 * of this need. The first reset prevents new master requests from
2555 * being issued by our device. We then must wait 1usec for any
2556 * remaining completions from the PCIe bus to trickle in, and then reset
2557 * again to clear out any effects they may have had on our device.
2559 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2567 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2568 * @hw: pointer to hardware structure
2569 * @mask: Mask to specify which semaphore to acquire
2571 * Acquires the SWFW semaphore thought the GSSR register for the specified
2572 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2574 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2578 u32 fwmask = mask << 5;
2581 DEBUGFUNC("ixgbe_acquire_swfw_sync");
2585 * SW EEPROM semaphore bit is used for access to all
2586 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2588 if (ixgbe_get_eeprom_semaphore(hw))
2589 return IXGBE_ERR_SWFW_SYNC;
2591 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2592 if (!(gssr & (fwmask | swmask)))
2596 * Firmware currently using resource (fwmask) or other software
2597 * thread currently using resource (swmask)
2599 ixgbe_release_eeprom_semaphore(hw);
2605 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2606 return IXGBE_ERR_SWFW_SYNC;
2610 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2612 ixgbe_release_eeprom_semaphore(hw);
2613 return IXGBE_SUCCESS;
2617 * ixgbe_release_swfw_sync - Release SWFW semaphore
2618 * @hw: pointer to hardware structure
2619 * @mask: Mask to specify which semaphore to release
2621 * Releases the SWFW semaphore thought the GSSR register for the specified
2622 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2624 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2629 DEBUGFUNC("ixgbe_release_swfw_sync");
2631 ixgbe_get_eeprom_semaphore(hw);
2633 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2635 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2637 ixgbe_release_eeprom_semaphore(hw);
2641 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2642 * @hw: pointer to hardware structure
2643 * @regval: register value to write to RXCTRL
2645 * Enables the Rx DMA unit
2647 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2649 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2651 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2653 return IXGBE_SUCCESS;
2657 * ixgbe_blink_led_start_generic - Blink LED based on index.
2658 * @hw: pointer to hardware structure
2659 * @index: led number to blink
2661 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2663 ixgbe_link_speed speed = 0;
2665 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2666 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2668 DEBUGFUNC("ixgbe_blink_led_start_generic");
2671 * Link must be up to auto-blink the LEDs;
2672 * Force it if link is down.
2674 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2677 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2678 autoc_reg |= IXGBE_AUTOC_FLU;
2679 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2683 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2684 led_reg |= IXGBE_LED_BLINK(index);
2685 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2686 IXGBE_WRITE_FLUSH(hw);
2688 return IXGBE_SUCCESS;
2692 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2693 * @hw: pointer to hardware structure
2694 * @index: led number to stop blinking
2696 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2698 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2699 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2701 DEBUGFUNC("ixgbe_blink_led_stop_generic");
2704 autoc_reg &= ~IXGBE_AUTOC_FLU;
2705 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2706 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2708 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2709 led_reg &= ~IXGBE_LED_BLINK(index);
2710 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2711 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2712 IXGBE_WRITE_FLUSH(hw);
2714 return IXGBE_SUCCESS;
2718 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2719 * @hw: pointer to hardware structure
2720 * @san_mac_offset: SAN MAC address offset
2722 * This function will read the EEPROM location for the SAN MAC address
2723 * pointer, and returns the value at that location. This is used in both
2724 * get and set mac_addr routines.
2726 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2727 u16 *san_mac_offset)
2729 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
2732 * First read the EEPROM pointer to see if the MAC addresses are
2735 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2737 return IXGBE_SUCCESS;
2741 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2742 * @hw: pointer to hardware structure
2743 * @san_mac_addr: SAN MAC address
2745 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2746 * per-port, so set_lan_id() must be called before reading the addresses.
2747 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2748 * upon for non-SFP connections, so we must call it here.
2750 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2752 u16 san_mac_data, san_mac_offset;
2755 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
2758 * First read the EEPROM pointer to see if the MAC addresses are
2759 * available. If they're not, no point in calling set_lan_id() here.
2761 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2763 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2765 * No addresses available in this EEPROM. It's not an
2766 * error though, so just wipe the local address and return.
2768 for (i = 0; i < 6; i++)
2769 san_mac_addr[i] = 0xFF;
2771 goto san_mac_addr_out;
2774 /* make sure we know which port we need to program */
2775 hw->mac.ops.set_lan_id(hw);
2776 /* apply the port offset to the address offset */
2777 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2778 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2779 for (i = 0; i < 3; i++) {
2780 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2781 san_mac_addr[i * 2] = (u8)(san_mac_data);
2782 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2787 return IXGBE_SUCCESS;
2791 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
2792 * @hw: pointer to hardware structure
2793 * @san_mac_addr: SAN MAC address
2795 * Write a SAN MAC address to the EEPROM.
2797 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2799 s32 status = IXGBE_SUCCESS;
2800 u16 san_mac_data, san_mac_offset;
2803 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
2805 /* Look for SAN mac address pointer. If not defined, return */
2806 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2808 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2809 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2810 goto san_mac_addr_out;
2813 /* Make sure we know which port we need to write */
2814 hw->mac.ops.set_lan_id(hw);
2815 /* Apply the port offset to the address offset */
2816 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2817 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2819 for (i = 0; i < 3; i++) {
2820 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2821 san_mac_data |= (u16)(san_mac_addr[i * 2]);
2822 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2831 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2832 * @hw: pointer to hardware structure
2834 * Read PCIe configuration space, and get the MSI-X vector count from
2835 * the capabilities table.
2837 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2839 u32 msix_count = 64;
2841 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
2842 if (hw->mac.msix_vectors_from_pcie) {
2843 msix_count = IXGBE_READ_PCIE_WORD(hw,
2844 IXGBE_PCIE_MSIX_82599_CAPS);
2845 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2847 /* MSI-X count is zero-based in HW, so increment to give
2856 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
2857 * @hw: pointer to hardware structure
2858 * @addr: Address to put into receive address register
2859 * @vmdq: VMDq pool to assign
2861 * Puts an ethernet address into a receive address register, or
2862 * finds the rar that it is aleady in; adds to the pool list
2864 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2866 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
2867 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
2869 u32 rar_low, rar_high;
2870 u32 addr_low, addr_high;
2872 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
2874 /* swap bytes for HW little endian */
2875 addr_low = addr[0] | (addr[1] << 8)
2878 addr_high = addr[4] | (addr[5] << 8);
2881 * Either find the mac_id in rar or find the first empty space.
2882 * rar_highwater points to just after the highest currently used
2883 * rar in order to shorten the search. It grows when we add a new
2886 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
2887 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
2889 if (((IXGBE_RAH_AV & rar_high) == 0)
2890 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
2891 first_empty_rar = rar;
2892 } else if ((rar_high & 0xFFFF) == addr_high) {
2893 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
2894 if (rar_low == addr_low)
2895 break; /* found it already in the rars */
2899 if (rar < hw->mac.rar_highwater) {
2900 /* already there so just add to the pool bits */
2901 ixgbe_set_vmdq(hw, rar, vmdq);
2902 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
2903 /* stick it into first empty RAR slot we found */
2904 rar = first_empty_rar;
2905 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2906 } else if (rar == hw->mac.rar_highwater) {
2907 /* add it to the top of the list and inc the highwater mark */
2908 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2909 hw->mac.rar_highwater++;
2910 } else if (rar >= hw->mac.num_rar_entries) {
2911 return IXGBE_ERR_INVALID_MAC_ADDR;
2915 * If we found rar[0], make sure the default pool bit (we use pool 0)
2916 * remains cleared to be sure default pool packets will get delivered
2919 ixgbe_clear_vmdq(hw, rar, 0);
2925 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2926 * @hw: pointer to hardware struct
2927 * @rar: receive address register index to disassociate
2928 * @vmdq: VMDq pool index to remove from the rar
2930 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2932 u32 mpsar_lo, mpsar_hi;
2933 u32 rar_entries = hw->mac.num_rar_entries;
2935 DEBUGFUNC("ixgbe_clear_vmdq_generic");
2937 /* Make sure we are using a valid rar index range */
2938 if (rar >= rar_entries) {
2939 DEBUGOUT1("RAR index %d is out of range.\n", rar);
2940 return IXGBE_ERR_INVALID_ARGUMENT;
2943 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2944 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2946 if (!mpsar_lo && !mpsar_hi)
2949 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2951 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2955 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2958 } else if (vmdq < 32) {
2959 mpsar_lo &= ~(1 << vmdq);
2960 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2962 mpsar_hi &= ~(1 << (vmdq - 32));
2963 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2966 /* was that the last pool using this rar? */
2967 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2968 hw->mac.ops.clear_rar(hw, rar);
2970 return IXGBE_SUCCESS;
2974 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2975 * @hw: pointer to hardware struct
2976 * @rar: receive address register index to associate with a VMDq index
2977 * @vmdq: VMDq pool index
2979 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2982 u32 rar_entries = hw->mac.num_rar_entries;
2984 DEBUGFUNC("ixgbe_set_vmdq_generic");
2986 /* Make sure we are using a valid rar index range */
2987 if (rar >= rar_entries) {
2988 DEBUGOUT1("RAR index %d is out of range.\n", rar);
2989 return IXGBE_ERR_INVALID_ARGUMENT;
2993 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2995 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2997 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2998 mpsar |= 1 << (vmdq - 32);
2999 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3001 return IXGBE_SUCCESS;
3005 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3006 * @hw: pointer to hardware structure
3008 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3012 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3013 DEBUGOUT(" Clearing UTA\n");
3015 for (i = 0; i < 128; i++)
3016 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3018 return IXGBE_SUCCESS;
3022 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3023 * @hw: pointer to hardware structure
3024 * @vlan: VLAN id to write to VLAN filter
3026 * return the VLVF index where this VLAN id should be placed
3029 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3032 u32 first_empty_slot = 0;
3035 /* short cut the special case */
3040 * Search for the vlan id in the VLVF entries. Save off the first empty
3041 * slot found along the way
3043 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3044 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3045 if (!bits && !(first_empty_slot))
3046 first_empty_slot = regindex;
3047 else if ((bits & 0x0FFF) == vlan)
3052 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3053 * in the VLVF. Else use the first empty VLVF register for this
3056 if (regindex >= IXGBE_VLVF_ENTRIES) {
3057 if (first_empty_slot)
3058 regindex = first_empty_slot;
3060 DEBUGOUT("No space in VLVF.\n");
3061 regindex = IXGBE_ERR_NO_SPACE;
3069 * ixgbe_set_vfta_generic - Set VLAN filter table
3070 * @hw: pointer to hardware structure
3071 * @vlan: VLAN id to write to VLAN filter
3072 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3073 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3075 * Turn on/off specified VLAN in the VLAN filter table.
3077 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3086 bool vfta_changed = FALSE;
3088 DEBUGFUNC("ixgbe_set_vfta_generic");
3091 return IXGBE_ERR_PARAM;
3094 * this is a 2 part operation - first the VFTA, then the
3095 * VLVF and VLVFB if VT Mode is set
3096 * We don't write the VFTA until we know the VLVF part succeeded.
3100 * The VFTA is a bitstring made up of 128 32-bit registers
3101 * that enable the particular VLAN id, much like the MTA:
3102 * bits[11-5]: which register
3103 * bits[4-0]: which bit in the register
3105 regindex = (vlan >> 5) & 0x7F;
3106 bitindex = vlan & 0x1F;
3107 targetbit = (1 << bitindex);
3108 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3111 if (!(vfta & targetbit)) {
3113 vfta_changed = TRUE;
3116 if ((vfta & targetbit)) {
3118 vfta_changed = TRUE;
3125 * make sure the vlan is in VLVF
3126 * set the vind bit in the matching VLVFB
3128 * clear the pool bit and possibly the vind
3130 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3131 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3134 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3139 /* set the pool bit */
3141 bits = IXGBE_READ_REG(hw,
3142 IXGBE_VLVFB(vlvf_index*2));
3143 bits |= (1 << vind);
3145 IXGBE_VLVFB(vlvf_index*2),
3148 bits = IXGBE_READ_REG(hw,
3149 IXGBE_VLVFB((vlvf_index*2)+1));
3150 bits |= (1 << (vind-32));
3152 IXGBE_VLVFB((vlvf_index*2)+1),
3156 /* clear the pool bit */
3158 bits = IXGBE_READ_REG(hw,
3159 IXGBE_VLVFB(vlvf_index*2));
3160 bits &= ~(1 << vind);
3162 IXGBE_VLVFB(vlvf_index*2),
3164 bits |= IXGBE_READ_REG(hw,
3165 IXGBE_VLVFB((vlvf_index*2)+1));
3167 bits = IXGBE_READ_REG(hw,
3168 IXGBE_VLVFB((vlvf_index*2)+1));
3169 bits &= ~(1 << (vind-32));
3171 IXGBE_VLVFB((vlvf_index*2)+1),
3173 bits |= IXGBE_READ_REG(hw,
3174 IXGBE_VLVFB(vlvf_index*2));
3179 * If there are still bits set in the VLVFB registers
3180 * for the VLAN ID indicated we need to see if the
3181 * caller is requesting that we clear the VFTA entry bit.
3182 * If the caller has requested that we clear the VFTA
3183 * entry bit but there are still pools/VFs using this VLAN
3184 * ID entry then ignore the request. We're not worried
3185 * about the case where we're turning the VFTA VLAN ID
3186 * entry bit on, only when requested to turn it off as
3187 * there may be multiple pools and/or VFs using the
3188 * VLAN ID entry. In that case we cannot clear the
3189 * VFTA bit until all pools/VFs using that VLAN ID have also
3190 * been cleared. This will be indicated by "bits" being
3194 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3195 (IXGBE_VLVF_VIEN | vlan));
3197 /* someone wants to clear the vfta entry
3198 * but some pools/VFs are still using it.
3200 vfta_changed = FALSE;
3204 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3208 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3210 return IXGBE_SUCCESS;
3214 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3215 * @hw: pointer to hardware structure
3217 * Clears the VLAN filer table, and the VMDq index associated with the filter
3219 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3223 DEBUGFUNC("ixgbe_clear_vfta_generic");
3225 for (offset = 0; offset < hw->mac.vft_size; offset++)
3226 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3228 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3229 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3230 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3231 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3234 return IXGBE_SUCCESS;
3238 * ixgbe_check_mac_link_generic - Determine link and speed status
3239 * @hw: pointer to hardware structure
3240 * @speed: pointer to link speed
3241 * @link_up: TRUE when link is up
3242 * @link_up_wait_to_complete: bool used to wait for link up or not
3244 * Reads the links register to determine if link is up and the current speed
3246 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3247 bool *link_up, bool link_up_wait_to_complete)
3249 u32 links_reg, links_orig;
3252 DEBUGFUNC("ixgbe_check_mac_link_generic");
3254 /* clear the old state */
3255 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3257 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3259 if (links_orig != links_reg) {
3260 DEBUGOUT2("LINKS changed from %08X to %08X\n",
3261 links_orig, links_reg);
3264 if (link_up_wait_to_complete) {
3265 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3266 if (links_reg & IXGBE_LINKS_UP) {
3273 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3276 if (links_reg & IXGBE_LINKS_UP)
3282 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3283 IXGBE_LINKS_SPEED_10G_82599)
3284 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3285 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3286 IXGBE_LINKS_SPEED_1G_82599)
3287 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3288 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3289 IXGBE_LINKS_SPEED_100_82599)
3290 *speed = IXGBE_LINK_SPEED_100_FULL;
3292 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3294 /* if link is down, zero out the current_mode */
3295 if (*link_up == FALSE) {
3296 hw->fc.current_mode = ixgbe_fc_none;
3297 hw->fc.fc_was_autonegged = FALSE;
3300 return IXGBE_SUCCESS;
3304 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3306 * @hw: pointer to hardware structure
3307 * @wwnn_prefix: the alternative WWNN prefix
3308 * @wwpn_prefix: the alternative WWPN prefix
3310 * This function will read the EEPROM from the alternative SAN MAC address
3311 * block to check the support for the alternative WWNN/WWPN prefix support.
3313 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3317 u16 alt_san_mac_blk_offset;
3319 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3321 /* clear output first */
3322 *wwnn_prefix = 0xFFFF;
3323 *wwpn_prefix = 0xFFFF;
3325 /* check if alternative SAN MAC is supported */
3326 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
3327 &alt_san_mac_blk_offset);
3329 if ((alt_san_mac_blk_offset == 0) ||
3330 (alt_san_mac_blk_offset == 0xFFFF))
3331 goto wwn_prefix_out;
3333 /* check capability in alternative san mac address block */
3334 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3335 hw->eeprom.ops.read(hw, offset, &caps);
3336 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3337 goto wwn_prefix_out;
3339 /* get the corresponding prefix for WWNN/WWPN */
3340 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3341 hw->eeprom.ops.read(hw, offset, wwnn_prefix);
3343 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3344 hw->eeprom.ops.read(hw, offset, wwpn_prefix);
3347 return IXGBE_SUCCESS;
3351 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
3352 * @hw: pointer to hardware structure
3353 * @bs: the fcoe boot status
3355 * This function will read the FCOE boot status from the iSCSI FCOE block
3357 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
3359 u16 offset, caps, flags;
3362 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
3364 /* clear output first */
3365 *bs = ixgbe_fcoe_bootstatus_unavailable;
3367 /* check if FCOE IBA block is present */
3368 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
3369 status = hw->eeprom.ops.read(hw, offset, &caps);
3370 if (status != IXGBE_SUCCESS)
3373 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
3376 /* check if iSCSI FCOE block is populated */
3377 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
3378 if (status != IXGBE_SUCCESS)
3381 if ((offset == 0) || (offset == 0xFFFF))
3384 /* read fcoe flags in iSCSI FCOE block */
3385 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3386 status = hw->eeprom.ops.read(hw, offset, &flags);
3387 if (status != IXGBE_SUCCESS)
3390 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3391 *bs = ixgbe_fcoe_bootstatus_enabled;
3393 *bs = ixgbe_fcoe_bootstatus_disabled;
3400 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
3402 * @hw: pointer to hardware structure
3404 * There are several phys that do not support autoneg flow control. This
3405 * function check the device id to see if the associated phy supports
3406 * autoneg flow control.
3408 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
3411 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
3413 switch (hw->device_id) {
3414 case IXGBE_DEV_ID_82599_T3_LOM:
3415 return IXGBE_SUCCESS;
3417 return IXGBE_ERR_FC_NOT_SUPPORTED;
3422 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3423 * @hw: pointer to hardware structure
3424 * @enable: enable or disable switch for anti-spoofing
3425 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3428 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3431 int pf_target_reg = pf >> 3;
3432 int pf_target_shift = pf % 8;
3435 if (hw->mac.type == ixgbe_mac_82598EB)
3439 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3442 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3443 * MAC anti-spoof enables in each register array element.
3445 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3446 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3448 /* If not enabling anti-spoofing then done */
3453 * The PF should be allowed to spoof so that it can support
3454 * emulation mode NICs. Reset the bit assigned to the PF
3456 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3457 pfvfspoof ^= (1 << pf_target_shift);
3458 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3462 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3463 * @hw: pointer to hardware structure
3464 * @enable: enable or disable switch for VLAN anti-spoofing
3465 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3468 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3470 int vf_target_reg = vf >> 3;
3471 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3474 if (hw->mac.type == ixgbe_mac_82598EB)
3477 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3479 pfvfspoof |= (1 << vf_target_shift);
3481 pfvfspoof &= ~(1 << vf_target_shift);
3482 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);