1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
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8 modification, are permitted provided that the following conditions are met:
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33 ******************************************************************************/
37 #include "ixgbe_type.h"
38 #include "ixgbe_dcb.h"
39 #include "ixgbe_dcb_82598.h"
40 #include "ixgbe_dcb_82599.h"
43 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
44 * credits from the configured bandwidth percentages. Credits
45 * are the smallest unit programmable into the underlying
46 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
47 * groups so this is much simplified from the CEE case.
48 * @bw: bandwidth index by traffic class
49 * @refill: refill credits index by traffic class
50 * @max: max credits by traffic class
51 * @max_frame_size: maximum frame size
53 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
56 int min_percent = 100;
57 int min_credit, multiplier;
60 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
61 IXGBE_DCB_CREDIT_QUANTUM;
63 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
64 if (bw[i] < min_percent && bw[i])
68 multiplier = (min_credit / min_percent) + 1;
70 /* Find out the hw credits for each TC */
71 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
72 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
78 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
85 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
86 * @hw: pointer to hardware structure
87 * @dcb_config: Struct containing DCB settings
88 * @max_frame_size: Maximum frame size
89 * @direction: Configuring either Tx or Rx
91 * This function calculates the credits allocated to each traffic class.
92 * It should be called only after the rules are checked by
93 * ixgbe_dcb_check_config_cee().
95 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
96 struct ixgbe_dcb_config *dcb_config,
97 u32 max_frame_size, u8 direction)
99 struct ixgbe_dcb_tc_path *p;
100 u32 min_multiplier = 0;
101 u16 min_percent = 100;
102 s32 ret_val = IXGBE_SUCCESS;
103 /* Initialization values default for Tx settings */
105 u32 credit_refill = 0;
107 u16 link_percentage = 0;
111 if (dcb_config == NULL) {
112 ret_val = IXGBE_ERR_CONFIG;
116 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
117 IXGBE_DCB_CREDIT_QUANTUM;
119 /* Find smallest link percentage */
120 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
121 p = &dcb_config->tc_config[i].path[direction];
122 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
123 link_percentage = p->bwg_percent;
125 link_percentage = (link_percentage * bw_percent) / 100;
127 if (link_percentage && link_percentage < min_percent)
128 min_percent = link_percentage;
132 * The ratio between traffic classes will control the bandwidth
133 * percentages seen on the wire. To calculate this ratio we use
134 * a multiplier. It is required that the refill credits must be
135 * larger than the max frame size so here we find the smallest
136 * multiplier that will allow all bandwidth percentages to be
137 * greater than the max frame size.
139 min_multiplier = (min_credit / min_percent) + 1;
141 /* Find out the link percentage for each TC first */
142 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
143 p = &dcb_config->tc_config[i].path[direction];
144 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
146 link_percentage = p->bwg_percent;
147 /* Must be careful of integer division for very small nums */
148 link_percentage = (link_percentage * bw_percent) / 100;
149 if (p->bwg_percent > 0 && link_percentage == 0)
152 /* Save link_percentage for reference */
153 p->link_percent = (u8)link_percentage;
155 /* Calculate credit refill ratio using multiplier */
156 credit_refill = min(link_percentage * min_multiplier,
157 (u32)IXGBE_DCB_MAX_CREDIT_REFILL);
159 /* Refill at least minimum credit */
160 if (credit_refill < min_credit)
161 credit_refill = min_credit;
163 p->data_credits_refill = (u16)credit_refill;
165 /* Calculate maximum credit for the TC */
166 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
169 * Adjustment based on rule checking, if the percentage
170 * of a TC is too small, the maximum credit may not be
171 * enough to send out a jumbo frame in data plane arbitration.
173 if (credit_max < min_credit)
174 credit_max = min_credit;
176 if (direction == IXGBE_DCB_TX_CONFIG) {
178 * Adjustment based on rule checking, if the
179 * percentage of a TC is too small, the maximum
180 * credit may not be enough to send out a TSO
181 * packet in descriptor plane arbitration.
183 if (credit_max && (credit_max <
184 IXGBE_DCB_MIN_TSO_CREDIT)
185 && (hw->mac.type == ixgbe_mac_82598EB))
186 credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
188 dcb_config->tc_config[i].desc_credits_max =
192 p->data_credits_max = (u16)credit_max;
200 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
201 * @cfg: dcb configuration to unpack into hardware consumable fields
202 * @map: user priority to traffic class map
203 * @pfc_up: u8 to store user priority PFC bitmask
205 * This unpacks the dcb configuration PFC info which is stored per
206 * traffic class into a 8bit user priority bitmask that can be
207 * consumed by hardware routines. The priority to tc map must be
208 * updated before calling this routine to use current up-to maps.
210 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
212 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
216 * If the TC for this user priority has PFC enabled then set the
217 * matching bit in 'pfc_up' to reflect that PFC is enabled.
219 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
220 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
225 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
228 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
231 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
232 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
235 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
237 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
240 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
241 max[tc] = tc_config[tc].desc_credits_max;
244 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
247 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
250 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
251 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
254 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
257 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
260 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
261 tsa[tc] = tc_config[tc].path[direction].tsa;
264 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
266 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
267 u8 prio_mask = 1 << up;
268 u8 tc = cfg->num_tcs.pg_tcs;
270 /* If tc is 0 then DCB is likely not enabled or supported */
275 * Test from maximum TC to 1 and report the first match we find. If
276 * we find no match we can assume that the TC is 0 since the TC must
277 * be set for all user priorities
279 for (tc--; tc; tc--) {
280 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
287 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
292 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
293 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
297 * ixgbe_dcb_config - Struct containing DCB settings.
298 * @dcb_config: Pointer to DCB config structure
300 * This function checks DCB rules for DCB settings.
301 * The following rules are checked:
302 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
303 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
304 * Group must total 100.
305 * 3. A Traffic Class should not be set to both Link Strict Priority
306 * and Group Strict Priority.
307 * 4. Link strict Bandwidth Groups can only have link strict traffic classes
308 * with zero bandwidth.
310 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
312 struct ixgbe_dcb_tc_path *p;
313 s32 ret_val = IXGBE_SUCCESS;
314 u8 i, j, bw = 0, bw_id;
315 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
316 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
318 memset(bw_sum, 0, sizeof(bw_sum));
319 memset(link_strict, 0, sizeof(link_strict));
321 /* First Tx, then Rx */
322 for (i = 0; i < 2; i++) {
323 /* Check each traffic class for rule violation */
324 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
325 p = &dcb_config->tc_config[j].path[i];
330 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
331 ret_val = IXGBE_ERR_CONFIG;
334 if (p->tsa == ixgbe_dcb_tsa_strict) {
335 link_strict[i][bw_id] = true;
336 /* Link strict should have zero bandwidth */
338 ret_val = IXGBE_ERR_CONFIG;
343 * Traffic classes without link strict
344 * should have non-zero bandwidth.
346 ret_val = IXGBE_ERR_CONFIG;
349 bw_sum[i][bw_id] += bw;
354 /* Check each bandwidth group for rule violation */
355 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
356 bw += dcb_config->bw_percentage[i][j];
358 * Sum of bandwidth percentages of all traffic classes
359 * within a Bandwidth Group must total 100 except for
360 * link strict group (zero bandwidth).
362 if (link_strict[i][j]) {
365 * Link strict group should have zero
368 ret_val = IXGBE_ERR_CONFIG;
371 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
373 ret_val = IXGBE_ERR_CONFIG;
378 if (bw != IXGBE_DCB_BW_PERCENT) {
379 ret_val = IXGBE_ERR_CONFIG;
385 DEBUGOUT2("DCB error code %d while checking %s settings.\n",
386 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
392 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
393 * @hw: pointer to hardware structure
394 * @stats: pointer to statistics structure
395 * @tc_count: Number of elements in bwg_array.
397 * This function returns the status data for each of the Traffic Classes in use.
399 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
402 s32 ret = IXGBE_NOT_IMPLEMENTED;
403 switch (hw->mac.type) {
404 case ixgbe_mac_82598EB:
405 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
407 case ixgbe_mac_82599EB:
410 case ixgbe_mac_X550EM_x:
411 case ixgbe_mac_X550EM_a:
412 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
421 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
422 * @hw: pointer to hardware structure
423 * @stats: pointer to statistics structure
424 * @tc_count: Number of elements in bwg_array.
426 * This function returns the CBFC status data for each of the Traffic Classes.
428 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
431 s32 ret = IXGBE_NOT_IMPLEMENTED;
432 switch (hw->mac.type) {
433 case ixgbe_mac_82598EB:
434 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
436 case ixgbe_mac_82599EB:
439 case ixgbe_mac_X550EM_x:
440 case ixgbe_mac_X550EM_a:
441 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
450 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
451 * @hw: pointer to hardware structure
452 * @dcb_config: pointer to ixgbe_dcb_config structure
454 * Configure Rx Data Arbiter and credits for each traffic class.
456 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
457 struct ixgbe_dcb_config *dcb_config)
459 s32 ret = IXGBE_NOT_IMPLEMENTED;
460 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
461 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
462 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
463 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
464 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
466 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
467 ixgbe_dcb_unpack_max_cee(dcb_config, max);
468 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
469 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
470 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
472 switch (hw->mac.type) {
473 case ixgbe_mac_82598EB:
474 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
476 case ixgbe_mac_82599EB:
479 case ixgbe_mac_X550EM_x:
480 case ixgbe_mac_X550EM_a:
481 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
491 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
492 * @hw: pointer to hardware structure
493 * @dcb_config: pointer to ixgbe_dcb_config structure
495 * Configure Tx Descriptor Arbiter and credits for each traffic class.
497 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
498 struct ixgbe_dcb_config *dcb_config)
500 s32 ret = IXGBE_NOT_IMPLEMENTED;
501 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
502 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
503 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
504 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
506 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
507 ixgbe_dcb_unpack_max_cee(dcb_config, max);
508 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
509 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
511 switch (hw->mac.type) {
512 case ixgbe_mac_82598EB:
513 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
516 case ixgbe_mac_82599EB:
519 case ixgbe_mac_X550EM_x:
520 case ixgbe_mac_X550EM_a:
521 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
531 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
532 * @hw: pointer to hardware structure
533 * @dcb_config: pointer to ixgbe_dcb_config structure
535 * Configure Tx Data Arbiter and credits for each traffic class.
537 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
538 struct ixgbe_dcb_config *dcb_config)
540 s32 ret = IXGBE_NOT_IMPLEMENTED;
541 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
542 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
543 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
544 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
545 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
547 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
548 ixgbe_dcb_unpack_max_cee(dcb_config, max);
549 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
550 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
551 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
553 switch (hw->mac.type) {
554 case ixgbe_mac_82598EB:
555 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
558 case ixgbe_mac_82599EB:
561 case ixgbe_mac_X550EM_x:
562 case ixgbe_mac_X550EM_a:
563 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
574 * ixgbe_dcb_config_pfc_cee - Config priority flow control
575 * @hw: pointer to hardware structure
576 * @dcb_config: pointer to ixgbe_dcb_config structure
578 * Configure Priority Flow Control for each traffic class.
580 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
581 struct ixgbe_dcb_config *dcb_config)
583 s32 ret = IXGBE_NOT_IMPLEMENTED;
585 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
587 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
588 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
590 switch (hw->mac.type) {
591 case ixgbe_mac_82598EB:
592 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
594 case ixgbe_mac_82599EB:
597 case ixgbe_mac_X550EM_x:
598 case ixgbe_mac_X550EM_a:
599 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
608 * ixgbe_dcb_config_tc_stats - Config traffic class statistics
609 * @hw: pointer to hardware structure
611 * Configure queue statistics registers, all queues belonging to same traffic
612 * class uses a single set of queue statistics counters.
614 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
616 s32 ret = IXGBE_NOT_IMPLEMENTED;
617 switch (hw->mac.type) {
618 case ixgbe_mac_82598EB:
619 ret = ixgbe_dcb_config_tc_stats_82598(hw);
621 case ixgbe_mac_82599EB:
624 case ixgbe_mac_X550EM_x:
625 case ixgbe_mac_X550EM_a:
626 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
635 * ixgbe_dcb_hw_config_cee - Config and enable DCB
636 * @hw: pointer to hardware structure
637 * @dcb_config: pointer to ixgbe_dcb_config structure
639 * Configure dcb settings and enable dcb mode.
641 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
642 struct ixgbe_dcb_config *dcb_config)
644 s32 ret = IXGBE_NOT_IMPLEMENTED;
646 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
647 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
648 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
649 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
650 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
652 /* Unpack CEE standard containers */
653 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
654 ixgbe_dcb_unpack_max_cee(dcb_config, max);
655 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
656 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
657 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
659 hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs,
660 0, dcb_config->rx_pba_cfg);
662 switch (hw->mac.type) {
663 case ixgbe_mac_82598EB:
664 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
665 refill, max, bwgid, tsa);
667 case ixgbe_mac_82599EB:
670 case ixgbe_mac_X550EM_x:
671 case ixgbe_mac_X550EM_a:
672 ixgbe_dcb_config_82599(hw, dcb_config);
673 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
677 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
683 if (!ret && dcb_config->pfc_mode_enable) {
684 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
685 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
691 /* Helper routines to abstract HW specifics from DCB netlink ops */
692 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
694 int ret = IXGBE_ERR_PARAM;
696 switch (hw->mac.type) {
697 case ixgbe_mac_82598EB:
698 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
700 case ixgbe_mac_82599EB:
703 case ixgbe_mac_X550EM_x:
704 case ixgbe_mac_X550EM_a:
705 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
713 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
714 u8 *bwg_id, u8 *tsa, u8 *map)
716 switch (hw->mac.type) {
717 case ixgbe_mac_82598EB:
718 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
719 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
721 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
724 case ixgbe_mac_82599EB:
727 case ixgbe_mac_X550EM_x:
728 case ixgbe_mac_X550EM_a:
729 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
731 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
733 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,