1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
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8 modification, are permitted provided that the following conditions are met:
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33 ******************************************************************************/
37 #include "ixgbe_type.h"
38 #include "ixgbe_dcb.h"
39 #include "ixgbe_dcb_82598.h"
40 #include "ixgbe_dcb_82599.h"
43 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
44 * credits from the configured bandwidth percentages. Credits
45 * are the smallest unit programmable into the underlying
46 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
47 * groups so this is much simplified from the CEE case.
49 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
52 int min_percent = 100;
53 int min_credit, multiplier;
56 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
57 IXGBE_DCB_CREDIT_QUANTUM;
59 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
60 if (bw[i] < min_percent && bw[i])
64 multiplier = (min_credit / min_percent) + 1;
66 /* Find out the hw credits for each TC */
67 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
68 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
74 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
81 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
82 * @ixgbe_dcb_config: Struct containing DCB settings.
83 * @direction: Configuring either Tx or Rx.
85 * This function calculates the credits allocated to each traffic class.
86 * It should be called only after the rules are checked by
87 * ixgbe_dcb_check_config_cee().
89 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
90 struct ixgbe_dcb_config *dcb_config,
91 u32 max_frame_size, u8 direction)
93 struct ixgbe_dcb_tc_path *p;
94 u32 min_multiplier = 0;
95 u16 min_percent = 100;
96 s32 ret_val = IXGBE_SUCCESS;
97 /* Initialization values default for Tx settings */
99 u32 credit_refill = 0;
101 u16 link_percentage = 0;
105 if (dcb_config == NULL) {
106 ret_val = IXGBE_ERR_CONFIG;
110 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
111 IXGBE_DCB_CREDIT_QUANTUM;
113 /* Find smallest link percentage */
114 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
115 p = &dcb_config->tc_config[i].path[direction];
116 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
117 link_percentage = p->bwg_percent;
119 link_percentage = (link_percentage * bw_percent) / 100;
121 if (link_percentage && link_percentage < min_percent)
122 min_percent = link_percentage;
126 * The ratio between traffic classes will control the bandwidth
127 * percentages seen on the wire. To calculate this ratio we use
128 * a multiplier. It is required that the refill credits must be
129 * larger than the max frame size so here we find the smallest
130 * multiplier that will allow all bandwidth percentages to be
131 * greater than the max frame size.
133 min_multiplier = (min_credit / min_percent) + 1;
135 /* Find out the link percentage for each TC first */
136 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
137 p = &dcb_config->tc_config[i].path[direction];
138 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
140 link_percentage = p->bwg_percent;
141 /* Must be careful of integer division for very small nums */
142 link_percentage = (link_percentage * bw_percent) / 100;
143 if (p->bwg_percent > 0 && link_percentage == 0)
146 /* Save link_percentage for reference */
147 p->link_percent = (u8)link_percentage;
149 /* Calculate credit refill ratio using multiplier */
150 credit_refill = min(link_percentage * min_multiplier,
151 (u32)IXGBE_DCB_MAX_CREDIT_REFILL);
153 /* Refill at least minimum credit */
154 if (credit_refill < min_credit)
155 credit_refill = min_credit;
157 p->data_credits_refill = (u16)credit_refill;
159 /* Calculate maximum credit for the TC */
160 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
163 * Adjustment based on rule checking, if the percentage
164 * of a TC is too small, the maximum credit may not be
165 * enough to send out a jumbo frame in data plane arbitration.
167 if (credit_max < min_credit)
168 credit_max = min_credit;
170 if (direction == IXGBE_DCB_TX_CONFIG) {
172 * Adjustment based on rule checking, if the
173 * percentage of a TC is too small, the maximum
174 * credit may not be enough to send out a TSO
175 * packet in descriptor plane arbitration.
177 if (credit_max && (credit_max <
178 IXGBE_DCB_MIN_TSO_CREDIT)
179 && (hw->mac.type == ixgbe_mac_82598EB))
180 credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
182 dcb_config->tc_config[i].desc_credits_max =
186 p->data_credits_max = (u16)credit_max;
194 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
195 * @cfg: dcb configuration to unpack into hardware consumable fields
196 * @map: user priority to traffic class map
197 * @pfc_up: u8 to store user priority PFC bitmask
199 * This unpacks the dcb configuration PFC info which is stored per
200 * traffic class into a 8bit user priority bitmask that can be
201 * consumed by hardware routines. The priority to tc map must be
202 * updated before calling this routine to use current up-to maps.
204 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
206 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
210 * If the TC for this user priority has PFC enabled then set the
211 * matching bit in 'pfc_up' to reflect that PFC is enabled.
213 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
214 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
219 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
222 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
225 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
226 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
229 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
231 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
234 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
235 max[tc] = tc_config[tc].desc_credits_max;
238 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
241 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
244 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
245 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
248 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
251 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
254 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
255 tsa[tc] = tc_config[tc].path[direction].tsa;
258 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
260 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
261 u8 prio_mask = 1 << up;
262 u8 tc = cfg->num_tcs.pg_tcs;
264 /* If tc is 0 then DCB is likely not enabled or supported */
269 * Test from maximum TC to 1 and report the first match we find. If
270 * we find no match we can assume that the TC is 0 since the TC must
271 * be set for all user priorities
273 for (tc--; tc; tc--) {
274 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
281 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
286 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
287 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
291 * ixgbe_dcb_config - Struct containing DCB settings.
292 * @dcb_config: Pointer to DCB config structure
294 * This function checks DCB rules for DCB settings.
295 * The following rules are checked:
296 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
297 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
298 * Group must total 100.
299 * 3. A Traffic Class should not be set to both Link Strict Priority
300 * and Group Strict Priority.
301 * 4. Link strict Bandwidth Groups can only have link strict traffic classes
302 * with zero bandwidth.
304 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
306 struct ixgbe_dcb_tc_path *p;
307 s32 ret_val = IXGBE_SUCCESS;
308 u8 i, j, bw = 0, bw_id;
309 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
310 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
312 memset(bw_sum, 0, sizeof(bw_sum));
313 memset(link_strict, 0, sizeof(link_strict));
315 /* First Tx, then Rx */
316 for (i = 0; i < 2; i++) {
317 /* Check each traffic class for rule violation */
318 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
319 p = &dcb_config->tc_config[j].path[i];
324 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
325 ret_val = IXGBE_ERR_CONFIG;
328 if (p->tsa == ixgbe_dcb_tsa_strict) {
329 link_strict[i][bw_id] = TRUE;
330 /* Link strict should have zero bandwidth */
332 ret_val = IXGBE_ERR_CONFIG;
337 * Traffic classes without link strict
338 * should have non-zero bandwidth.
340 ret_val = IXGBE_ERR_CONFIG;
343 bw_sum[i][bw_id] += bw;
348 /* Check each bandwidth group for rule violation */
349 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
350 bw += dcb_config->bw_percentage[i][j];
352 * Sum of bandwidth percentages of all traffic classes
353 * within a Bandwidth Group must total 100 except for
354 * link strict group (zero bandwidth).
356 if (link_strict[i][j]) {
359 * Link strict group should have zero
362 ret_val = IXGBE_ERR_CONFIG;
365 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
367 ret_val = IXGBE_ERR_CONFIG;
372 if (bw != IXGBE_DCB_BW_PERCENT) {
373 ret_val = IXGBE_ERR_CONFIG;
379 DEBUGOUT2("DCB error code %d while checking %s settings.\n",
380 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
386 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
387 * @hw: pointer to hardware structure
388 * @stats: pointer to statistics structure
389 * @tc_count: Number of elements in bwg_array.
391 * This function returns the status data for each of the Traffic Classes in use.
393 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
396 s32 ret = IXGBE_NOT_IMPLEMENTED;
397 switch (hw->mac.type) {
398 case ixgbe_mac_82598EB:
399 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
401 case ixgbe_mac_82599EB:
404 case ixgbe_mac_X550EM_x:
405 case ixgbe_mac_X550EM_a:
406 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
407 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
417 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
418 * @hw: pointer to hardware structure
419 * @stats: pointer to statistics structure
420 * @tc_count: Number of elements in bwg_array.
422 * This function returns the CBFC status data for each of the Traffic Classes.
424 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
427 s32 ret = IXGBE_NOT_IMPLEMENTED;
428 switch (hw->mac.type) {
429 case ixgbe_mac_82598EB:
430 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
432 case ixgbe_mac_82599EB:
435 case ixgbe_mac_X550EM_x:
436 case ixgbe_mac_X550EM_a:
437 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
438 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
448 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
449 * @hw: pointer to hardware structure
450 * @dcb_config: pointer to ixgbe_dcb_config structure
452 * Configure Rx Data Arbiter and credits for each traffic class.
454 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
455 struct ixgbe_dcb_config *dcb_config)
457 s32 ret = IXGBE_NOT_IMPLEMENTED;
458 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
459 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
460 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
461 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
462 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
464 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
465 ixgbe_dcb_unpack_max_cee(dcb_config, max);
466 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
467 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
468 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
470 switch (hw->mac.type) {
471 case ixgbe_mac_82598EB:
472 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
474 case ixgbe_mac_82599EB:
477 case ixgbe_mac_X550EM_x:
478 case ixgbe_mac_X550EM_a:
479 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
480 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
491 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
492 * @hw: pointer to hardware structure
493 * @dcb_config: pointer to ixgbe_dcb_config structure
495 * Configure Tx Descriptor Arbiter and credits for each traffic class.
497 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
498 struct ixgbe_dcb_config *dcb_config)
500 s32 ret = IXGBE_NOT_IMPLEMENTED;
501 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
502 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
503 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
504 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
506 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
507 ixgbe_dcb_unpack_max_cee(dcb_config, max);
508 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
509 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
511 switch (hw->mac.type) {
512 case ixgbe_mac_82598EB:
513 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
516 case ixgbe_mac_82599EB:
519 case ixgbe_mac_X550EM_x:
520 case ixgbe_mac_X550EM_a:
521 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
522 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
533 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
534 * @hw: pointer to hardware structure
535 * @dcb_config: pointer to ixgbe_dcb_config structure
537 * Configure Tx Data Arbiter and credits for each traffic class.
539 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
540 struct ixgbe_dcb_config *dcb_config)
542 s32 ret = IXGBE_NOT_IMPLEMENTED;
543 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
544 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
545 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
546 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
547 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
549 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
550 ixgbe_dcb_unpack_max_cee(dcb_config, max);
551 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
552 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
553 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
555 switch (hw->mac.type) {
556 case ixgbe_mac_82598EB:
557 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
560 case ixgbe_mac_82599EB:
563 case ixgbe_mac_X550EM_x:
564 case ixgbe_mac_X550EM_a:
565 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
566 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
578 * ixgbe_dcb_config_pfc_cee - Config priority flow control
579 * @hw: pointer to hardware structure
580 * @dcb_config: pointer to ixgbe_dcb_config structure
582 * Configure Priority Flow Control for each traffic class.
584 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
585 struct ixgbe_dcb_config *dcb_config)
587 s32 ret = IXGBE_NOT_IMPLEMENTED;
589 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
591 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
592 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
594 switch (hw->mac.type) {
595 case ixgbe_mac_82598EB:
596 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
598 case ixgbe_mac_82599EB:
601 case ixgbe_mac_X550EM_x:
602 case ixgbe_mac_X550EM_a:
603 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
604 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
614 * ixgbe_dcb_config_tc_stats - Config traffic class statistics
615 * @hw: pointer to hardware structure
617 * Configure queue statistics registers, all queues belonging to same traffic
618 * class uses a single set of queue statistics counters.
620 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
622 s32 ret = IXGBE_NOT_IMPLEMENTED;
623 switch (hw->mac.type) {
624 case ixgbe_mac_82598EB:
625 ret = ixgbe_dcb_config_tc_stats_82598(hw);
627 case ixgbe_mac_82599EB:
630 case ixgbe_mac_X550EM_x:
631 case ixgbe_mac_X550EM_a:
632 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
633 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
643 * ixgbe_dcb_hw_config_cee - Config and enable DCB
644 * @hw: pointer to hardware structure
645 * @dcb_config: pointer to ixgbe_dcb_config structure
647 * Configure dcb settings and enable dcb mode.
649 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
650 struct ixgbe_dcb_config *dcb_config)
652 s32 ret = IXGBE_NOT_IMPLEMENTED;
654 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
655 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
656 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
657 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
658 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
660 /* Unpack CEE standard containers */
661 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
662 ixgbe_dcb_unpack_max_cee(dcb_config, max);
663 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
664 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
665 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
667 hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs,
668 0, dcb_config->rx_pba_cfg);
670 switch (hw->mac.type) {
671 case ixgbe_mac_82598EB:
672 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
673 refill, max, bwgid, tsa);
675 case ixgbe_mac_82599EB:
678 case ixgbe_mac_X550EM_x:
679 case ixgbe_mac_X550EM_a:
680 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
681 ixgbe_dcb_config_82599(hw, dcb_config);
682 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
686 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
693 if (!ret && dcb_config->pfc_mode_enable) {
694 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
695 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
701 /* Helper routines to abstract HW specifics from DCB netlink ops */
702 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
704 int ret = IXGBE_ERR_PARAM;
706 switch (hw->mac.type) {
707 case ixgbe_mac_82598EB:
708 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
710 case ixgbe_mac_82599EB:
713 case ixgbe_mac_X550EM_x:
714 case ixgbe_mac_X550EM_a:
715 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
716 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
725 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
726 u8 *bwg_id, u8 *tsa, u8 *map)
728 switch (hw->mac.type) {
729 case ixgbe_mac_82598EB:
730 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
731 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
733 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
736 case ixgbe_mac_82599EB:
739 case ixgbe_mac_X550EM_x:
740 case ixgbe_mac_X550EM_a:
741 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
742 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
744 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
746 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,