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37 #include "ixgbe_type.h"
38 #include "ixgbe_dcb.h"
39 #include "ixgbe_dcb_82598.h"
42 * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
43 * @hw: pointer to hardware structure
44 * @stats: pointer to statistics structure
45 * @tc_count: Number of elements in bwg_array.
47 * This function returns the status data for each of the Traffic Classes in use.
49 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
50 struct ixgbe_hw_stats *stats,
55 DEBUGFUNC("dcb_get_tc_stats");
57 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
58 return IXGBE_ERR_PARAM;
60 /* Statistics pertaining to each traffic class */
61 for (tc = 0; tc < tc_count; tc++) {
62 /* Transmitted Packets */
63 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64 /* Transmitted Bytes */
65 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
66 /* Received Packets */
67 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
69 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
72 /* Can we get rid of these?? Consequently, getting rid
73 * of the tc_stats structure.
75 tc_stats_array[up]->in_overflow_discards = 0;
76 tc_stats_array[up]->out_overflow_discards = 0;
84 * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
85 * @hw: pointer to hardware structure
86 * @stats: pointer to statistics structure
87 * @tc_count: Number of elements in bwg_array.
89 * This function returns the CBFC status data for each of the Traffic Classes.
91 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
92 struct ixgbe_hw_stats *stats,
97 DEBUGFUNC("dcb_get_pfc_stats");
99 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
100 return IXGBE_ERR_PARAM;
102 for (tc = 0; tc < tc_count; tc++) {
103 /* Priority XOFF Transmitted */
104 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
105 /* Priority XOFF Received */
106 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
109 return IXGBE_SUCCESS;
113 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
114 * @hw: pointer to hardware structure
115 * @refill: refill credits index by traffic class
116 * @max: max credits index by traffic class
117 * @tsa: transmission selection algorithm indexed by traffic class
119 * Configure Rx Data Arbiter and credits for each traffic class.
121 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
125 u32 credit_refill = 0;
129 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
130 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
132 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
134 reg &= ~IXGBE_RMCS_ARBDIS;
135 /* Enable Receive Recycle within the BWG */
136 reg |= IXGBE_RMCS_RRM;
137 /* Enable Deficit Fixed Priority arbitration*/
138 reg |= IXGBE_RMCS_DFP;
140 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
142 /* Configure traffic class credits and priority */
143 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
144 credit_refill = refill[i];
147 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
149 if (tsa[i] == ixgbe_dcb_tsa_strict)
150 reg |= IXGBE_RT2CR_LSP;
152 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
155 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
156 reg |= IXGBE_RDRXCTL_RDMTS_1_2;
157 reg |= IXGBE_RDRXCTL_MPBEN;
158 reg |= IXGBE_RDRXCTL_MCEN;
159 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
161 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
162 /* Make sure there is enough descriptors before arbitration */
163 reg &= ~IXGBE_RXCTRL_DMBYPS;
164 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
166 return IXGBE_SUCCESS;
170 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
171 * @hw: pointer to hardware structure
172 * @refill: refill credits index by traffic class
173 * @max: max credits index by traffic class
174 * @bwg_id: bandwidth grouping indexed by traffic class
175 * @tsa: transmission selection algorithm indexed by traffic class
177 * Configure Tx Descriptor Arbiter and credits for each traffic class.
179 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
180 u16 *refill, u16 *max, u8 *bwg_id,
183 u32 reg, max_credits;
186 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
189 reg &= ~IXGBE_DPMCS_ARBDIS;
190 reg |= IXGBE_DPMCS_TSOEF;
192 /* Configure Max TSO packet size 34KB including payload and headers */
193 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
195 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
197 /* Configure traffic class credits and priority */
198 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
199 max_credits = max[i];
200 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
202 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
204 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
205 reg |= IXGBE_TDTQ2TCCR_GSP;
207 if (tsa[i] == ixgbe_dcb_tsa_strict)
208 reg |= IXGBE_TDTQ2TCCR_LSP;
210 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
213 return IXGBE_SUCCESS;
217 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
218 * @hw: pointer to hardware structure
219 * @refill: refill credits index by traffic class
220 * @max: max credits index by traffic class
221 * @bwg_id: bandwidth grouping indexed by traffic class
222 * @tsa: transmission selection algorithm indexed by traffic class
224 * Configure Tx Data Arbiter and credits for each traffic class.
226 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
227 u16 *refill, u16 *max, u8 *bwg_id,
233 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
234 /* Enable Data Plane Arbiter */
235 reg &= ~IXGBE_PDPMCS_ARBDIS;
236 /* Enable DFP and Transmit Recycle Mode */
237 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
239 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
241 /* Configure traffic class credits and priority */
242 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
244 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
245 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
247 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
248 reg |= IXGBE_TDPT2TCCR_GSP;
250 if (tsa[i] == ixgbe_dcb_tsa_strict)
251 reg |= IXGBE_TDPT2TCCR_LSP;
253 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
256 /* Enable Tx packet buffer division */
257 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
258 reg |= IXGBE_DTXCTL_ENDBUBD;
259 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
261 return IXGBE_SUCCESS;
265 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
266 * @hw: pointer to hardware structure
267 * @pfc_en: enabled pfc bitmask
269 * Configure Priority Flow Control for each traffic class.
271 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
276 /* Enable Transmit Priority Flow Control */
277 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
278 reg &= ~IXGBE_RMCS_TFCE_802_3X;
279 reg |= IXGBE_RMCS_TFCE_PRIORITY;
280 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
282 /* Enable Receive Priority Flow Control */
283 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
284 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
287 reg |= IXGBE_FCTRL_RPFCE;
289 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
291 /* Configure PFC Tx thresholds per TC */
292 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
293 if (!(pfc_en & (1 << i))) {
294 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
295 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
299 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
300 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
301 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
302 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
305 /* Configure pause time */
306 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
307 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
308 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
310 /* Configure flow control refresh threshold value */
311 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
313 return IXGBE_SUCCESS;
317 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
318 * @hw: pointer to hardware structure
320 * Configure queue statistics registers, all queues belonging to same traffic
321 * class uses a single set of queue statistics counters.
323 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
329 /* Receive Queues stats setting - 8 queues per statistics reg */
330 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
331 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
332 reg |= ((0x1010101) * j);
333 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
334 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
335 reg |= ((0x1010101) * j);
336 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
338 /* Transmit Queues stats setting - 4 queues per statistics reg*/
339 for (i = 0; i < 8; i++) {
340 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
341 reg |= ((0x1010101) * i);
342 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
345 return IXGBE_SUCCESS;
349 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
350 * @hw: pointer to hardware structure
351 * @link_speed: unused
352 * @refill: refill credits index by traffic class
353 * @max: max credits index by traffic class
354 * @bwg_id: bandwidth grouping indexed by traffic class
355 * @tsa: transmission selection algorithm indexed by traffic class
357 * Configure dcb settings and enable dcb mode.
359 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
360 u16 *refill, u16 *max, u8 *bwg_id,
363 UNREFERENCED_1PARAMETER(link_speed);
365 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
366 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
368 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
370 ixgbe_dcb_config_tc_stats_82598(hw);
373 return IXGBE_SUCCESS;