1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
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8 modification, are permitted provided that the following conditions are met:
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37 #include "ixgbe_type.h"
38 #include "ixgbe_dcb.h"
39 #include "ixgbe_dcb_82599.h"
42 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
43 * @hw: pointer to hardware structure
44 * @stats: pointer to statistics structure
45 * @tc_count: Number of elements in bwg_array.
47 * This function returns the status data for each of the Traffic Classes in use.
49 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
50 struct ixgbe_hw_stats *stats,
55 DEBUGFUNC("dcb_get_tc_stats");
57 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
58 return IXGBE_ERR_PARAM;
60 /* Statistics pertaining to each traffic class */
61 for (tc = 0; tc < tc_count; tc++) {
62 /* Transmitted Packets */
63 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64 /* Transmitted Bytes (read low first to prevent missed carry) */
65 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
67 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
68 /* Received Packets */
69 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
70 /* Received Bytes (read low first to prevent missed carry) */
71 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
73 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
75 /* Received Dropped Packet */
76 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
83 * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
84 * @hw: pointer to hardware structure
85 * @stats: pointer to statistics structure
86 * @tc_count: Number of elements in bwg_array.
88 * This function returns the CBFC status data for each of the Traffic Classes.
90 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
91 struct ixgbe_hw_stats *stats,
96 DEBUGFUNC("dcb_get_pfc_stats");
98 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
99 return IXGBE_ERR_PARAM;
101 for (tc = 0; tc < tc_count; tc++) {
102 /* Priority XOFF Transmitted */
103 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
104 /* Priority XOFF Received */
105 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
108 return IXGBE_SUCCESS;
112 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
113 * @hw: pointer to hardware structure
114 * @refill: refill credits index by traffic class
115 * @max: max credits index by traffic class
116 * @bwg_id: bandwidth grouping indexed by traffic class
117 * @tsa: transmission selection algorithm indexed by traffic class
118 * @map: priority to tc assignments indexed by priority
120 * Configure Rx Packet Arbiter and credits for each traffic class.
122 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
123 u16 *max, u8 *bwg_id, u8 *tsa,
127 u32 credit_refill = 0;
132 * Disable the arbiter before changing parameters
133 * (always enable recycle mode; WSP)
135 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
136 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
139 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
140 * bits sets for the UPs that needs to be mappped to that TC.
141 * e.g if priorities 6 and 7 are to be mapped to a TC then the
142 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
145 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
146 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
148 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
150 /* Configure traffic class credits and priority */
151 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
152 credit_refill = refill[i];
154 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
156 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
158 if (tsa[i] == ixgbe_dcb_tsa_strict)
159 reg |= IXGBE_RTRPT4C_LSP;
161 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
165 * Configure Rx packet plane (recycle mode; WSP) and
168 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
169 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
171 return IXGBE_SUCCESS;
175 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
176 * @hw: pointer to hardware structure
177 * @refill: refill credits index by traffic class
178 * @max: max credits index by traffic class
179 * @bwg_id: bandwidth grouping indexed by traffic class
180 * @tsa: transmission selection algorithm indexed by traffic class
182 * Configure Tx Descriptor Arbiter and credits for each traffic class.
184 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
185 u16 *max, u8 *bwg_id, u8 *tsa)
187 u32 reg, max_credits;
190 /* Clear the per-Tx queue credits; we use per-TC instead */
191 for (i = 0; i < 128; i++) {
192 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
193 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
196 /* Configure traffic class credits and priority */
197 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
198 max_credits = max[i];
199 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
201 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
203 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
204 reg |= IXGBE_RTTDT2C_GSP;
206 if (tsa[i] == ixgbe_dcb_tsa_strict)
207 reg |= IXGBE_RTTDT2C_LSP;
209 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
213 * Configure Tx descriptor plane (recycle mode; WSP) and
216 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
217 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
219 return IXGBE_SUCCESS;
223 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
224 * @hw: pointer to hardware structure
225 * @refill: refill credits index by traffic class
226 * @max: max credits index by traffic class
227 * @bwg_id: bandwidth grouping indexed by traffic class
228 * @tsa: transmission selection algorithm indexed by traffic class
229 * @map: priority to tc assignments indexed by priority
231 * Configure Tx Packet Arbiter and credits for each traffic class.
233 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
234 u16 *max, u8 *bwg_id, u8 *tsa,
241 * Disable the arbiter before changing parameters
242 * (always enable recycle mode; SP; arb delay)
244 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
245 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
247 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
250 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
251 * bits sets for the UPs that needs to be mappped to that TC.
252 * e.g if priorities 6 and 7 are to be mapped to a TC then the
253 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
256 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
257 reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
259 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
261 /* Configure traffic class credits and priority */
262 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
264 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
265 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
267 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
268 reg |= IXGBE_RTTPT2C_GSP;
270 if (tsa[i] == ixgbe_dcb_tsa_strict)
271 reg |= IXGBE_RTTPT2C_LSP;
273 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
277 * Configure Tx packet plane (recycle mode; SP; arb delay) and
280 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
281 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
282 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
284 return IXGBE_SUCCESS;
288 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
289 * @hw: pointer to hardware structure
290 * @pfc_en: enabled pfc bitmask
291 * @map: priority to tc assignments indexed by priority
293 * Configure Priority Flow Control (PFC) for each traffic class.
295 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
297 u32 i, j, fcrtl, reg;
300 /* Enable Transmit Priority Flow Control */
301 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
303 /* Enable Receive Priority Flow Control */
304 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
305 reg |= IXGBE_MFLCN_DPF;
308 * X540 supports per TC Rx priority flow control. So
309 * clear all TCs and only enable those that should be
312 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
314 if (hw->mac.type >= ixgbe_mac_X540)
315 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
318 reg |= IXGBE_MFLCN_RPFCE;
320 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
322 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
328 /* Configure PFC Tx thresholds per TC */
329 for (i = 0; i <= max_tc; i++) {
332 for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
333 if ((map[j] == i) && (pfc_en & (1 << j))) {
340 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
341 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
342 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
345 * In order to prevent Tx hangs when the internal Tx
346 * switch is enabled we must set the high water mark
347 * to the Rx packet buffer size - 24KB. This allows
348 * the Tx switch to function even under heavy Rx
351 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
352 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
355 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
358 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
359 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
360 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
363 /* Configure pause time (2 TCs per register) */
364 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
365 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
366 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
368 /* Configure flow control refresh threshold value */
369 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
371 return IXGBE_SUCCESS;
375 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
376 * @hw: pointer to hardware structure
377 * @dcb_config: pointer to ixgbe_dcb_config structure
379 * Configure queue statistics registers, all queues belonging to same traffic
380 * class uses a single set of queue statistics counters.
382 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
383 struct ixgbe_dcb_config *dcb_config)
388 bool vt_mode = FALSE;
390 if (dcb_config != NULL) {
391 tc_count = dcb_config->num_tcs.pg_tcs;
392 vt_mode = dcb_config->vt_mode;
395 if (!((tc_count == 8 && vt_mode == FALSE) || tc_count == 4))
396 return IXGBE_ERR_PARAM;
398 if (tc_count == 8 && vt_mode == FALSE) {
400 * Receive Queues stats setting
401 * 32 RQSMR registers, each configuring 4 queues.
403 * Set all 16 queues of each TC to the same stat
404 * with TC 'n' going to stat 'n'.
406 for (i = 0; i < 32; i++) {
407 reg = 0x01010101 * (i / 4);
408 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
411 * Transmit Queues stats setting
412 * 32 TQSM registers, each controlling 4 queues.
414 * Set all queues of each TC to the same stat
415 * with TC 'n' going to stat 'n'.
416 * Tx queues are allocated non-uniformly to TCs:
417 * 32, 32, 16, 16, 8, 8, 8, 8.
419 for (i = 0; i < 32; i++) {
436 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
438 } else if (tc_count == 4 && vt_mode == FALSE) {
440 * Receive Queues stats setting
441 * 32 RQSMR registers, each configuring 4 queues.
443 * Set all 16 queues of each TC to the same stat
444 * with TC 'n' going to stat 'n'.
446 for (i = 0; i < 32; i++) {
448 /* In 4 TC mode, odd 16-queue ranges are
452 reg = 0x01010101 * (i / 8);
453 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
456 * Transmit Queues stats setting
457 * 32 TQSM registers, each controlling 4 queues.
459 * Set all queues of each TC to the same stat
460 * with TC 'n' going to stat 'n'.
461 * Tx queues are allocated non-uniformly to TCs:
464 for (i = 0; i < 32; i++) {
473 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
475 } else if (tc_count == 4 && vt_mode == TRUE) {
477 * Receive Queues stats setting
478 * 32 RQSMR registers, each configuring 4 queues.
480 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
481 * pool. Set all 32 queues of each TC across pools to the same
482 * stat with TC 'n' going to stat 'n'.
484 for (i = 0; i < 32; i++)
485 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
487 * Transmit Queues stats setting
488 * 32 TQSM registers, each controlling 4 queues.
490 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
491 * pool. Set all 32 queues of each TC across pools to the same
492 * stat with TC 'n' going to stat 'n'.
494 for (i = 0; i < 32; i++)
495 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
498 return IXGBE_SUCCESS;
502 * ixgbe_dcb_config_82599 - Configure general DCB parameters
503 * @hw: pointer to hardware structure
504 * @dcb_config: pointer to ixgbe_dcb_config structure
506 * Configure general DCB parameters.
508 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
509 struct ixgbe_dcb_config *dcb_config)
514 /* Disable the Tx desc arbiter so that MTQC can be changed */
515 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
516 reg |= IXGBE_RTTDCS_ARBDIS;
517 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
519 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
520 if (dcb_config->num_tcs.pg_tcs == 8) {
521 /* Enable DCB for Rx with 8 TCs */
522 switch (reg & IXGBE_MRQC_MRQE_MASK) {
524 case IXGBE_MRQC_RT4TCEN:
525 /* RSS disabled cases */
526 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
529 case IXGBE_MRQC_RSSEN:
530 case IXGBE_MRQC_RTRSS4TCEN:
531 /* RSS enabled cases */
532 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
533 IXGBE_MRQC_RTRSS8TCEN;
537 * Unsupported value, assume stale data,
541 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
545 if (dcb_config->num_tcs.pg_tcs == 4) {
546 /* We support both VT-on and VT-off with 4 TCs. */
547 if (dcb_config->vt_mode)
548 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
549 IXGBE_MRQC_VMDQRT4TCEN;
551 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
552 IXGBE_MRQC_RTRSS4TCEN;
554 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
556 /* Enable DCB for Tx with 8 TCs */
557 if (dcb_config->num_tcs.pg_tcs == 8)
558 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
560 /* We support both VT-on and VT-off with 4 TCs. */
561 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
562 if (dcb_config->vt_mode)
563 reg |= IXGBE_MTQC_VT_ENA;
565 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
567 /* Disable drop for all queues */
568 for (q = 0; q < 128; q++)
569 IXGBE_WRITE_REG(hw, IXGBE_QDE,
570 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
572 /* Enable the Tx desc arbiter */
573 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
574 reg &= ~IXGBE_RTTDCS_ARBDIS;
575 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
577 /* Enable Security TX Buffer IFG for DCB */
578 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
579 reg |= IXGBE_SECTX_DCB;
580 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
582 return IXGBE_SUCCESS;
586 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
587 * @hw: pointer to hardware structure
588 * @link_speed: unused
589 * @refill: refill credits index by traffic class
590 * @max: max credits index by traffic class
591 * @bwg_id: bandwidth grouping indexed by traffic class
592 * @tsa: transmission selection algorithm indexed by traffic class
593 * @map: priority to tc assignments indexed by priority
595 * Configure dcb settings and enable dcb mode.
597 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
598 u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
601 UNREFERENCED_1PARAMETER(link_speed);
603 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
605 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
607 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
610 return IXGBE_SUCCESS;