1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
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8 modification, are permitted provided that the following conditions are met:
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33 ******************************************************************************/
37 #include "ixgbe_type.h"
38 #include "ixgbe_dcb.h"
39 #include "ixgbe_dcb_82599.h"
42 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
43 * @hw: pointer to hardware structure
44 * @stats: pointer to statistics structure
45 * @tc_count: Number of elements in bwg_array.
47 * This function returns the status data for each of the Traffic Classes in use.
49 s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,
50 struct ixgbe_hw_stats *stats,
55 DEBUGFUNC("dcb_get_tc_stats");
57 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
58 return IXGBE_ERR_PARAM;
60 /* Statistics pertaining to each traffic class */
61 for (tc = 0; tc < tc_count; tc++) {
62 /* Transmitted Packets */
63 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
64 /* Transmitted Bytes (read low first to prevent missed carry) */
65 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));
67 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);
68 /* Received Packets */
69 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
70 /* Received Bytes (read low first to prevent missed carry) */
71 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));
73 (((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);
75 /* Received Dropped Packet */
76 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));
83 * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data
84 * @hw: pointer to hardware structure
85 * @stats: pointer to statistics structure
86 * @tc_count: Number of elements in bwg_array.
88 * This function returns the CBFC status data for each of the Traffic Classes.
90 s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,
91 struct ixgbe_hw_stats *stats,
96 DEBUGFUNC("dcb_get_pfc_stats");
98 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
99 return IXGBE_ERR_PARAM;
101 for (tc = 0; tc < tc_count; tc++) {
102 /* Priority XOFF Transmitted */
103 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
104 /* Priority XOFF Received */
105 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));
108 return IXGBE_SUCCESS;
112 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
113 * @hw: pointer to hardware structure
114 * @dcb_config: pointer to ixgbe_dcb_config structure
116 * Configure Rx Packet Arbiter and credits for each traffic class.
118 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
119 u16 *max, u8 *bwg_id, u8 *tsa,
123 u32 credit_refill = 0;
128 * Disable the arbiter before changing parameters
129 * (always enable recycle mode; WSP)
131 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
132 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
135 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
136 * bits sets for the UPs that needs to be mappped to that TC.
137 * e.g if priorities 6 and 7 are to be mapped to a TC then the
138 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
141 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
142 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
144 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
146 /* Configure traffic class credits and priority */
147 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
148 credit_refill = refill[i];
150 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
152 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
154 if (tsa[i] == ixgbe_dcb_tsa_strict)
155 reg |= IXGBE_RTRPT4C_LSP;
157 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
161 * Configure Rx packet plane (recycle mode; WSP) and
164 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
165 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
167 return IXGBE_SUCCESS;
171 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
172 * @hw: pointer to hardware structure
173 * @dcb_config: pointer to ixgbe_dcb_config structure
175 * Configure Tx Descriptor Arbiter and credits for each traffic class.
177 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
178 u16 *max, u8 *bwg_id, u8 *tsa)
180 u32 reg, max_credits;
183 /* Clear the per-Tx queue credits; we use per-TC instead */
184 for (i = 0; i < 128; i++) {
185 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
186 IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
189 /* Configure traffic class credits and priority */
190 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
191 max_credits = max[i];
192 reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
194 reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
196 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
197 reg |= IXGBE_RTTDT2C_GSP;
199 if (tsa[i] == ixgbe_dcb_tsa_strict)
200 reg |= IXGBE_RTTDT2C_LSP;
202 IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
206 * Configure Tx descriptor plane (recycle mode; WSP) and
209 reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
210 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
212 return IXGBE_SUCCESS;
216 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
217 * @hw: pointer to hardware structure
218 * @dcb_config: pointer to ixgbe_dcb_config structure
220 * Configure Tx Packet Arbiter and credits for each traffic class.
222 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,
223 u16 *max, u8 *bwg_id, u8 *tsa,
230 * Disable the arbiter before changing parameters
231 * (always enable recycle mode; SP; arb delay)
233 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
234 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
236 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
239 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
240 * bits sets for the UPs that needs to be mappped to that TC.
241 * e.g if priorities 6 and 7 are to be mapped to a TC then the
242 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
245 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
246 reg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
248 IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
250 /* Configure traffic class credits and priority */
251 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
253 reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
254 reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
256 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
257 reg |= IXGBE_RTTPT2C_GSP;
259 if (tsa[i] == ixgbe_dcb_tsa_strict)
260 reg |= IXGBE_RTTPT2C_LSP;
262 IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
266 * Configure Tx packet plane (recycle mode; SP; arb delay) and
269 reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
270 (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
271 IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
273 return IXGBE_SUCCESS;
277 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
278 * @hw: pointer to hardware structure
279 * @pfc_en: enabled pfc bitmask
280 * @map: priority to tc assignments indexed by priority
282 * Configure Priority Flow Control (PFC) for each traffic class.
284 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
286 u32 i, j, fcrtl, reg;
289 /* Enable Transmit Priority Flow Control */
290 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);
292 /* Enable Receive Priority Flow Control */
293 reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
294 reg |= IXGBE_MFLCN_DPF;
297 * X540 supports per TC Rx priority flow control. So
298 * clear all TCs and only enable those that should be
301 reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
303 if (hw->mac.type >= ixgbe_mac_X540)
304 reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
307 reg |= IXGBE_MFLCN_RPFCE;
309 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
311 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {
317 /* Configure PFC Tx thresholds per TC */
318 for (i = 0; i <= max_tc; i++) {
321 for (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {
322 if ((map[j] == i) && (pfc_en & (1 << j))) {
329 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
330 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
331 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
334 * In order to prevent Tx hangs when the internal Tx
335 * switch is enabled we must set the high water mark
336 * to the Rx packet buffer size - 24KB. This allows
337 * the Tx switch to function even under heavy Rx
340 reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
341 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
344 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
347 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
348 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
349 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);
352 /* Configure pause time (2 TCs per register) */
353 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
354 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
355 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
357 /* Configure flow control refresh threshold value */
358 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
360 return IXGBE_SUCCESS;
364 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
365 * @hw: pointer to hardware structure
367 * Configure queue statistics registers, all queues belonging to same traffic
368 * class uses a single set of queue statistics counters.
370 s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,
371 struct ixgbe_dcb_config *dcb_config)
376 bool vt_mode = FALSE;
378 if (dcb_config != NULL) {
379 tc_count = dcb_config->num_tcs.pg_tcs;
380 vt_mode = dcb_config->vt_mode;
383 if (!((tc_count == 8 && vt_mode == FALSE) || tc_count == 4))
384 return IXGBE_ERR_PARAM;
386 if (tc_count == 8 && vt_mode == FALSE) {
388 * Receive Queues stats setting
389 * 32 RQSMR registers, each configuring 4 queues.
391 * Set all 16 queues of each TC to the same stat
392 * with TC 'n' going to stat 'n'.
394 for (i = 0; i < 32; i++) {
395 reg = 0x01010101 * (i / 4);
396 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
399 * Transmit Queues stats setting
400 * 32 TQSM registers, each controlling 4 queues.
402 * Set all queues of each TC to the same stat
403 * with TC 'n' going to stat 'n'.
404 * Tx queues are allocated non-uniformly to TCs:
405 * 32, 32, 16, 16, 8, 8, 8, 8.
407 for (i = 0; i < 32; i++) {
424 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
426 } else if (tc_count == 4 && vt_mode == FALSE) {
428 * Receive Queues stats setting
429 * 32 RQSMR registers, each configuring 4 queues.
431 * Set all 16 queues of each TC to the same stat
432 * with TC 'n' going to stat 'n'.
434 for (i = 0; i < 32; i++) {
436 /* In 4 TC mode, odd 16-queue ranges are
440 reg = 0x01010101 * (i / 8);
441 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
444 * Transmit Queues stats setting
445 * 32 TQSM registers, each controlling 4 queues.
447 * Set all queues of each TC to the same stat
448 * with TC 'n' going to stat 'n'.
449 * Tx queues are allocated non-uniformly to TCs:
452 for (i = 0; i < 32; i++) {
461 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
463 } else if (tc_count == 4 && vt_mode == TRUE) {
465 * Receive Queues stats setting
466 * 32 RQSMR registers, each configuring 4 queues.
468 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
469 * pool. Set all 32 queues of each TC across pools to the same
470 * stat with TC 'n' going to stat 'n'.
472 for (i = 0; i < 32; i++)
473 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);
475 * Transmit Queues stats setting
476 * 32 TQSM registers, each controlling 4 queues.
478 * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each
479 * pool. Set all 32 queues of each TC across pools to the same
480 * stat with TC 'n' going to stat 'n'.
482 for (i = 0; i < 32; i++)
483 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);
486 return IXGBE_SUCCESS;
490 * ixgbe_dcb_config_82599 - Configure general DCB parameters
491 * @hw: pointer to hardware structure
492 * @dcb_config: pointer to ixgbe_dcb_config structure
494 * Configure general DCB parameters.
496 s32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,
497 struct ixgbe_dcb_config *dcb_config)
502 /* Disable the Tx desc arbiter so that MTQC can be changed */
503 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
504 reg |= IXGBE_RTTDCS_ARBDIS;
505 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
507 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
508 if (dcb_config->num_tcs.pg_tcs == 8) {
509 /* Enable DCB for Rx with 8 TCs */
510 switch (reg & IXGBE_MRQC_MRQE_MASK) {
512 case IXGBE_MRQC_RT4TCEN:
513 /* RSS disabled cases */
514 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
517 case IXGBE_MRQC_RSSEN:
518 case IXGBE_MRQC_RTRSS4TCEN:
519 /* RSS enabled cases */
520 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
521 IXGBE_MRQC_RTRSS8TCEN;
525 * Unsupported value, assume stale data,
529 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
533 if (dcb_config->num_tcs.pg_tcs == 4) {
534 /* We support both VT-on and VT-off with 4 TCs. */
535 if (dcb_config->vt_mode)
536 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
537 IXGBE_MRQC_VMDQRT4TCEN;
539 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
540 IXGBE_MRQC_RTRSS4TCEN;
542 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
544 /* Enable DCB for Tx with 8 TCs */
545 if (dcb_config->num_tcs.pg_tcs == 8)
546 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
548 /* We support both VT-on and VT-off with 4 TCs. */
549 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
550 if (dcb_config->vt_mode)
551 reg |= IXGBE_MTQC_VT_ENA;
553 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
555 /* Disable drop for all queues */
556 for (q = 0; q < 128; q++)
557 IXGBE_WRITE_REG(hw, IXGBE_QDE,
558 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
560 /* Enable the Tx desc arbiter */
561 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
562 reg &= ~IXGBE_RTTDCS_ARBDIS;
563 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
565 /* Enable Security TX Buffer IFG for DCB */
566 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
567 reg |= IXGBE_SECTX_DCB;
568 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
570 return IXGBE_SUCCESS;
574 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
575 * @hw: pointer to hardware structure
576 * @dcb_config: pointer to ixgbe_dcb_config structure
578 * Configure dcb settings and enable dcb mode.
580 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,
581 u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,
584 UNREFERENCED_1PARAMETER(link_speed);
586 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,
588 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
590 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
593 return IXGBE_SUCCESS;