1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
40 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
41 * @hw: pointer to the hardware structure
43 * Initialize the function pointers.
45 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
47 struct ixgbe_phy_info *phy = &hw->phy;
50 phy->ops.identify = &ixgbe_identify_phy_generic;
51 phy->ops.reset = &ixgbe_reset_phy_generic;
52 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
53 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
54 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
55 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
56 phy->ops.check_link = NULL;
57 phy->ops.get_firmware_version = NULL;
63 * ixgbe_identify_phy_generic - Get physical layer module
64 * @hw: pointer to hardware structure
66 * Determines the physical layer module found on the current adapter.
68 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
70 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
73 if (hw->phy.type == ixgbe_phy_unknown) {
74 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
75 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
76 hw->phy.addr = phy_addr;
79 ixgbe_get_phy_type_from_id(hw->phy.id);
80 status = IXGBE_SUCCESS;
85 status = IXGBE_SUCCESS;
92 * ixgbe_validate_phy_addr - Determines phy address is valid
93 * @hw: pointer to hardware structure
96 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
101 hw->phy.addr = phy_addr;
102 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
103 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
105 if (phy_id != 0xFFFF && phy_id != 0x0)
112 * ixgbe_get_phy_id - Get the phy type
113 * @hw: pointer to hardware structure
116 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
122 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
123 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
126 if (status == IXGBE_SUCCESS) {
127 hw->phy.id = (u32)(phy_id_high << 16);
128 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
129 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
131 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
132 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
139 * ixgbe_get_phy_type_from_id - Get the phy type
140 * @hw: pointer to hardware structure
143 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
145 enum ixgbe_phy_type phy_type;
149 phy_type = ixgbe_phy_tn;
152 phy_type = ixgbe_phy_qt;
155 phy_type = ixgbe_phy_nl;
158 phy_type = ixgbe_phy_unknown;
162 DEBUGOUT1("phy type found is %d\n", phy_type);
167 * ixgbe_reset_phy_generic - Performs a PHY reset
168 * @hw: pointer to hardware structure
170 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
173 * Perform soft PHY reset to the PHY_XS.
174 * This will cause a soft reset to the PHY
176 return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
177 IXGBE_MDIO_PHY_XS_DEV_TYPE,
178 IXGBE_MDIO_PHY_XS_RESET);
182 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
183 * @hw: pointer to hardware structure
184 * @reg_addr: 32 bit address of PHY register to read
185 * @phy_data: Pointer to read data from PHY register
187 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
188 u32 device_type, u16 *phy_data)
193 s32 status = IXGBE_SUCCESS;
196 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
197 gssr = IXGBE_GSSR_PHY1_SM;
199 gssr = IXGBE_GSSR_PHY0_SM;
201 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
202 status = IXGBE_ERR_SWFW_SYNC;
204 if (status == IXGBE_SUCCESS) {
205 /* Setup and write the address cycle command */
206 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
207 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
208 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
209 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
211 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
214 * Check every 10 usec to see if the address cycle completed.
215 * The MDI Command bit will clear when the operation is
218 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
221 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
223 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
228 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
229 DEBUGOUT("PHY address command did not complete.\n");
230 status = IXGBE_ERR_PHY;
233 if (status == IXGBE_SUCCESS) {
235 * Address cycle complete, setup and write the read
238 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
239 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
240 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
241 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
243 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
246 * Check every 10 usec to see if the address cycle
247 * completed. The MDI Command bit will clear when the
248 * operation is complete
250 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
253 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
255 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
259 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
260 DEBUGOUT("PHY read command didn't complete\n");
261 status = IXGBE_ERR_PHY;
264 * Read operation is complete. Get the data
267 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
268 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
269 *phy_data = (u16)(data);
273 ixgbe_release_swfw_sync(hw, gssr);
280 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
281 * @hw: pointer to hardware structure
282 * @reg_addr: 32 bit PHY register to write
283 * @device_type: 5 bit device type
284 * @phy_data: Data to write to the PHY register
286 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
287 u32 device_type, u16 phy_data)
291 s32 status = IXGBE_SUCCESS;
294 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
295 gssr = IXGBE_GSSR_PHY1_SM;
297 gssr = IXGBE_GSSR_PHY0_SM;
299 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
300 status = IXGBE_ERR_SWFW_SYNC;
302 if (status == IXGBE_SUCCESS) {
303 /* Put the data in the MDI single read and write data register*/
304 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
306 /* Setup and write the address cycle command */
307 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
308 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
309 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
310 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
312 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
315 * Check every 10 usec to see if the address cycle completed.
316 * The MDI Command bit will clear when the operation is
319 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
322 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
324 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
328 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
329 DEBUGOUT("PHY address cmd didn't complete\n");
330 status = IXGBE_ERR_PHY;
333 if (status == IXGBE_SUCCESS) {
335 * Address cycle complete, setup and write the write
338 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
339 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
340 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
341 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
343 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
346 * Check every 10 usec to see if the address cycle
347 * completed. The MDI Command bit will clear when the
348 * operation is complete
350 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
353 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
355 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
359 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
360 DEBUGOUT("PHY address cmd didn't complete\n");
361 status = IXGBE_ERR_PHY;
365 ixgbe_release_swfw_sync(hw, gssr);
372 * ixgbe_setup_phy_link_generic - Set and restart autoneg
373 * @hw: pointer to hardware structure
375 * Restart autonegotiation and PHY and waits for completion.
377 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
379 s32 status = IXGBE_NOT_IMPLEMENTED;
381 u32 max_time_out = 10;
382 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
385 * Set advertisement settings in PHY based on autoneg_advertised
386 * settings. If autoneg_advertised = 0, then advertise default values
387 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
390 hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
391 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
393 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
394 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
396 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
398 hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
399 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
401 /* Restart PHY autonegotiation and wait for completion */
402 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
403 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
405 autoneg_reg |= IXGBE_MII_RESTART;
407 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
408 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
410 /* Wait for autonegotiation to finish */
411 for (time_out = 0; time_out < max_time_out; time_out++) {
413 /* Restart PHY autonegotiation and wait for completion */
414 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
415 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
418 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
419 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
420 status = IXGBE_SUCCESS;
425 if (time_out == max_time_out)
426 status = IXGBE_ERR_LINK_SETUP;
432 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
433 * @hw: pointer to hardware structure
434 * @speed: new link speed
435 * @autoneg: TRUE if autonegotiation enabled
437 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
438 ixgbe_link_speed speed,
440 bool autoneg_wait_to_complete)
442 UNREFERENCED_PARAMETER(autoneg);
443 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
446 * Clear autoneg_advertised and set new values based on input link
449 hw->phy.autoneg_advertised = 0;
451 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
452 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
454 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
455 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
458 /* Setup link based on the new speed settings */
459 hw->phy.ops.setup_link(hw);
461 return IXGBE_SUCCESS;
465 * ixgbe_check_phy_link_tnx - Determine link and speed status
466 * @hw: pointer to hardware structure
468 * Reads the VS1 register to determine if link is up and the current speed for
471 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
474 s32 status = IXGBE_SUCCESS;
476 u32 max_time_out = 10;
481 /* Initialize speed and link to default case */
483 *speed = IXGBE_LINK_SPEED_10GB_FULL;
486 * Check current speed and link status of the PHY register.
487 * This is a vendor specific register and may have to
488 * be changed for other copper PHYs.
490 for (time_out = 0; time_out < max_time_out; time_out++) {
492 status = hw->phy.ops.read_reg(hw,
493 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
494 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
496 phy_link = phy_data &
497 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
498 phy_speed = phy_data &
499 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
500 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
503 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
504 *speed = IXGBE_LINK_SPEED_1GB_FULL;
513 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
514 * @hw: pointer to hardware structure
515 * @firmware_version: pointer to the PHY Firmware Version
517 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
518 u16 *firmware_version)
520 s32 status = IXGBE_SUCCESS;
522 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
523 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
530 * ixgbe_reset_phy_nl - Performs a PHY reset
531 * @hw: pointer to hardware structure
533 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
535 u16 phy_offset, control, eword, edata, list_crc, block_crc, id, sfp_id;
536 bool end_data = FALSE;
537 u16 list_offset, data_offset;
539 s32 ret_val = IXGBE_SUCCESS;
542 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
543 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
545 /* reset the PHY and poll for completion */
546 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
547 IXGBE_MDIO_PHY_XS_DEV_TYPE,
548 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
550 for (i = 0; i < 100; i++) {
551 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
552 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
553 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0 )
558 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
559 DEBUGOUT("PHY reset did not complete.\n");
560 ret_val = IXGBE_ERR_PHY;
564 /* read offset to PHY init contents */
565 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, &list_offset);
567 if ((!list_offset) || (list_offset == 0xFFFF)) {
568 ret_val = IXGBE_ERR_PHY;
572 /* Acquire the CRC */
573 hw->eeprom.ops.read(hw, list_offset, &list_crc);
575 /* Shift offset to first ID word */
578 /* determine the sfp sequence based on device ID */
579 switch (hw->device_id) {
580 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
583 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
587 ret_val = IXGBE_ERR_PHY;
592 * Find the matching sfp ID in the EEPROM
593 * and program the init sequence
595 hw->eeprom.ops.read(hw, list_offset, &id);
597 while (!((id == IXGBE_CONTROL_EOL_NL) || (end_data == TRUE))) {
600 hw->eeprom.ops.read(hw, list_offset, &data_offset);
601 if ((!data_offset) || (data_offset == 0xFFFF))
603 ret_val = hw->eeprom.ops.read(hw, data_offset,
608 * Read control word from PHY init contents
611 ret_val = hw->eeprom.ops.read(hw, data_offset,
613 control = (eword & IXGBE_CONTROL_MASK_NL) >>
614 IXGBE_CONTROL_SHIFT_NL;
615 edata = eword & IXGBE_DATA_MASK_NL;
619 DEBUGOUT1("DELAY: %d MS\n", edata);
623 DEBUGOUT("DATA: \n");
625 hw->eeprom.ops.read(hw, data_offset++,
627 for (i = 0; i < edata; i++) {
628 hw->eeprom.ops.read(hw,
631 hw->phy.ops.write_reg(hw,
635 DEBUGOUT2("Wrote %4.4x to %4.4x\n",
641 case IXGBE_CONTROL_NL:
643 DEBUGOUT("CONTROL: \n");
644 if (edata == IXGBE_CONTROL_EOL_NL) {
647 } else if (edata == IXGBE_CONTROL_SOL_NL) {
650 DEBUGOUT("Bad control value\n");
651 ret_val = IXGBE_ERR_PHY;
656 DEBUGOUT("Bad control type\n");
657 ret_val = IXGBE_ERR_PHY;
663 ret_val = hw->eeprom.ops.read(hw, list_offset, &id);