1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
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17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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31 POSSIBILITY OF SUCH DAMAGE.
33 ******************************************************************************/
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
42 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
45 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
55 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
56 * @hw: pointer to the hardware structure
59 * Returns an error code on error.
61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
65 status = ixgbe_clock_out_i2c_byte(hw, byte);
68 return ixgbe_get_i2c_ack(hw);
72 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
73 * @hw: pointer to the hardware structure
74 * @byte: pointer to a u8 to receive the byte
76 * Returns an error code on error.
78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 ixgbe_clock_in_i2c_byte(hw, byte);
82 return ixgbe_clock_out_i2c_bit(hw, false);
86 * ixgbe_ones_comp_byte_add - Perform one's complement addition
90 * Returns one's complement 8-bit sum.
92 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
94 u16 sum = add1 + add2;
96 sum = (sum & 0xFF) + (sum >> 8);
101 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
102 * @hw: pointer to the hardware structure
103 * @addr: I2C bus address to read from
104 * @reg: I2C device register to read from
105 * @val: pointer to location to receive read value
106 * @lock: true if to take and release semaphore
108 * Returns an error code on error.
110 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
113 u32 swfw_mask = hw->phy.phy_semaphore_mask;
122 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
123 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
127 return IXGBE_ERR_SWFW_SYNC;
129 /* Device Address and write indication */
130 if (ixgbe_out_i2c_byte_ack(hw, addr))
132 /* Write bits 14:8 */
133 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 if (ixgbe_out_i2c_byte_ack(hw, csum))
141 /* Re-start condition */
143 /* Device Address and read indication */
144 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
155 if (ixgbe_clock_out_i2c_bit(hw, false))
159 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
160 *val = (high_bits << 8) | low_bits;
164 ixgbe_i2c_bus_clear(hw);
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
167 if (retry < max_retry)
168 DEBUGOUT("I2C byte read combined error - Retrying.\n");
170 DEBUGOUT("I2C byte read combined error.\n");
172 } while (retry <= max_retry);
174 return IXGBE_ERR_I2C;
178 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
179 * @hw: pointer to the hardware structure
180 * @addr: I2C bus address to write to
181 * @reg: I2C device register to write to
182 * @val: value to write
183 * @lock: true if to take and release semaphore
185 * Returns an error code on error.
187 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
190 u32 swfw_mask = hw->phy.phy_semaphore_mask;
196 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
197 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
198 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
199 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
202 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
203 return IXGBE_ERR_SWFW_SYNC;
205 /* Device Address and write indication */
206 if (ixgbe_out_i2c_byte_ack(hw, addr))
208 /* Write bits 14:8 */
209 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
212 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
214 /* Write data 15:8 */
215 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
218 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
221 if (ixgbe_out_i2c_byte_ack(hw, csum))
225 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
229 ixgbe_i2c_bus_clear(hw);
231 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
232 if (retry < max_retry)
233 DEBUGOUT("I2C byte write combined error - Retrying.\n");
235 DEBUGOUT("I2C byte write combined error.\n");
237 } while (retry <= max_retry);
239 return IXGBE_ERR_I2C;
243 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
244 * @hw: pointer to the hardware structure
246 * Initialize the function pointers.
248 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
250 struct ixgbe_phy_info *phy = &hw->phy;
252 DEBUGFUNC("ixgbe_init_phy_ops_generic");
255 phy->ops.identify = ixgbe_identify_phy_generic;
256 phy->ops.reset = ixgbe_reset_phy_generic;
257 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
258 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
259 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
260 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
261 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
262 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
263 phy->ops.check_link = NULL;
264 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
265 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
266 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
267 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
268 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
269 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
270 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
271 phy->ops.identify_sfp = ixgbe_identify_module_generic;
272 phy->sfp_type = ixgbe_sfp_type_unknown;
273 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
274 phy->ops.write_i2c_byte_unlocked =
275 ixgbe_write_i2c_byte_generic_unlocked;
276 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
277 return IXGBE_SUCCESS;
281 * ixgbe_probe_phy - Probe a single address for a PHY
282 * @hw: pointer to hardware structure
283 * @phy_addr: PHY address to probe
285 * Returns true if PHY found
287 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
291 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
292 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
297 if (ixgbe_get_phy_id(hw))
300 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
302 if (hw->phy.type == ixgbe_phy_unknown) {
303 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
304 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
306 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
307 IXGBE_MDIO_PHY_1000BASET_ABILITY))
308 hw->phy.type = ixgbe_phy_cu_unknown;
310 hw->phy.type = ixgbe_phy_generic;
317 * ixgbe_identify_phy_generic - Get physical layer module
318 * @hw: pointer to hardware structure
320 * Determines the physical layer module found on the current adapter.
322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
324 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
327 DEBUGFUNC("ixgbe_identify_phy_generic");
329 if (!hw->phy.phy_semaphore_mask) {
331 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
333 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
336 if (hw->phy.type != ixgbe_phy_unknown)
337 return IXGBE_SUCCESS;
339 if (hw->phy.nw_mng_if_sel) {
340 phy_addr = (hw->phy.nw_mng_if_sel &
341 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
342 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
343 if (ixgbe_probe_phy(hw, phy_addr))
344 return IXGBE_SUCCESS;
346 return IXGBE_ERR_PHY_ADDR_INVALID;
349 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
350 if (ixgbe_probe_phy(hw, phy_addr)) {
351 status = IXGBE_SUCCESS;
356 /* Certain media types do not have a phy so an address will not
357 * be found and the code will take this path. Caller has to
358 * decide if it is an error or not.
360 if (status != IXGBE_SUCCESS)
367 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
368 * @hw: pointer to the hardware structure
370 * This function checks the MMNGC.MNG_VETO bit to see if there are
371 * any constraints on link from manageability. For MAC's that don't
372 * have this bit just return faluse since the link can not be blocked
375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
379 DEBUGFUNC("ixgbe_check_reset_blocked");
381 /* If we don't have this bit, it can't be blocking */
382 if (hw->mac.type == ixgbe_mac_82598EB)
385 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
386 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
387 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
388 "MNG_VETO bit detected.\n");
396 * ixgbe_validate_phy_addr - Determines phy address is valid
397 * @hw: pointer to hardware structure
398 * @phy_addr: PHY address
401 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
406 DEBUGFUNC("ixgbe_validate_phy_addr");
408 hw->phy.addr = phy_addr;
409 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
410 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
412 if (phy_id != 0xFFFF && phy_id != 0x0)
415 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
421 * ixgbe_get_phy_id - Get the phy type
422 * @hw: pointer to hardware structure
425 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
431 DEBUGFUNC("ixgbe_get_phy_id");
433 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
434 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
437 if (status == IXGBE_SUCCESS) {
438 hw->phy.id = (u32)(phy_id_high << 16);
439 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
440 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
442 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
443 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
445 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
446 phy_id_high, phy_id_low);
452 * ixgbe_get_phy_type_from_id - Get the phy type
453 * @phy_id: PHY ID information
456 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
458 enum ixgbe_phy_type phy_type;
460 DEBUGFUNC("ixgbe_get_phy_type_from_id");
464 phy_type = ixgbe_phy_tn;
469 phy_type = ixgbe_phy_aq;
472 phy_type = ixgbe_phy_qt;
475 phy_type = ixgbe_phy_nl;
479 phy_type = ixgbe_phy_x550em_ext_t;
481 case IXGBE_M88E1500_E_PHY_ID:
482 case IXGBE_M88E1543_E_PHY_ID:
483 phy_type = ixgbe_phy_ext_1g_t;
486 phy_type = ixgbe_phy_unknown;
493 * ixgbe_reset_phy_generic - Performs a PHY reset
494 * @hw: pointer to hardware structure
496 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
500 s32 status = IXGBE_SUCCESS;
502 DEBUGFUNC("ixgbe_reset_phy_generic");
504 if (hw->phy.type == ixgbe_phy_unknown)
505 status = ixgbe_identify_phy_generic(hw);
507 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
510 /* Don't reset PHY if it's shut down due to overtemp. */
511 if (!hw->phy.reset_if_overtemp &&
512 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
515 /* Blocked by MNG FW so bail */
516 if (ixgbe_check_reset_blocked(hw))
520 * Perform soft PHY reset to the PHY_XS.
521 * This will cause a soft reset to the PHY
523 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
524 IXGBE_MDIO_PHY_XS_DEV_TYPE,
525 IXGBE_MDIO_PHY_XS_RESET);
528 * Poll for reset bit to self-clear indicating reset is complete.
529 * Some PHYs could take up to 3 seconds to complete and need about
530 * 1.7 usec delay after the reset is complete.
532 for (i = 0; i < 30; i++) {
534 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
535 status = hw->phy.ops.read_reg(hw,
536 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
537 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
539 if (status != IXGBE_SUCCESS)
542 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
547 status = hw->phy.ops.read_reg(hw,
548 IXGBE_MDIO_PHY_XS_CONTROL,
549 IXGBE_MDIO_PHY_XS_DEV_TYPE,
551 if (status != IXGBE_SUCCESS)
554 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
561 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
562 status = IXGBE_ERR_RESET_FAILED;
563 ERROR_REPORT1(IXGBE_ERROR_POLLING,
564 "PHY reset polling failed to complete.\n");
572 * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
573 * @hw: pointer to hardware structure
575 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
579 /* Check if PHY reset is blocked by MNG FW */
580 if (ixgbe_check_reset_blocked(hw))
583 /* Restart PHY auto-negotiation. */
584 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
585 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
586 autoneg_reg |= IXGBE_MII_RESTART;
587 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
588 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
592 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
594 * @hw: pointer to hardware structure
595 * @reg_addr: 32 bit address of PHY register to read
596 * @device_type: 5 bit device type
597 * @phy_data: Pointer to read data from PHY register
599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
602 u32 i, data, command;
604 /* Setup and write the address cycle command */
605 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
606 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
607 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
608 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
610 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
613 * Check every 10 usec to see if the address cycle completed.
614 * The MDI Command bit will clear when the operation is
617 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
620 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
621 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
626 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
627 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
628 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
629 return IXGBE_ERR_PHY;
633 * Address cycle complete, setup and write the read
636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
644 * Check every 10 usec to see if the address cycle
645 * completed. The MDI Command bit will clear when the
646 * operation is complete
648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
651 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
658 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
659 return IXGBE_ERR_PHY;
663 * Read operation is complete. Get the data
666 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
667 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
668 *phy_data = (u16)(data);
670 return IXGBE_SUCCESS;
674 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
675 * using the SWFW lock - this function is needed in most cases
676 * @hw: pointer to hardware structure
677 * @reg_addr: 32 bit address of PHY register to read
678 * @device_type: 5 bit device type
679 * @phy_data: Pointer to read data from PHY register
681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
682 u32 device_type, u16 *phy_data)
685 u32 gssr = hw->phy.phy_semaphore_mask;
687 DEBUGFUNC("ixgbe_read_phy_reg_generic");
689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
690 return IXGBE_ERR_SWFW_SYNC;
692 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
694 hw->mac.ops.release_swfw_sync(hw, gssr);
700 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
702 * @hw: pointer to hardware structure
703 * @reg_addr: 32 bit PHY register to write
704 * @device_type: 5 bit device type
705 * @phy_data: Data to write to the PHY register
707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
708 u32 device_type, u16 phy_data)
712 /* Put the data in the MDI single read and write data register*/
713 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
715 /* Setup and write the address cycle command */
716 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
717 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
718 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
719 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
721 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
724 * Check every 10 usec to see if the address cycle completed.
725 * The MDI Command bit will clear when the operation is
728 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
731 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
732 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
736 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
737 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
738 return IXGBE_ERR_PHY;
742 * Address cycle complete, setup and write the write
745 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
746 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
747 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
748 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
750 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
753 * Check every 10 usec to see if the address cycle
754 * completed. The MDI Command bit will clear when the
755 * operation is complete
757 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
760 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
761 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
765 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
766 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
767 return IXGBE_ERR_PHY;
770 return IXGBE_SUCCESS;
774 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
775 * using SWFW lock- this function is needed in most cases
776 * @hw: pointer to hardware structure
777 * @reg_addr: 32 bit PHY register to write
778 * @device_type: 5 bit device type
779 * @phy_data: Data to write to the PHY register
781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
782 u32 device_type, u16 phy_data)
785 u32 gssr = hw->phy.phy_semaphore_mask;
787 DEBUGFUNC("ixgbe_write_phy_reg_generic");
789 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
790 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
792 hw->mac.ops.release_swfw_sync(hw, gssr);
794 status = IXGBE_ERR_SWFW_SYNC;
801 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
802 * @hw: pointer to hardware structure
804 * Restart auto-negotiation and PHY and waits for completion.
806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
808 s32 status = IXGBE_SUCCESS;
809 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
810 bool autoneg = false;
811 ixgbe_link_speed speed;
813 DEBUGFUNC("ixgbe_setup_phy_link_generic");
815 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
817 /* Set or unset auto-negotiation 10G advertisement */
818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
823 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
824 (speed & IXGBE_LINK_SPEED_10GB_FULL))
825 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
827 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
828 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
832 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
835 if (hw->mac.type == ixgbe_mac_X550) {
836 /* Set or unset auto-negotiation 5G advertisement */
837 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
838 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
839 (speed & IXGBE_LINK_SPEED_5GB_FULL))
840 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
842 /* Set or unset auto-negotiation 2.5G advertisement */
843 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
844 if ((hw->phy.autoneg_advertised &
845 IXGBE_LINK_SPEED_2_5GB_FULL) &&
846 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
847 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
850 /* Set or unset auto-negotiation 1G advertisement */
851 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
852 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
853 (speed & IXGBE_LINK_SPEED_1GB_FULL))
854 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
856 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
857 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
860 /* Set or unset auto-negotiation 100M advertisement */
861 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
862 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
865 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
866 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
867 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
868 (speed & IXGBE_LINK_SPEED_100_FULL))
869 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
871 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
872 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
875 ixgbe_restart_auto_neg(hw);
880 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
881 * @hw: pointer to hardware structure
882 * @speed: new link speed
883 * @autoneg_wait_to_complete: unused
885 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
886 ixgbe_link_speed speed,
887 bool autoneg_wait_to_complete)
889 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
891 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
894 * Clear autoneg_advertised and set new values based on input link
897 hw->phy.autoneg_advertised = 0;
899 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
902 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
903 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
905 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
908 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
911 if (speed & IXGBE_LINK_SPEED_100_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
914 if (speed & IXGBE_LINK_SPEED_10_FULL)
915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
917 /* Setup link based on the new speed settings */
918 ixgbe_setup_phy_link(hw);
920 return IXGBE_SUCCESS;
924 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
925 * @hw: pointer to hardware structure
927 * Determines the supported link capabilities by reading the PHY auto
928 * negotiation register.
930 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
936 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
941 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
942 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
943 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
944 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
945 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
948 switch (hw->mac.type) {
950 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
951 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
953 case ixgbe_mac_X550EM_x:
954 case ixgbe_mac_X550EM_a:
955 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
965 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
966 * @hw: pointer to hardware structure
967 * @speed: pointer to link speed
968 * @autoneg: boolean auto-negotiation value
970 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
971 ixgbe_link_speed *speed,
974 s32 status = IXGBE_SUCCESS;
976 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
979 if (!hw->phy.speeds_supported)
980 status = ixgbe_get_copper_speeds_supported(hw);
982 *speed = hw->phy.speeds_supported;
987 * ixgbe_check_phy_link_tnx - Determine link and speed status
988 * @hw: pointer to hardware structure
989 * @speed: current link speed
990 * @link_up: true is link is up, false otherwise
992 * Reads the VS1 register to determine if link is up and the current speed for
995 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
998 s32 status = IXGBE_SUCCESS;
1000 u32 max_time_out = 10;
1005 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1007 /* Initialize speed and link to default case */
1009 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1012 * Check current speed and link status of the PHY register.
1013 * This is a vendor specific register and may have to
1014 * be changed for other copper PHYs.
1016 for (time_out = 0; time_out < max_time_out; time_out++) {
1018 status = hw->phy.ops.read_reg(hw,
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1020 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1022 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1023 phy_speed = phy_data &
1024 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1025 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1028 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1029 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1038 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1039 * @hw: pointer to hardware structure
1041 * Restart auto-negotiation and PHY and waits for completion.
1043 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1045 s32 status = IXGBE_SUCCESS;
1046 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1047 bool autoneg = false;
1048 ixgbe_link_speed speed;
1050 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1052 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1054 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1055 /* Set or unset auto-negotiation 10G advertisement */
1056 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1057 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1060 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1061 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1062 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1064 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1065 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1069 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1070 /* Set or unset auto-negotiation 1G advertisement */
1071 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1072 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1075 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1076 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1077 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1079 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1080 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1084 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1085 /* Set or unset auto-negotiation 100M advertisement */
1086 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1087 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1090 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1091 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1092 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1094 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1095 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1099 ixgbe_restart_auto_neg(hw);
1104 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1105 * @hw: pointer to hardware structure
1106 * @firmware_version: pointer to the PHY Firmware Version
1108 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1109 u16 *firmware_version)
1113 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1115 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1116 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1123 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1124 * @hw: pointer to hardware structure
1125 * @firmware_version: pointer to the PHY Firmware Version
1127 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1128 u16 *firmware_version)
1132 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1134 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1135 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1142 * ixgbe_reset_phy_nl - Performs a PHY reset
1143 * @hw: pointer to hardware structure
1145 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1147 u16 phy_offset, control, eword, edata, block_crc;
1148 bool end_data = false;
1149 u16 list_offset, data_offset;
1151 s32 ret_val = IXGBE_SUCCESS;
1154 DEBUGFUNC("ixgbe_reset_phy_nl");
1156 /* Blocked by MNG FW so bail */
1157 if (ixgbe_check_reset_blocked(hw))
1160 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1161 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1163 /* reset the PHY and poll for completion */
1164 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1165 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1166 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1168 for (i = 0; i < 100; i++) {
1169 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1171 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1176 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1177 DEBUGOUT("PHY reset did not complete.\n");
1178 ret_val = IXGBE_ERR_PHY;
1182 /* Get init offsets */
1183 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1185 if (ret_val != IXGBE_SUCCESS)
1188 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192 * Read control word from PHY init contents offset
1194 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1197 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1198 IXGBE_CONTROL_SHIFT_NL;
1199 edata = eword & IXGBE_DATA_MASK_NL;
1201 case IXGBE_DELAY_NL:
1203 DEBUGOUT1("DELAY: %d MS\n", edata);
1207 DEBUGOUT("DATA:\n");
1209 ret_val = hw->eeprom.ops.read(hw, data_offset,
1214 for (i = 0; i < edata; i++) {
1215 ret_val = hw->eeprom.ops.read(hw, data_offset,
1219 hw->phy.ops.write_reg(hw, phy_offset,
1220 IXGBE_TWINAX_DEV, eword);
1221 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1227 case IXGBE_CONTROL_NL:
1229 DEBUGOUT("CONTROL:\n");
1230 if (edata == IXGBE_CONTROL_EOL_NL) {
1233 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1236 DEBUGOUT("Bad control value\n");
1237 ret_val = IXGBE_ERR_PHY;
1242 DEBUGOUT("Bad control type\n");
1243 ret_val = IXGBE_ERR_PHY;
1252 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1253 "eeprom read at offset %d failed", data_offset);
1254 return IXGBE_ERR_PHY;
1258 * ixgbe_identify_module_generic - Identifies module type
1259 * @hw: pointer to hardware structure
1261 * Determines HW type and calls appropriate function.
1263 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1265 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1267 DEBUGFUNC("ixgbe_identify_module_generic");
1269 switch (hw->mac.ops.get_media_type(hw)) {
1270 case ixgbe_media_type_fiber:
1271 status = ixgbe_identify_sfp_module_generic(hw);
1274 case ixgbe_media_type_fiber_qsfp:
1275 status = ixgbe_identify_qsfp_module_generic(hw);
1279 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1280 status = IXGBE_ERR_SFP_NOT_PRESENT;
1288 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1289 * @hw: pointer to hardware structure
1291 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1293 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1295 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1297 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1299 u8 comp_codes_1g = 0;
1300 u8 comp_codes_10g = 0;
1301 u8 oui_bytes[3] = {0, 0, 0};
1304 u16 enforce_sfp = 0;
1306 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1308 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1309 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1310 status = IXGBE_ERR_SFP_NOT_PRESENT;
1314 /* LAN ID is needed for I2C access */
1315 hw->mac.ops.set_lan_id(hw);
1317 status = hw->phy.ops.read_i2c_eeprom(hw,
1318 IXGBE_SFF_IDENTIFIER,
1321 if (status != IXGBE_SUCCESS)
1322 goto err_read_i2c_eeprom;
1324 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1325 hw->phy.type = ixgbe_phy_sfp_unsupported;
1326 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1328 status = hw->phy.ops.read_i2c_eeprom(hw,
1329 IXGBE_SFF_1GBE_COMP_CODES,
1332 if (status != IXGBE_SUCCESS)
1333 goto err_read_i2c_eeprom;
1335 status = hw->phy.ops.read_i2c_eeprom(hw,
1336 IXGBE_SFF_10GBE_COMP_CODES,
1339 if (status != IXGBE_SUCCESS)
1340 goto err_read_i2c_eeprom;
1341 status = hw->phy.ops.read_i2c_eeprom(hw,
1342 IXGBE_SFF_CABLE_TECHNOLOGY,
1345 if (status != IXGBE_SUCCESS)
1346 goto err_read_i2c_eeprom;
1353 * 3 SFP_DA_CORE0 - 82599-specific
1354 * 4 SFP_DA_CORE1 - 82599-specific
1355 * 5 SFP_SR/LR_CORE0 - 82599-specific
1356 * 6 SFP_SR/LR_CORE1 - 82599-specific
1357 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1358 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1359 * 9 SFP_1g_cu_CORE0 - 82599-specific
1360 * 10 SFP_1g_cu_CORE1 - 82599-specific
1361 * 11 SFP_1g_sx_CORE0 - 82599-specific
1362 * 12 SFP_1g_sx_CORE1 - 82599-specific
1364 if (hw->mac.type == ixgbe_mac_82598EB) {
1365 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1366 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1367 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1368 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1369 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1370 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1372 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1374 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1375 if (hw->bus.lan_id == 0)
1377 ixgbe_sfp_type_da_cu_core0;
1380 ixgbe_sfp_type_da_cu_core1;
1381 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1382 hw->phy.ops.read_i2c_eeprom(
1383 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1386 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1387 if (hw->bus.lan_id == 0)
1389 ixgbe_sfp_type_da_act_lmt_core0;
1392 ixgbe_sfp_type_da_act_lmt_core1;
1395 ixgbe_sfp_type_unknown;
1397 } else if (comp_codes_10g &
1398 (IXGBE_SFF_10GBASESR_CAPABLE |
1399 IXGBE_SFF_10GBASELR_CAPABLE)) {
1400 if (hw->bus.lan_id == 0)
1402 ixgbe_sfp_type_srlr_core0;
1405 ixgbe_sfp_type_srlr_core1;
1406 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1407 if (hw->bus.lan_id == 0)
1409 ixgbe_sfp_type_1g_cu_core0;
1412 ixgbe_sfp_type_1g_cu_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1416 ixgbe_sfp_type_1g_sx_core0;
1419 ixgbe_sfp_type_1g_sx_core1;
1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1421 if (hw->bus.lan_id == 0)
1423 ixgbe_sfp_type_1g_lx_core0;
1426 ixgbe_sfp_type_1g_lx_core1;
1428 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1432 if (hw->phy.sfp_type != stored_sfp_type)
1433 hw->phy.sfp_setup_needed = true;
1435 /* Determine if the SFP+ PHY is dual speed or not. */
1436 hw->phy.multispeed_fiber = false;
1437 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1438 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1439 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1440 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1441 hw->phy.multispeed_fiber = true;
1443 /* Determine PHY vendor */
1444 if (hw->phy.type != ixgbe_phy_nl) {
1445 hw->phy.id = identifier;
1446 status = hw->phy.ops.read_i2c_eeprom(hw,
1447 IXGBE_SFF_VENDOR_OUI_BYTE0,
1450 if (status != IXGBE_SUCCESS)
1451 goto err_read_i2c_eeprom;
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE1,
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1460 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 IXGBE_SFF_VENDOR_OUI_BYTE2,
1464 if (status != IXGBE_SUCCESS)
1465 goto err_read_i2c_eeprom;
1468 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1469 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1470 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1472 switch (vendor_oui) {
1473 case IXGBE_SFF_VENDOR_OUI_TYCO:
1474 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1476 ixgbe_phy_sfp_passive_tyco;
1478 case IXGBE_SFF_VENDOR_OUI_FTL:
1479 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1480 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1482 hw->phy.type = ixgbe_phy_sfp_ftl;
1484 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1485 hw->phy.type = ixgbe_phy_sfp_avago;
1487 case IXGBE_SFF_VENDOR_OUI_INTEL:
1488 hw->phy.type = ixgbe_phy_sfp_intel;
1491 hw->phy.type = ixgbe_phy_sfp_unknown;
1496 /* Allow any DA cable vendor */
1497 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1498 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1499 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1503 status = IXGBE_SUCCESS;
1507 /* Verify supported 1G SFP modules */
1508 if (comp_codes_10g == 0 &&
1509 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1510 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1511 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1512 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1513 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1514 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1515 hw->phy.type = ixgbe_phy_sfp_unsupported;
1516 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1520 /* Anything else 82598-based is supported */
1521 if (hw->mac.type == ixgbe_mac_82598EB) {
1522 status = IXGBE_SUCCESS;
1526 ixgbe_get_device_caps(hw, &enforce_sfp);
1527 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1528 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1529 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1530 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1532 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1533 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1534 /* Make sure we're a supported PHY type */
1535 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1536 status = IXGBE_SUCCESS;
1538 if (hw->allow_unsupported_sfp == true) {
1539 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1540 status = IXGBE_SUCCESS;
1542 DEBUGOUT("SFP+ module not supported\n");
1544 ixgbe_phy_sfp_unsupported;
1545 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1549 status = IXGBE_SUCCESS;
1556 err_read_i2c_eeprom:
1557 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1558 if (hw->phy.type != ixgbe_phy_nl) {
1560 hw->phy.type = ixgbe_phy_unknown;
1562 return IXGBE_ERR_SFP_NOT_PRESENT;
1566 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1567 * @hw: pointer to hardware structure
1569 * Determines physical layer capabilities of the current SFP.
1571 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1573 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1574 u8 comp_codes_10g = 0;
1575 u8 comp_codes_1g = 0;
1577 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1579 hw->phy.ops.identify_sfp(hw);
1580 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1581 return physical_layer;
1583 switch (hw->phy.type) {
1584 case ixgbe_phy_sfp_passive_tyco:
1585 case ixgbe_phy_sfp_passive_unknown:
1586 case ixgbe_phy_qsfp_passive_unknown:
1587 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1589 case ixgbe_phy_sfp_ftl_active:
1590 case ixgbe_phy_sfp_active_unknown:
1591 case ixgbe_phy_qsfp_active_unknown:
1592 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1594 case ixgbe_phy_sfp_avago:
1595 case ixgbe_phy_sfp_ftl:
1596 case ixgbe_phy_sfp_intel:
1597 case ixgbe_phy_sfp_unknown:
1598 hw->phy.ops.read_i2c_eeprom(hw,
1599 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1600 hw->phy.ops.read_i2c_eeprom(hw,
1601 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1602 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1603 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1604 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1605 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1606 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1607 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1608 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1609 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1611 case ixgbe_phy_qsfp_intel:
1612 case ixgbe_phy_qsfp_unknown:
1613 hw->phy.ops.read_i2c_eeprom(hw,
1614 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1615 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1616 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1617 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1618 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1624 return physical_layer;
1628 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1629 * @hw: pointer to hardware structure
1631 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1633 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1635 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1637 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1639 u8 comp_codes_1g = 0;
1640 u8 comp_codes_10g = 0;
1641 u8 oui_bytes[3] = {0, 0, 0};
1642 u16 enforce_sfp = 0;
1644 u8 cable_length = 0;
1646 bool active_cable = false;
1648 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1650 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1651 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1652 status = IXGBE_ERR_SFP_NOT_PRESENT;
1656 /* LAN ID is needed for I2C access */
1657 hw->mac.ops.set_lan_id(hw);
1659 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1662 if (status != IXGBE_SUCCESS)
1663 goto err_read_i2c_eeprom;
1665 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1666 hw->phy.type = ixgbe_phy_sfp_unsupported;
1667 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1671 hw->phy.id = identifier;
1673 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1676 if (status != IXGBE_SUCCESS)
1677 goto err_read_i2c_eeprom;
1679 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1682 if (status != IXGBE_SUCCESS)
1683 goto err_read_i2c_eeprom;
1685 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1686 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1687 if (hw->bus.lan_id == 0)
1688 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1690 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1691 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1692 IXGBE_SFF_10GBASELR_CAPABLE)) {
1693 if (hw->bus.lan_id == 0)
1694 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1696 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1698 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1699 active_cable = true;
1701 if (!active_cable) {
1702 /* check for active DA cables that pre-date
1704 hw->phy.ops.read_i2c_eeprom(hw,
1705 IXGBE_SFF_QSFP_CONNECTOR,
1708 hw->phy.ops.read_i2c_eeprom(hw,
1709 IXGBE_SFF_QSFP_CABLE_LENGTH,
1712 hw->phy.ops.read_i2c_eeprom(hw,
1713 IXGBE_SFF_QSFP_DEVICE_TECH,
1717 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1718 (cable_length > 0) &&
1719 ((device_tech >> 4) ==
1720 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1721 active_cable = true;
1725 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1726 if (hw->bus.lan_id == 0)
1728 ixgbe_sfp_type_da_act_lmt_core0;
1731 ixgbe_sfp_type_da_act_lmt_core1;
1733 /* unsupported module type */
1734 hw->phy.type = ixgbe_phy_sfp_unsupported;
1735 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1740 if (hw->phy.sfp_type != stored_sfp_type)
1741 hw->phy.sfp_setup_needed = true;
1743 /* Determine if the QSFP+ PHY is dual speed or not. */
1744 hw->phy.multispeed_fiber = false;
1745 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1746 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1747 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1748 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1749 hw->phy.multispeed_fiber = true;
1751 /* Determine PHY vendor for optical modules */
1752 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1753 IXGBE_SFF_10GBASELR_CAPABLE)) {
1754 status = hw->phy.ops.read_i2c_eeprom(hw,
1755 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1758 if (status != IXGBE_SUCCESS)
1759 goto err_read_i2c_eeprom;
1761 status = hw->phy.ops.read_i2c_eeprom(hw,
1762 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1765 if (status != IXGBE_SUCCESS)
1766 goto err_read_i2c_eeprom;
1768 status = hw->phy.ops.read_i2c_eeprom(hw,
1769 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1772 if (status != IXGBE_SUCCESS)
1773 goto err_read_i2c_eeprom;
1776 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1777 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1778 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1780 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1781 hw->phy.type = ixgbe_phy_qsfp_intel;
1783 hw->phy.type = ixgbe_phy_qsfp_unknown;
1785 ixgbe_get_device_caps(hw, &enforce_sfp);
1786 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1787 /* Make sure we're a supported PHY type */
1788 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1789 status = IXGBE_SUCCESS;
1791 if (hw->allow_unsupported_sfp == true) {
1792 EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1793 status = IXGBE_SUCCESS;
1795 DEBUGOUT("QSFP module not supported\n");
1797 ixgbe_phy_sfp_unsupported;
1798 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1802 status = IXGBE_SUCCESS;
1809 err_read_i2c_eeprom:
1810 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1812 hw->phy.type = ixgbe_phy_unknown;
1814 return IXGBE_ERR_SFP_NOT_PRESENT;
1818 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1819 * @hw: pointer to hardware structure
1820 * @list_offset: offset to the SFP ID list
1821 * @data_offset: offset to the SFP data block
1823 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1824 * so it returns the offsets to the phy init sequence block.
1826 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1831 u16 sfp_type = hw->phy.sfp_type;
1833 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1835 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1836 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1838 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1839 return IXGBE_ERR_SFP_NOT_PRESENT;
1841 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1842 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1843 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1846 * Limiting active cables and 1G Phys must be initialized as
1849 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1850 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1851 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1852 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1853 sfp_type = ixgbe_sfp_type_srlr_core0;
1854 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1855 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1856 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1857 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1858 sfp_type = ixgbe_sfp_type_srlr_core1;
1860 /* Read offset to PHY init contents */
1861 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1862 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1863 "eeprom read at offset %d failed",
1864 IXGBE_PHY_INIT_OFFSET_NL);
1865 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1868 if ((!*list_offset) || (*list_offset == 0xFFFF))
1869 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1871 /* Shift offset to first ID word */
1875 * Find the matching SFP ID in the EEPROM
1876 * and program the init sequence
1878 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1881 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1882 if (sfp_id == sfp_type) {
1884 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1886 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1887 DEBUGOUT("SFP+ module not supported\n");
1888 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1893 (*list_offset) += 2;
1894 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1899 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1900 DEBUGOUT("No matching SFP+ module found\n");
1901 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1904 return IXGBE_SUCCESS;
1907 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1908 "eeprom read at offset %d failed", *list_offset);
1909 return IXGBE_ERR_PHY;
1913 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1914 * @hw: pointer to hardware structure
1915 * @byte_offset: EEPROM byte offset to read
1916 * @eeprom_data: value read
1918 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1920 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1923 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1925 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1926 IXGBE_I2C_EEPROM_DEV_ADDR,
1931 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1932 * @hw: pointer to hardware structure
1933 * @byte_offset: byte offset at address 0xA2
1934 * @sff8472_data: value read
1936 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1938 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1941 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942 IXGBE_I2C_EEPROM_DEV_ADDR2,
1947 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1948 * @hw: pointer to hardware structure
1949 * @byte_offset: EEPROM byte offset to write
1950 * @eeprom_data: value to write
1952 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1954 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1957 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1959 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1960 IXGBE_I2C_EEPROM_DEV_ADDR,
1965 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1966 * @hw: pointer to hardware structure
1967 * @offset: eeprom offset to be read
1968 * @addr: I2C address to be read
1970 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1972 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1973 offset == IXGBE_SFF_IDENTIFIER &&
1974 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1980 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1981 * @hw: pointer to hardware structure
1982 * @byte_offset: byte offset to read
1983 * @dev_addr: address to read from
1985 * @lock: true if to take and release semaphore
1987 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1988 * a specified device address.
1990 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1991 u8 dev_addr, u8 *data, bool lock)
1996 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2000 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2002 if (hw->mac.type >= ixgbe_mac_X550)
2004 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2005 max_retry = IXGBE_SFP_DETECT_RETRIES;
2008 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2009 return IXGBE_ERR_SWFW_SYNC;
2011 ixgbe_i2c_start(hw);
2013 /* Device Address and write indication */
2014 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2015 if (status != IXGBE_SUCCESS)
2018 status = ixgbe_get_i2c_ack(hw);
2019 if (status != IXGBE_SUCCESS)
2022 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2023 if (status != IXGBE_SUCCESS)
2026 status = ixgbe_get_i2c_ack(hw);
2027 if (status != IXGBE_SUCCESS)
2030 ixgbe_i2c_start(hw);
2032 /* Device Address and read indication */
2033 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2034 if (status != IXGBE_SUCCESS)
2037 status = ixgbe_get_i2c_ack(hw);
2038 if (status != IXGBE_SUCCESS)
2041 ixgbe_clock_in_i2c_byte(hw, data);
2043 status = ixgbe_clock_out_i2c_bit(hw, nack);
2044 if (status != IXGBE_SUCCESS)
2049 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2050 return IXGBE_SUCCESS;
2053 ixgbe_i2c_bus_clear(hw);
2055 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2058 if (retry < max_retry)
2059 DEBUGOUT("I2C byte read error - Retrying.\n");
2061 DEBUGOUT("I2C byte read error.\n");
2063 } while (retry <= max_retry);
2069 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2070 * @hw: pointer to hardware structure
2071 * @byte_offset: byte offset to read
2072 * @dev_addr: address to read from
2075 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2076 * a specified device address.
2078 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2079 u8 dev_addr, u8 *data)
2081 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2086 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2087 * @hw: pointer to hardware structure
2088 * @byte_offset: byte offset to read
2089 * @dev_addr: address to read from
2092 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2093 * a specified device address.
2095 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2096 u8 dev_addr, u8 *data)
2098 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2103 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2104 * @hw: pointer to hardware structure
2105 * @byte_offset: byte offset to write
2106 * @dev_addr: address to write to
2107 * @data: value to write
2108 * @lock: true if to take and release semaphore
2110 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2111 * a specified device address.
2113 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2114 u8 dev_addr, u8 data, bool lock)
2119 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2121 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2123 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2125 return IXGBE_ERR_SWFW_SYNC;
2128 ixgbe_i2c_start(hw);
2130 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2131 if (status != IXGBE_SUCCESS)
2134 status = ixgbe_get_i2c_ack(hw);
2135 if (status != IXGBE_SUCCESS)
2138 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2139 if (status != IXGBE_SUCCESS)
2142 status = ixgbe_get_i2c_ack(hw);
2143 if (status != IXGBE_SUCCESS)
2146 status = ixgbe_clock_out_i2c_byte(hw, data);
2147 if (status != IXGBE_SUCCESS)
2150 status = ixgbe_get_i2c_ack(hw);
2151 if (status != IXGBE_SUCCESS)
2156 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2157 return IXGBE_SUCCESS;
2160 ixgbe_i2c_bus_clear(hw);
2161 if (retry < max_retry)
2162 DEBUGOUT("I2C byte write error - Retrying.\n");
2164 DEBUGOUT("I2C byte write error.\n");
2166 } while (retry <= max_retry);
2169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2175 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2176 * @hw: pointer to hardware structure
2177 * @byte_offset: byte offset to write
2178 * @dev_addr: address to write to
2179 * @data: value to write
2181 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2182 * a specified device address.
2184 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2185 u8 dev_addr, u8 data)
2187 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2192 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2193 * @hw: pointer to hardware structure
2194 * @byte_offset: byte offset to write
2195 * @dev_addr: address to write to
2196 * @data: value to write
2198 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2199 * a specified device address.
2201 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2202 u8 dev_addr, u8 data)
2204 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2209 * ixgbe_i2c_start - Sets I2C start condition
2210 * @hw: pointer to hardware structure
2212 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2213 * Set bit-bang mode on X550 hardware.
2215 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2217 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2219 DEBUGFUNC("ixgbe_i2c_start");
2221 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2223 /* Start condition must begin with data and clock high */
2224 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2225 ixgbe_raise_i2c_clk(hw, &i2cctl);
2227 /* Setup time for start condition (4.7us) */
2228 usec_delay(IXGBE_I2C_T_SU_STA);
2230 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2232 /* Hold time for start condition (4us) */
2233 usec_delay(IXGBE_I2C_T_HD_STA);
2235 ixgbe_lower_i2c_clk(hw, &i2cctl);
2237 /* Minimum low period of clock is 4.7 us */
2238 usec_delay(IXGBE_I2C_T_LOW);
2243 * ixgbe_i2c_stop - Sets I2C stop condition
2244 * @hw: pointer to hardware structure
2246 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2247 * Disables bit-bang mode and negates data output enable on X550
2250 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2252 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2253 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2254 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2255 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2257 DEBUGFUNC("ixgbe_i2c_stop");
2259 /* Stop condition must begin with data low and clock high */
2260 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2261 ixgbe_raise_i2c_clk(hw, &i2cctl);
2263 /* Setup time for stop condition (4us) */
2264 usec_delay(IXGBE_I2C_T_SU_STO);
2266 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2268 /* bus free time between stop and start (4.7us)*/
2269 usec_delay(IXGBE_I2C_T_BUF);
2271 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2272 i2cctl &= ~bb_en_bit;
2273 i2cctl |= data_oe_bit | clk_oe_bit;
2274 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2275 IXGBE_WRITE_FLUSH(hw);
2280 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2281 * @hw: pointer to hardware structure
2282 * @data: data byte to clock in
2284 * Clocks in one byte data via I2C data/clock
2286 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2291 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2294 for (i = 7; i >= 0; i--) {
2295 ixgbe_clock_in_i2c_bit(hw, &bit);
2301 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2302 * @hw: pointer to hardware structure
2303 * @data: data byte clocked out
2305 * Clocks out one byte data via I2C data/clock
2307 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2309 s32 status = IXGBE_SUCCESS;
2314 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2316 for (i = 7; i >= 0; i--) {
2317 bit = (data >> i) & 0x1;
2318 status = ixgbe_clock_out_i2c_bit(hw, bit);
2320 if (status != IXGBE_SUCCESS)
2324 /* Release SDA line (set high) */
2325 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2326 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2327 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2328 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2329 IXGBE_WRITE_FLUSH(hw);
2335 * ixgbe_get_i2c_ack - Polls for I2C ACK
2336 * @hw: pointer to hardware structure
2338 * Clocks in/out one bit via I2C data/clock
2340 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2342 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2343 s32 status = IXGBE_SUCCESS;
2345 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2349 DEBUGFUNC("ixgbe_get_i2c_ack");
2352 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2353 i2cctl |= data_oe_bit;
2354 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2355 IXGBE_WRITE_FLUSH(hw);
2357 ixgbe_raise_i2c_clk(hw, &i2cctl);
2359 /* Minimum high period of clock is 4us */
2360 usec_delay(IXGBE_I2C_T_HIGH);
2362 /* Poll for ACK. Note that ACK in I2C spec is
2363 * transition from 1 to 0 */
2364 for (i = 0; i < timeout; i++) {
2365 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2366 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2374 DEBUGOUT("I2C ack was not received.\n");
2375 status = IXGBE_ERR_I2C;
2378 ixgbe_lower_i2c_clk(hw, &i2cctl);
2380 /* Minimum low period of clock is 4.7 us */
2381 usec_delay(IXGBE_I2C_T_LOW);
2387 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2388 * @hw: pointer to hardware structure
2389 * @data: read data value
2391 * Clocks in one bit via I2C data/clock
2393 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2395 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2396 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2398 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2401 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2402 i2cctl |= data_oe_bit;
2403 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2404 IXGBE_WRITE_FLUSH(hw);
2406 ixgbe_raise_i2c_clk(hw, &i2cctl);
2408 /* Minimum high period of clock is 4us */
2409 usec_delay(IXGBE_I2C_T_HIGH);
2411 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2412 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2414 ixgbe_lower_i2c_clk(hw, &i2cctl);
2416 /* Minimum low period of clock is 4.7 us */
2417 usec_delay(IXGBE_I2C_T_LOW);
2421 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2422 * @hw: pointer to hardware structure
2423 * @data: data value to write
2425 * Clocks out one bit via I2C data/clock
2427 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2430 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2432 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2434 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2435 if (status == IXGBE_SUCCESS) {
2436 ixgbe_raise_i2c_clk(hw, &i2cctl);
2438 /* Minimum high period of clock is 4us */
2439 usec_delay(IXGBE_I2C_T_HIGH);
2441 ixgbe_lower_i2c_clk(hw, &i2cctl);
2443 /* Minimum low period of clock is 4.7 us.
2444 * This also takes care of the data hold time.
2446 usec_delay(IXGBE_I2C_T_LOW);
2448 status = IXGBE_ERR_I2C;
2449 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2450 "I2C data was not set to %X\n", data);
2457 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2458 * @hw: pointer to hardware structure
2459 * @i2cctl: Current value of I2CCTL register
2461 * Raises the I2C clock line '0'->'1'
2462 * Negates the I2C clock output enable on X550 hardware.
2464 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2466 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2468 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2471 DEBUGFUNC("ixgbe_raise_i2c_clk");
2474 *i2cctl |= clk_oe_bit;
2475 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2478 for (i = 0; i < timeout; i++) {
2479 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2481 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2482 IXGBE_WRITE_FLUSH(hw);
2483 /* SCL rise time (1000ns) */
2484 usec_delay(IXGBE_I2C_T_RISE);
2486 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2487 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2493 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2494 * @hw: pointer to hardware structure
2495 * @i2cctl: Current value of I2CCTL register
2497 * Lowers the I2C clock line '1'->'0'
2498 * Asserts the I2C clock output enable on X550 hardware.
2500 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2502 DEBUGFUNC("ixgbe_lower_i2c_clk");
2504 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2505 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2507 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2508 IXGBE_WRITE_FLUSH(hw);
2510 /* SCL fall time (300ns) */
2511 usec_delay(IXGBE_I2C_T_FALL);
2515 * ixgbe_set_i2c_data - Sets the I2C data bit
2516 * @hw: pointer to hardware structure
2517 * @i2cctl: Current value of I2CCTL register
2518 * @data: I2C data value (0 or 1) to set
2520 * Sets the I2C data bit
2521 * Asserts the I2C data output enable on X550 hardware.
2523 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2525 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2526 s32 status = IXGBE_SUCCESS;
2528 DEBUGFUNC("ixgbe_set_i2c_data");
2531 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2533 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2534 *i2cctl &= ~data_oe_bit;
2536 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2537 IXGBE_WRITE_FLUSH(hw);
2539 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2540 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2542 if (!data) /* Can't verify data in this case */
2543 return IXGBE_SUCCESS;
2545 *i2cctl |= data_oe_bit;
2546 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2547 IXGBE_WRITE_FLUSH(hw);
2550 /* Verify data was set correctly */
2551 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2552 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2553 status = IXGBE_ERR_I2C;
2554 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2555 "Error - I2C data was not set to %X.\n",
2563 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2564 * @hw: pointer to hardware structure
2565 * @i2cctl: Current value of I2CCTL register
2567 * Returns the I2C data bit value
2568 * Negates the I2C data output enable on X550 hardware.
2570 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2572 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2574 UNREFERENCED_1PARAMETER(hw);
2576 DEBUGFUNC("ixgbe_get_i2c_data");
2579 *i2cctl |= data_oe_bit;
2580 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2581 IXGBE_WRITE_FLUSH(hw);
2582 usec_delay(IXGBE_I2C_T_FALL);
2585 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2594 * ixgbe_i2c_bus_clear - Clears the I2C bus
2595 * @hw: pointer to hardware structure
2597 * Clears the I2C bus by sending nine clock pulses.
2598 * Used when data line is stuck low.
2600 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2605 DEBUGFUNC("ixgbe_i2c_bus_clear");
2607 ixgbe_i2c_start(hw);
2608 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2610 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2612 for (i = 0; i < 9; i++) {
2613 ixgbe_raise_i2c_clk(hw, &i2cctl);
2615 /* Min high period of clock is 4us */
2616 usec_delay(IXGBE_I2C_T_HIGH);
2618 ixgbe_lower_i2c_clk(hw, &i2cctl);
2620 /* Min low period of clock is 4.7us*/
2621 usec_delay(IXGBE_I2C_T_LOW);
2624 ixgbe_i2c_start(hw);
2626 /* Put the i2c bus back to default state */
2631 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2632 * @hw: pointer to hardware structure
2634 * Checks if the LASI temp alarm status was triggered due to overtemp
2636 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2638 s32 status = IXGBE_SUCCESS;
2641 DEBUGFUNC("ixgbe_tn_check_overtemp");
2643 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2646 /* Check that the LASI temp alarm status was triggered */
2647 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2648 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2650 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2653 status = IXGBE_ERR_OVERTEMP;
2654 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2660 * ixgbe_set_copper_phy_power - Control power for copper phy
2661 * @hw: pointer to hardware structure
2662 * @on: true for on, false for off
2664 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2669 if (!on && ixgbe_mng_present(hw))
2672 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2673 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2679 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2681 if (ixgbe_check_reset_blocked(hw))
2683 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2686 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2687 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,