sys/dev/ixgbe/ixgbe_phy.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2020, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  42 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  45 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  52                                           u8 *sff8472_data);
  53
  54 /**
  55  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  56  * @hw: pointer to the hardware structure
  57  * @byte: byte to send
  58  *
  59  * Returns an error code on error.
  60  */
  61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  62 {
  63         s32 status;
  64
  65         status = ixgbe_clock_out_i2c_byte(hw, byte);
  66         if (status)
  67                 return status;
  68         return ixgbe_get_i2c_ack(hw);
  69 }
  70
  71 /**
  72  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  73  * @hw: pointer to the hardware structure
  74  * @byte: pointer to a u8 to receive the byte
  75  *
  76  * Returns an error code on error.
  77  */
  78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  79 {
  80         ixgbe_clock_in_i2c_byte(hw, byte);
  81         /* ACK */
  82         return ixgbe_clock_out_i2c_bit(hw, false);
  83 }
  84
  85 /**
  86  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  87  * @add1: addend 1
  88  * @add2: addend 2
  89  *
  90  * Returns one's complement 8-bit sum.
  91  */
  92 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  93 {
  94         u16 sum = add1 + add2;
  95
  96         sum = (sum & 0xFF) + (sum >> 8);
  97         return sum & 0xFF;
  98 }
  99
 100 /**
 101  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 102  * @hw: pointer to the hardware structure
 103  * @addr: I2C bus address to read from
 104  * @reg: I2C device register to read from
 105  * @val: pointer to location to receive read value
 106  * @lock: true if to take and release semaphore
 107  *
 108  * Returns an error code on error.
 109  */
 110 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 111                                         u16 *val, bool lock)
 112 {
 113         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 114         int max_retry = 3;
 115         int retry = 0;
 116         u8 csum_byte;
 117         u8 high_bits;
 118         u8 low_bits;
 119         u8 reg_high;
 120         u8 csum;
 121
 122         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 123         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 124         csum = ~csum;
 125         do {
 126                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 127                         return IXGBE_ERR_SWFW_SYNC;
 128                 ixgbe_i2c_start(hw);
 129                 /* Device Address and write indication */
 130                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 131                         goto fail;
 132                 /* Write bits 14:8 */
 133                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 134                         goto fail;
 135                 /* Write bits 7:0 */
 136                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 137                         goto fail;
 138                 /* Write csum */
 139                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 140                         goto fail;
 141                 /* Re-start condition */
 142                 ixgbe_i2c_start(hw);
 143                 /* Device Address and read indication */
 144                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 145                         goto fail;
 146                 /* Get upper bits */
 147                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 148                         goto fail;
 149                 /* Get low bits */
 150                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 151                         goto fail;
 152                 /* Get csum */
 153                 ixgbe_clock_in_i2c_byte(hw, &csum_byte);
 154                 /* NACK */
 155                 if (ixgbe_clock_out_i2c_bit(hw, false))
 156                         goto fail;
 157                 ixgbe_i2c_stop(hw);
 158                 if (lock)
 159                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 160                 *val = (high_bits << 8) | low_bits;
 161                 return 0;
 162
 163 fail:
 164                 ixgbe_i2c_bus_clear(hw);
 165                 if (lock)
 166                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 167                 if (retry < max_retry)
 168                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 169                 else
 170                         DEBUGOUT("I2C byte read combined error.\n");
 171                 retry++;
 172         } while (retry <= max_retry);
 173
 174         return IXGBE_ERR_I2C;
 175 }
 176
 177 /**
 178  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 179  * @hw: pointer to the hardware structure
 180  * @addr: I2C bus address to write to
 181  * @reg: I2C device register to write to
 182  * @val: value to write
 183  * @lock: true if to take and release semaphore
 184  *
 185  * Returns an error code on error.
 186  */
 187 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 188                                          u16 val, bool lock)
 189 {
 190         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 191         int max_retry = 1;
 192         int retry = 0;
 193         u8 reg_high;
 194         u8 csum;
 195
 196         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 197         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 198         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 199         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 200         csum = ~csum;
 201         do {
 202                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 203                         return IXGBE_ERR_SWFW_SYNC;
 204                 ixgbe_i2c_start(hw);
 205                 /* Device Address and write indication */
 206                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 207                         goto fail;
 208                 /* Write bits 14:8 */
 209                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 210                         goto fail;
 211                 /* Write bits 7:0 */
 212                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 213                         goto fail;
 214                 /* Write data 15:8 */
 215                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 216                         goto fail;
 217                 /* Write data 7:0 */
 218                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 219                         goto fail;
 220                 /* Write csum */
 221                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 222                         goto fail;
 223                 ixgbe_i2c_stop(hw);
 224                 if (lock)
 225                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 226                 return 0;
 227
 228 fail:
 229                 ixgbe_i2c_bus_clear(hw);
 230                 if (lock)
 231                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 232                 if (retry < max_retry)
 233                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 234                 else
 235                         DEBUGOUT("I2C byte write combined error.\n");
 236                 retry++;
 237         } while (retry <= max_retry);
 238
 239         return IXGBE_ERR_I2C;
 240 }
 241
 242 /**
 243  * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 244  * @hw: pointer to the hardware structure
 245  *
 246  * Initialize the function pointers.
 247  **/
 248 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 249 {
 250         struct ixgbe_phy_info *phy = &hw->phy;
 251
 252         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 253
 254         /* PHY */
 255         phy->ops.identify = ixgbe_identify_phy_generic;
 256         phy->ops.reset = ixgbe_reset_phy_generic;
 257         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 258         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 259         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 260         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 261         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 262         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 263         phy->ops.check_link = NULL;
 264         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 265         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 266         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 267         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 268         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 269         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 270         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 271         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 272         phy->sfp_type = ixgbe_sfp_type_unknown;
 273         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 274         phy->ops.write_i2c_byte_unlocked =
 275                                 ixgbe_write_i2c_byte_generic_unlocked;
 276         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 277         return IXGBE_SUCCESS;
 278 }
 279
 280 /**
 281  * ixgbe_probe_phy - Probe a single address for a PHY
 282  * @hw: pointer to hardware structure
 283  * @phy_addr: PHY address to probe
 284  *
 285  * Returns true if PHY found
 286  */
 287 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 288 {
 289         u16 ext_ability = 0;
 290
 291         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 292                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 293                         phy_addr);
 294                 return false;
 295         }
 296
 297         if (ixgbe_get_phy_id(hw))
 298                 return false;
 299
 300         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 301
 302         if (hw->phy.type == ixgbe_phy_unknown) {
 303                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 304                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 305                 if (ext_ability &
 306                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 307                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 308                         hw->phy.type = ixgbe_phy_cu_unknown;
 309                 else
 310                         hw->phy.type = ixgbe_phy_generic;
 311         }
 312
 313         return true;
 314 }
 315
 316 /**
 317  * ixgbe_identify_phy_generic - Get physical layer module
 318  * @hw: pointer to hardware structure
 319  *
 320  * Determines the physical layer module found on the current adapter.
 321  **/
 322 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 323 {
 324         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 325         u16 phy_addr;
 326
 327         DEBUGFUNC("ixgbe_identify_phy_generic");
 328
 329         if (!hw->phy.phy_semaphore_mask) {
 330                 if (hw->bus.lan_id)
 331                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 332                 else
 333                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 334         }
 335
 336         if (hw->phy.type != ixgbe_phy_unknown)
 337                 return IXGBE_SUCCESS;
 338
 339         if (hw->phy.nw_mng_if_sel) {
 340                 phy_addr = (hw->phy.nw_mng_if_sel &
 341                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 342                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 343                 if (ixgbe_probe_phy(hw, phy_addr))
 344                         return IXGBE_SUCCESS;
 345                 else
 346                         return IXGBE_ERR_PHY_ADDR_INVALID;
 347         }
 348
 349         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 350                 if (ixgbe_probe_phy(hw, phy_addr)) {
 351                         status = IXGBE_SUCCESS;
 352                         break;
 353                 }
 354         }
 355
 356         /* Certain media types do not have a phy so an address will not
 357          * be found and the code will take this path.  Caller has to
 358          * decide if it is an error or not.
 359          */
 360         if (status != IXGBE_SUCCESS)
 361                 hw->phy.addr = 0;
 362
 363         return status;
 364 }
 365
 366 /**
 367  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 368  * @hw: pointer to the hardware structure
 369  *
 370  * This function checks the MMNGC.MNG_VETO bit to see if there are
 371  * any constraints on link from manageability.  For MAC's that don't
 372  * have this bit just return faluse since the link can not be blocked
 373  * via this method.
 374  **/
 375 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 376 {
 377         u32 mmngc;
 378
 379         DEBUGFUNC("ixgbe_check_reset_blocked");
 380
 381         /* If we don't have this bit, it can't be blocking */
 382         if (hw->mac.type == ixgbe_mac_82598EB)
 383                 return false;
 384
 385         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 386         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 387                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 388                               "MNG_VETO bit detected.\n");
 389                 return true;
 390         }
 391
 392         return false;
 393 }
 394
 395 /**
 396  * ixgbe_validate_phy_addr - Determines phy address is valid
 397  * @hw: pointer to hardware structure
 398  * @phy_addr: PHY address
 399  *
 400  **/
 401 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 402 {
 403         u16 phy_id = 0;
 404         bool valid = false;
 405
 406         DEBUGFUNC("ixgbe_validate_phy_addr");
 407
 408         hw->phy.addr = phy_addr;
 409         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 410                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 411
 412         if (phy_id != 0xFFFF && phy_id != 0x0)
 413                 valid = true;
 414
 415         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 416
 417         return valid;
 418 }
 419
 420 /**
 421  * ixgbe_get_phy_id - Get the phy type
 422  * @hw: pointer to hardware structure
 423  *
 424  **/
 425 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 426 {
 427         u32 status;
 428         u16 phy_id_high = 0;
 429         u16 phy_id_low = 0;
 430
 431         DEBUGFUNC("ixgbe_get_phy_id");
 432
 433         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 434                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 435                                       &phy_id_high);
 436
 437         if (status == IXGBE_SUCCESS) {
 438                 hw->phy.id = (u32)(phy_id_high << 16);
 439                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 440                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 441                                               &phy_id_low);
 442                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 443                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 444         }
 445         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 446                   phy_id_high, phy_id_low);
 447
 448         return status;
 449 }
 450
 451 /**
 452  * ixgbe_get_phy_type_from_id - Get the phy type
 453  * @phy_id: PHY ID information
 454  *
 455  **/
 456 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 457 {
 458         enum ixgbe_phy_type phy_type;
 459
 460         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 461
 462         switch (phy_id) {
 463         case TN1010_PHY_ID:
 464                 phy_type = ixgbe_phy_tn;
 465                 break;
 466         case X550_PHY_ID2:
 467         case X550_PHY_ID3:
 468         case X540_PHY_ID:
 469                 phy_type = ixgbe_phy_aq;
 470                 break;
 471         case QT2022_PHY_ID:
 472                 phy_type = ixgbe_phy_qt;
 473                 break;
 474         case ATH_PHY_ID:
 475                 phy_type = ixgbe_phy_nl;
 476                 break;
 477         case X557_PHY_ID:
 478         case X557_PHY_ID2:
 479                 phy_type = ixgbe_phy_x550em_ext_t;
 480                 break;
 481         case IXGBE_M88E1500_E_PHY_ID:
 482         case IXGBE_M88E1543_E_PHY_ID:
 483                 phy_type = ixgbe_phy_ext_1g_t;
 484                 break;
 485         default:
 486                 phy_type = ixgbe_phy_unknown;
 487                 break;
 488         }
 489         return phy_type;
 490 }
 491
 492 /**
 493  * ixgbe_reset_phy_generic - Performs a PHY reset
 494  * @hw: pointer to hardware structure
 495  **/
 496 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 497 {
 498         u32 i;
 499         u16 ctrl = 0;
 500         s32 status = IXGBE_SUCCESS;
 501
 502         DEBUGFUNC("ixgbe_reset_phy_generic");
 503
 504         if (hw->phy.type == ixgbe_phy_unknown)
 505                 status = ixgbe_identify_phy_generic(hw);
 506
 507         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 508                 goto out;
 509
 510         /* Don't reset PHY if it's shut down due to overtemp. */
 511         if (!hw->phy.reset_if_overtemp &&
 512             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 513                 goto out;
 514
 515         /* Blocked by MNG FW so bail */
 516         if (ixgbe_check_reset_blocked(hw))
 517                 goto out;
 518
 519         /*
 520          * Perform soft PHY reset to the PHY_XS.
 521          * This will cause a soft reset to the PHY
 522          */
 523         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 524                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 525                               IXGBE_MDIO_PHY_XS_RESET);
 526
 527         /*
 528          * Poll for reset bit to self-clear indicating reset is complete.
 529          * Some PHYs could take up to 3 seconds to complete and need about
 530          * 1.7 usec delay after the reset is complete.
 531          */
 532         for (i = 0; i < 30; i++) {
 533                 msec_delay(100);
 534                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 535                         status = hw->phy.ops.read_reg(hw,
 536                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 537                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 538                                                   &ctrl);
 539                         if (status != IXGBE_SUCCESS)
 540                                 return status;
 541
 542                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 543                                 usec_delay(2);
 544                                 break;
 545                         }
 546                 } else {
 547                         status = hw->phy.ops.read_reg(hw,
 548                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 549                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 550                                                      &ctrl);
 551                         if (status != IXGBE_SUCCESS)
 552                                 return status;
 553
 554                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 555                                 usec_delay(2);
 556                                 break;
 557                         }
 558                 }
 559         }
 560
 561         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 562                 status = IXGBE_ERR_RESET_FAILED;
 563                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 564                              "PHY reset polling failed to complete.\n");
 565         }
 566
 567 out:
 568         return status;
 569 }
 570
 571 /**
 572  * ixgbe_restart_auto_neg - Restart auto negotiation on the PHY
 573  * @hw: pointer to hardware structure
 574  **/
 575 void ixgbe_restart_auto_neg(struct ixgbe_hw *hw)
 576 {
 577         u16 autoneg_reg;
 578
 579         /* Check if PHY reset is blocked by MNG FW */
 580         if (ixgbe_check_reset_blocked(hw))
 581                 return;
 582
 583         /* Restart PHY auto-negotiation. */
 584         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 585                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 586         autoneg_reg |= IXGBE_MII_RESTART;
 587         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 588                                 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 589 }
 590
 591 /**
 592  * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 593  * the SWFW lock
 594  * @hw: pointer to hardware structure
 595  * @reg_addr: 32 bit address of PHY register to read
 596  * @device_type: 5 bit device type
 597  * @phy_data: Pointer to read data from PHY register
 598  **/
 599 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 600                            u16 *phy_data)
 601 {
 602         u32 i, data, command;
 603
 604         /* Setup and write the address cycle command */
 605         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 606                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 607                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 608                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 609
 610         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 611
 612         /*
 613          * Check every 10 usec to see if the address cycle completed.
 614          * The MDI Command bit will clear when the operation is
 615          * complete
 616          */
 617         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 618                 usec_delay(10);
 619
 620                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 621                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 622                         break;
 623         }
 624
 625
 626         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 627                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 628                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 629                 return IXGBE_ERR_PHY;
 630         }
 631
 632         /*
 633          * Address cycle complete, setup and write the read
 634          * command
 635          */
 636         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 637                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 638                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 639                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 640
 641         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 642
 643         /*
 644          * Check every 10 usec to see if the address cycle
 645          * completed. The MDI Command bit will clear when the
 646          * operation is complete
 647          */
 648         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 649                 usec_delay(10);
 650
 651                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 652                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 653                         break;
 654         }
 655
 656         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 657                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 658                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 659                 return IXGBE_ERR_PHY;
 660         }
 661
 662         /*
 663          * Read operation is complete.  Get the data
 664          * from MSRWD
 665          */
 666         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 667         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 668         *phy_data = (u16)(data);
 669
 670         return IXGBE_SUCCESS;
 671 }
 672
 673 /**
 674  * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 675  * using the SWFW lock - this function is needed in most cases
 676  * @hw: pointer to hardware structure
 677  * @reg_addr: 32 bit address of PHY register to read
 678  * @device_type: 5 bit device type
 679  * @phy_data: Pointer to read data from PHY register
 680  **/
 681 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 682                                u32 device_type, u16 *phy_data)
 683 {
 684         s32 status;
 685         u32 gssr = hw->phy.phy_semaphore_mask;
 686
 687         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 688
 689         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 690                 return IXGBE_ERR_SWFW_SYNC;
 691
 692         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 693
 694         hw->mac.ops.release_swfw_sync(hw, gssr);
 695
 696         return status;
 697 }
 698
 699 /**
 700  * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 701  * without SWFW lock
 702  * @hw: pointer to hardware structure
 703  * @reg_addr: 32 bit PHY register to write
 704  * @device_type: 5 bit device type
 705  * @phy_data: Data to write to the PHY register
 706  **/
 707 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 708                                 u32 device_type, u16 phy_data)
 709 {
 710         u32 i, command;
 711
 712         /* Put the data in the MDI single read and write data register*/
 713         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 714
 715         /* Setup and write the address cycle command */
 716         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 717                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 718                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 719                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 720
 721         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 722
 723         /*
 724          * Check every 10 usec to see if the address cycle completed.
 725          * The MDI Command bit will clear when the operation is
 726          * complete
 727          */
 728         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 729                 usec_delay(10);
 730
 731                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 732                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 733                         break;
 734         }
 735
 736         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 737                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 738                 return IXGBE_ERR_PHY;
 739         }
 740
 741         /*
 742          * Address cycle complete, setup and write the write
 743          * command
 744          */
 745         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 746                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 747                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 748                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 749
 750         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 751
 752         /*
 753          * Check every 10 usec to see if the address cycle
 754          * completed. The MDI Command bit will clear when the
 755          * operation is complete
 756          */
 757         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 758                 usec_delay(10);
 759
 760                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 761                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 762                         break;
 763         }
 764
 765         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 766                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 767                 return IXGBE_ERR_PHY;
 768         }
 769
 770         return IXGBE_SUCCESS;
 771 }
 772
 773 /**
 774  * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 775  * using SWFW lock- this function is needed in most cases
 776  * @hw: pointer to hardware structure
 777  * @reg_addr: 32 bit PHY register to write
 778  * @device_type: 5 bit device type
 779  * @phy_data: Data to write to the PHY register
 780  **/
 781 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 782                                 u32 device_type, u16 phy_data)
 783 {
 784         s32 status;
 785         u32 gssr = hw->phy.phy_semaphore_mask;
 786
 787         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 788
 789         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 790                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 791                                                  phy_data);
 792                 hw->mac.ops.release_swfw_sync(hw, gssr);
 793         } else {
 794                 status = IXGBE_ERR_SWFW_SYNC;
 795         }
 796
 797         return status;
 798 }
 799
 800 /**
 801  * ixgbe_setup_phy_link_generic - Set and restart auto-neg
 802  * @hw: pointer to hardware structure
 803  *
 804  * Restart auto-negotiation and PHY and waits for completion.
 805  **/
 806 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 807 {
 808         s32 status = IXGBE_SUCCESS;
 809         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 810         bool autoneg = false;
 811         ixgbe_link_speed speed;
 812
 813         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 814
 815         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 816
 817         /* Set or unset auto-negotiation 10G advertisement */
 818         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 819                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 820                              &autoneg_reg);
 821
 822         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 823         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 824             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 825                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 826
 827         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 828                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 829                               autoneg_reg);
 830
 831         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 832                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 833                              &autoneg_reg);
 834
 835         if (hw->mac.type == ixgbe_mac_X550) {
 836                 /* Set or unset auto-negotiation 5G advertisement */
 837                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 838                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 839                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 840                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 841
 842                 /* Set or unset auto-negotiation 2.5G advertisement */
 843                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 844                 if ((hw->phy.autoneg_advertised &
 845                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 846                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 847                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 848         }
 849
 850         /* Set or unset auto-negotiation 1G advertisement */
 851         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 852         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 853             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 854                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 855
 856         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 857                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 858                               autoneg_reg);
 859
 860         /* Set or unset auto-negotiation 100M advertisement */
 861         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 862                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 863                              &autoneg_reg);
 864
 865         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 866                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 867         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 868             (speed & IXGBE_LINK_SPEED_100_FULL))
 869                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 870
 871         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 872                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 873                               autoneg_reg);
 874
 875         ixgbe_restart_auto_neg(hw);
 876         return status;
 877 }
 878
 879 /**
 880  * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 881  * @hw: pointer to hardware structure
 882  * @speed: new link speed
 883  * @autoneg_wait_to_complete: unused
 884  **/
 885 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 886                                        ixgbe_link_speed speed,
 887                                        bool autoneg_wait_to_complete)
 888 {
 889         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 890
 891         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 892
 893         /*
 894          * Clear autoneg_advertised and set new values based on input link
 895          * speed.
 896          */
 897         hw->phy.autoneg_advertised = 0;
 898
 899         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 900                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 901
 902         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 903                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 904
 905         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 906                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 907
 908         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 909                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 910
 911         if (speed & IXGBE_LINK_SPEED_100_FULL)
 912                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 913
 914         if (speed & IXGBE_LINK_SPEED_10_FULL)
 915                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 916
 917         /* Setup link based on the new speed settings */
 918         ixgbe_setup_phy_link(hw);
 919
 920         return IXGBE_SUCCESS;
 921 }
 922
 923 /**
 924  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 925  * @hw: pointer to hardware structure
 926  *
 927  * Determines the supported link capabilities by reading the PHY auto
 928  * negotiation register.
 929  **/
 930 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 931 {
 932         s32 status;
 933         u16 speed_ability;
 934
 935         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 936                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 937                                       &speed_ability);
 938         if (status)
 939                 return status;
 940
 941         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 942                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 943         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 944                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 945         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 946                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 947
 948         switch (hw->mac.type) {
 949         case ixgbe_mac_X550:
 950                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 951                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 952                 break;
 953         case ixgbe_mac_X550EM_x:
 954         case ixgbe_mac_X550EM_a:
 955                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 956                 break;
 957         default:
 958                 break;
 959         }
 960
 961         return status;
 962 }
 963
 964 /**
 965  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 966  * @hw: pointer to hardware structure
 967  * @speed: pointer to link speed
 968  * @autoneg: boolean auto-negotiation value
 969  **/
 970 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 971                                                ixgbe_link_speed *speed,
 972                                                bool *autoneg)
 973 {
 974         s32 status = IXGBE_SUCCESS;
 975
 976         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 977
 978         *autoneg = true;
 979         if (!hw->phy.speeds_supported)
 980                 status = ixgbe_get_copper_speeds_supported(hw);
 981
 982         *speed = hw->phy.speeds_supported;
 983         return status;
 984 }
 985
 986 /**
 987  * ixgbe_check_phy_link_tnx - Determine link and speed status
 988  * @hw: pointer to hardware structure
 989  * @speed: current link speed
 990  * @link_up: true is link is up, false otherwise
 991  *
 992  * Reads the VS1 register to determine if link is up and the current speed for
 993  * the PHY.
 994  **/
 995 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 996                              bool *link_up)
 997 {
 998         s32 status = IXGBE_SUCCESS;
 999         u32 time_out;
1000         u32 max_time_out = 10;
1001         u16 phy_link = 0;
1002         u16 phy_speed = 0;
1003         u16 phy_data = 0;
1004
1005         DEBUGFUNC("ixgbe_check_phy_link_tnx");
1006
1007         /* Initialize speed and link to default case */
1008         *link_up = false;
1009         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1010
1011         /*
1012          * Check current speed and link status of the PHY register.
1013          * This is a vendor specific register and may have to
1014          * be changed for other copper PHYs.
1015          */
1016         for (time_out = 0; time_out < max_time_out; time_out++) {
1017                 usec_delay(10);
1018                 status = hw->phy.ops.read_reg(hw,
1019                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1020                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1021                                         &phy_data);
1022                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1023                 phy_speed = phy_data &
1024                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1025                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1026                         *link_up = true;
1027                         if (phy_speed ==
1028                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1029                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1030                         break;
1031                 }
1032         }
1033
1034         return status;
1035 }
1036
1037 /**
1038  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1039  *      @hw: pointer to hardware structure
1040  *
1041  *      Restart auto-negotiation and PHY and waits for completion.
1042  **/
1043 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1044 {
1045         s32 status = IXGBE_SUCCESS;
1046         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1047         bool autoneg = false;
1048         ixgbe_link_speed speed;
1049
1050         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1051
1052         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1053
1054         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1055                 /* Set or unset auto-negotiation 10G advertisement */
1056                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1057                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1058                                      &autoneg_reg);
1059
1060                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1061                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1062                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1063
1064                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1065                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1066                                       autoneg_reg);
1067         }
1068
1069         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1070                 /* Set or unset auto-negotiation 1G advertisement */
1071                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1072                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1073                                      &autoneg_reg);
1074
1075                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1076                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1077                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1078
1079                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1080                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1081                                       autoneg_reg);
1082         }
1083
1084         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1085                 /* Set or unset auto-negotiation 100M advertisement */
1086                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1087                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1088                                      &autoneg_reg);
1089
1090                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1091                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1092                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1093
1094                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1095                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1096                                       autoneg_reg);
1097         }
1098
1099         ixgbe_restart_auto_neg(hw);
1100         return status;
1101 }
1102
1103 /**
1104  * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1105  * @hw: pointer to hardware structure
1106  * @firmware_version: pointer to the PHY Firmware Version
1107  **/
1108 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1109                                        u16 *firmware_version)
1110 {
1111         s32 status;
1112
1113         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1114
1115         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1116                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1117                                       firmware_version);
1118
1119         return status;
1120 }
1121
1122 /**
1123  * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1124  * @hw: pointer to hardware structure
1125  * @firmware_version: pointer to the PHY Firmware Version
1126  **/
1127 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1128                                            u16 *firmware_version)
1129 {
1130         s32 status;
1131
1132         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1133
1134         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1135                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1136                                       firmware_version);
1137
1138         return status;
1139 }
1140
1141 /**
1142  * ixgbe_reset_phy_nl - Performs a PHY reset
1143  * @hw: pointer to hardware structure
1144  **/
1145 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1146 {
1147         u16 phy_offset, control, eword, edata, block_crc;
1148         bool end_data = false;
1149         u16 list_offset, data_offset;
1150         u16 phy_data = 0;
1151         s32 ret_val = IXGBE_SUCCESS;
1152         u32 i;
1153
1154         DEBUGFUNC("ixgbe_reset_phy_nl");
1155
1156         /* Blocked by MNG FW so bail */
1157         if (ixgbe_check_reset_blocked(hw))
1158                 goto out;
1159
1160         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1161                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1162
1163         /* reset the PHY and poll for completion */
1164         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1165                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1166                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1167
1168         for (i = 0; i < 100; i++) {
1169                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1171                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1172                         break;
1173                 msec_delay(10);
1174         }
1175
1176         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1177                 DEBUGOUT("PHY reset did not complete.\n");
1178                 ret_val = IXGBE_ERR_PHY;
1179                 goto out;
1180         }
1181
1182         /* Get init offsets */
1183         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1184                                                       &data_offset);
1185         if (ret_val != IXGBE_SUCCESS)
1186                 goto out;
1187
1188         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1189         data_offset++;
1190         while (!end_data) {
1191                 /*
1192                  * Read control word from PHY init contents offset
1193                  */
1194                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1195                 if (ret_val)
1196                         goto err_eeprom;
1197                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1198                            IXGBE_CONTROL_SHIFT_NL;
1199                 edata = eword & IXGBE_DATA_MASK_NL;
1200                 switch (control) {
1201                 case IXGBE_DELAY_NL:
1202                         data_offset++;
1203                         DEBUGOUT1("DELAY: %d MS\n", edata);
1204                         msec_delay(edata);
1205                         break;
1206                 case IXGBE_DATA_NL:
1207                         DEBUGOUT("DATA:\n");
1208                         data_offset++;
1209                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1210                                                       &phy_offset);
1211                         if (ret_val)
1212                                 goto err_eeprom;
1213                         data_offset++;
1214                         for (i = 0; i < edata; i++) {
1215                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1216                                                               &eword);
1217                                 if (ret_val)
1218                                         goto err_eeprom;
1219                                 hw->phy.ops.write_reg(hw, phy_offset,
1220                                                       IXGBE_TWINAX_DEV, eword);
1221                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1222                                           phy_offset);
1223                                 data_offset++;
1224                                 phy_offset++;
1225                         }
1226                         break;
1227                 case IXGBE_CONTROL_NL:
1228                         data_offset++;
1229                         DEBUGOUT("CONTROL:\n");
1230                         if (edata == IXGBE_CONTROL_EOL_NL) {
1231                                 DEBUGOUT("EOL\n");
1232                                 end_data = true;
1233                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1234                                 DEBUGOUT("SOL\n");
1235                         } else {
1236                                 DEBUGOUT("Bad control value\n");
1237                                 ret_val = IXGBE_ERR_PHY;
1238                                 goto out;
1239                         }
1240                         break;
1241                 default:
1242                         DEBUGOUT("Bad control type\n");
1243                         ret_val = IXGBE_ERR_PHY;
1244                         goto out;
1245                 }
1246         }
1247
1248 out:
1249         return ret_val;
1250
1251 err_eeprom:
1252         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1253                       "eeprom read at offset %d failed", data_offset);
1254         return IXGBE_ERR_PHY;
1255 }
1256
1257 /**
1258  * ixgbe_identify_module_generic - Identifies module type
1259  * @hw: pointer to hardware structure
1260  *
1261  * Determines HW type and calls appropriate function.
1262  **/
1263 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1264 {
1265         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1266
1267         DEBUGFUNC("ixgbe_identify_module_generic");
1268
1269         switch (hw->mac.ops.get_media_type(hw)) {
1270         case ixgbe_media_type_fiber:
1271                 status = ixgbe_identify_sfp_module_generic(hw);
1272                 break;
1273
1274         case ixgbe_media_type_fiber_qsfp:
1275                 status = ixgbe_identify_qsfp_module_generic(hw);
1276                 break;
1277
1278         default:
1279                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1280                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1281                 break;
1282         }
1283
1284         return status;
1285 }
1286
1287 /**
1288  * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1289  * @hw: pointer to hardware structure
1290  *
1291  * Searches for and identifies the SFP module and assigns appropriate PHY type.
1292  **/
1293 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1294 {
1295         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1296         u32 vendor_oui = 0;
1297         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1298         u8 identifier = 0;
1299         u8 comp_codes_1g = 0;
1300         u8 comp_codes_10g = 0;
1301         u8 oui_bytes[3] = {0, 0, 0};
1302         u8 cable_tech = 0;
1303         u8 cable_spec = 0;
1304         u16 enforce_sfp = 0;
1305
1306         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1307
1308         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1309                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1310                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1311                 goto out;
1312         }
1313
1314         /* LAN ID is needed for I2C access */
1315         hw->mac.ops.set_lan_id(hw);
1316
1317         status = hw->phy.ops.read_i2c_eeprom(hw,
1318                                              IXGBE_SFF_IDENTIFIER,
1319                                              &identifier);
1320
1321         if (status != IXGBE_SUCCESS)
1322                 goto err_read_i2c_eeprom;
1323
1324         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1325                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1326                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1327         } else {
1328                 status = hw->phy.ops.read_i2c_eeprom(hw,
1329                                                      IXGBE_SFF_1GBE_COMP_CODES,
1330                                                      &comp_codes_1g);
1331
1332                 if (status != IXGBE_SUCCESS)
1333                         goto err_read_i2c_eeprom;
1334
1335                 status = hw->phy.ops.read_i2c_eeprom(hw,
1336                                                      IXGBE_SFF_10GBE_COMP_CODES,
1337                                                      &comp_codes_10g);
1338
1339                 if (status != IXGBE_SUCCESS)
1340                         goto err_read_i2c_eeprom;
1341                 status = hw->phy.ops.read_i2c_eeprom(hw,
1342                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1343                                                      &cable_tech);
1344
1345                 if (status != IXGBE_SUCCESS)
1346                         goto err_read_i2c_eeprom;
1347
1348                  /* ID Module
1349                   * =========
1350                   * 0   SFP_DA_CU
1351                   * 1   SFP_SR
1352                   * 2   SFP_LR
1353                   * 3   SFP_DA_CORE0 - 82599-specific
1354                   * 4   SFP_DA_CORE1 - 82599-specific
1355                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1356                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1357                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1358                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1359                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1360                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1361                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1362                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1363                   */
1364                 if (hw->mac.type == ixgbe_mac_82598EB) {
1365                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1366                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1367                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1368                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1369                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1370                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1371                         else
1372                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1373                 } else {
1374                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1375                                 if (hw->bus.lan_id == 0)
1376                                         hw->phy.sfp_type =
1377                                                      ixgbe_sfp_type_da_cu_core0;
1378                                 else
1379                                         hw->phy.sfp_type =
1380                                                      ixgbe_sfp_type_da_cu_core1;
1381                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1382                                 hw->phy.ops.read_i2c_eeprom(
1383                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1384                                                 &cable_spec);
1385                                 if (cable_spec &
1386                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1387                                         if (hw->bus.lan_id == 0)
1388                                                 hw->phy.sfp_type =
1389                                                 ixgbe_sfp_type_da_act_lmt_core0;
1390                                         else
1391                                                 hw->phy.sfp_type =
1392                                                 ixgbe_sfp_type_da_act_lmt_core1;
1393                                 } else {
1394                                         hw->phy.sfp_type =
1395                                                         ixgbe_sfp_type_unknown;
1396                                 }
1397                         } else if (comp_codes_10g &
1398                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1399                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1400                                 if (hw->bus.lan_id == 0)
1401                                         hw->phy.sfp_type =
1402                                                       ixgbe_sfp_type_srlr_core0;
1403                                 else
1404                                         hw->phy.sfp_type =
1405                                                       ixgbe_sfp_type_srlr_core1;
1406                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1407                                 if (hw->bus.lan_id == 0)
1408                                         hw->phy.sfp_type =
1409                                                 ixgbe_sfp_type_1g_cu_core0;
1410                                 else
1411                                         hw->phy.sfp_type =
1412                                                 ixgbe_sfp_type_1g_cu_core1;
1413                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1414                                 if (hw->bus.lan_id == 0)
1415                                         hw->phy.sfp_type =
1416                                                 ixgbe_sfp_type_1g_sx_core0;
1417                                 else
1418                                         hw->phy.sfp_type =
1419                                                 ixgbe_sfp_type_1g_sx_core1;
1420                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1421                                 if (hw->bus.lan_id == 0)
1422                                         hw->phy.sfp_type =
1423                                                 ixgbe_sfp_type_1g_lx_core0;
1424                                 else
1425                                         hw->phy.sfp_type =
1426                                                 ixgbe_sfp_type_1g_lx_core1;
1427                         } else {
1428                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1429                         }
1430                 }
1431
1432                 if (hw->phy.sfp_type != stored_sfp_type)
1433                         hw->phy.sfp_setup_needed = true;
1434
1435                 /* Determine if the SFP+ PHY is dual speed or not. */
1436                 hw->phy.multispeed_fiber = false;
1437                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1438                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1439                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1440                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1441                         hw->phy.multispeed_fiber = true;
1442
1443                 /* Determine PHY vendor */
1444                 if (hw->phy.type != ixgbe_phy_nl) {
1445                         hw->phy.id = identifier;
1446                         status = hw->phy.ops.read_i2c_eeprom(hw,
1447                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1448                                                     &oui_bytes[0]);
1449
1450                         if (status != IXGBE_SUCCESS)
1451                                 goto err_read_i2c_eeprom;
1452
1453                         status = hw->phy.ops.read_i2c_eeprom(hw,
1454                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1455                                                     &oui_bytes[1]);
1456
1457                         if (status != IXGBE_SUCCESS)
1458                                 goto err_read_i2c_eeprom;
1459
1460                         status = hw->phy.ops.read_i2c_eeprom(hw,
1461                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1462                                                     &oui_bytes[2]);
1463
1464                         if (status != IXGBE_SUCCESS)
1465                                 goto err_read_i2c_eeprom;
1466
1467                         vendor_oui =
1468                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1469                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1470                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1471
1472                         switch (vendor_oui) {
1473                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1474                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1475                                         hw->phy.type =
1476                                                     ixgbe_phy_sfp_passive_tyco;
1477                                 break;
1478                         case IXGBE_SFF_VENDOR_OUI_FTL:
1479                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1480                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1481                                 else
1482                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1483                                 break;
1484                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1485                                 hw->phy.type = ixgbe_phy_sfp_avago;
1486                                 break;
1487                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1488                                 hw->phy.type = ixgbe_phy_sfp_intel;
1489                                 break;
1490                         default:
1491                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1492                                 break;
1493                         }
1494                 }
1495
1496                 /* Allow any DA cable vendor */
1497                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1498                         IXGBE_SFF_DA_ACTIVE_CABLE)) {
1499                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1500                                 hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1501                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502                                 hw->phy.type = ixgbe_phy_sfp_active_unknown;
1503                         status = IXGBE_SUCCESS;
1504                         goto out;
1505                 }
1506
1507                 /* Verify supported 1G SFP modules */
1508                 if (comp_codes_10g == 0 &&
1509                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1510                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1511                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1512                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1513                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1514                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1515                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1516                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1517                         goto out;
1518                 }
1519
1520                 /* Anything else 82598-based is supported */
1521                 if (hw->mac.type == ixgbe_mac_82598EB) {
1522                         status = IXGBE_SUCCESS;
1523                         goto out;
1524                 }
1525
1526                 ixgbe_get_device_caps(hw, &enforce_sfp);
1527                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1528                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1529                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1530                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1531                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1532                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1533                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1534                         /* Make sure we're a supported PHY type */
1535                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1536                                 status = IXGBE_SUCCESS;
1537                         } else {
1538                                 if (hw->allow_unsupported_sfp == true) {
1539                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1540                                         status = IXGBE_SUCCESS;
1541                                 } else {
1542                                         DEBUGOUT("SFP+ module not supported\n");
1543                                         hw->phy.type =
1544                                                 ixgbe_phy_sfp_unsupported;
1545                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1546                                 }
1547                         }
1548                 } else {
1549                         status = IXGBE_SUCCESS;
1550                 }
1551         }
1552
1553 out:
1554         return status;
1555
1556 err_read_i2c_eeprom:
1557         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1558         if (hw->phy.type != ixgbe_phy_nl) {
1559                 hw->phy.id = 0;
1560                 hw->phy.type = ixgbe_phy_unknown;
1561         }
1562         return IXGBE_ERR_SFP_NOT_PRESENT;
1563 }
1564
1565 /**
1566  * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1567  * @hw: pointer to hardware structure
1568  *
1569  * Determines physical layer capabilities of the current SFP.
1570  */
1571 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1572 {
1573         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1574         u8 comp_codes_10g = 0;
1575         u8 comp_codes_1g = 0;
1576
1577         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1578
1579         hw->phy.ops.identify_sfp(hw);
1580         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1581                 return physical_layer;
1582
1583         switch (hw->phy.type) {
1584         case ixgbe_phy_sfp_passive_tyco:
1585         case ixgbe_phy_sfp_passive_unknown:
1586         case ixgbe_phy_qsfp_passive_unknown:
1587                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1588                 break;
1589         case ixgbe_phy_sfp_ftl_active:
1590         case ixgbe_phy_sfp_active_unknown:
1591         case ixgbe_phy_qsfp_active_unknown:
1592                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1593                 break;
1594         case ixgbe_phy_sfp_avago:
1595         case ixgbe_phy_sfp_ftl:
1596         case ixgbe_phy_sfp_intel:
1597         case ixgbe_phy_sfp_unknown:
1598                 hw->phy.ops.read_i2c_eeprom(hw,
1599                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1600                 hw->phy.ops.read_i2c_eeprom(hw,
1601                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1602                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1603                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1604                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1605                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1606                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1607                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1608                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1609                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1610                 break;
1611         case ixgbe_phy_qsfp_intel:
1612         case ixgbe_phy_qsfp_unknown:
1613                 hw->phy.ops.read_i2c_eeprom(hw,
1614                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1615                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1616                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1617                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1618                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1619                 break;
1620         default:
1621                 break;
1622         }
1623
1624         return physical_layer;
1625 }
1626
1627 /**
1628  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1629  * @hw: pointer to hardware structure
1630  *
1631  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1632  **/
1633 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1634 {
1635         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1636         u32 vendor_oui = 0;
1637         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1638         u8 identifier = 0;
1639         u8 comp_codes_1g = 0;
1640         u8 comp_codes_10g = 0;
1641         u8 oui_bytes[3] = {0, 0, 0};
1642         u16 enforce_sfp = 0;
1643         u8 connector = 0;
1644         u8 cable_length = 0;
1645         u8 device_tech = 0;
1646         bool active_cable = false;
1647
1648         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1649
1650         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1651                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1652                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1653                 goto out;
1654         }
1655
1656         /* LAN ID is needed for I2C access */
1657         hw->mac.ops.set_lan_id(hw);
1658
1659         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1660                                              &identifier);
1661
1662         if (status != IXGBE_SUCCESS)
1663                 goto err_read_i2c_eeprom;
1664
1665         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1666                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1667                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1668                 goto out;
1669         }
1670
1671         hw->phy.id = identifier;
1672
1673         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1674                                              &comp_codes_10g);
1675
1676         if (status != IXGBE_SUCCESS)
1677                 goto err_read_i2c_eeprom;
1678
1679         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1680                                              &comp_codes_1g);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 goto err_read_i2c_eeprom;
1684
1685         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1686                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1687                 if (hw->bus.lan_id == 0)
1688                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1689                 else
1690                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1691         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1692                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1693                 if (hw->bus.lan_id == 0)
1694                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1695                 else
1696                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1697         } else {
1698                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1699                         active_cable = true;
1700
1701                 if (!active_cable) {
1702                         /* check for active DA cables that pre-date
1703                          * SFF-8436 v3.6 */
1704                         hw->phy.ops.read_i2c_eeprom(hw,
1705                                         IXGBE_SFF_QSFP_CONNECTOR,
1706                                         &connector);
1707
1708                         hw->phy.ops.read_i2c_eeprom(hw,
1709                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1710                                         &cable_length);
1711
1712                         hw->phy.ops.read_i2c_eeprom(hw,
1713                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1714                                         &device_tech);
1715
1716                         if ((connector ==
1717                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1718                             (cable_length > 0) &&
1719                             ((device_tech >> 4) ==
1720                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1721                                 active_cable = true;
1722                 }
1723
1724                 if (active_cable) {
1725                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1726                         if (hw->bus.lan_id == 0)
1727                                 hw->phy.sfp_type =
1728                                                 ixgbe_sfp_type_da_act_lmt_core0;
1729                         else
1730                                 hw->phy.sfp_type =
1731                                                 ixgbe_sfp_type_da_act_lmt_core1;
1732                 } else {
1733                         /* unsupported module type */
1734                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1735                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1736                         goto out;
1737                 }
1738         }
1739
1740         if (hw->phy.sfp_type != stored_sfp_type)
1741                 hw->phy.sfp_setup_needed = true;
1742
1743         /* Determine if the QSFP+ PHY is dual speed or not. */
1744         hw->phy.multispeed_fiber = false;
1745         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1746            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1747            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1748            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1749                 hw->phy.multispeed_fiber = true;
1750
1751         /* Determine PHY vendor for optical modules */
1752         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1753                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1754                 status = hw->phy.ops.read_i2c_eeprom(hw,
1755                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1756                                             &oui_bytes[0]);
1757
1758                 if (status != IXGBE_SUCCESS)
1759                         goto err_read_i2c_eeprom;
1760
1761                 status = hw->phy.ops.read_i2c_eeprom(hw,
1762                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1763                                             &oui_bytes[1]);
1764
1765                 if (status != IXGBE_SUCCESS)
1766                         goto err_read_i2c_eeprom;
1767
1768                 status = hw->phy.ops.read_i2c_eeprom(hw,
1769                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1770                                             &oui_bytes[2]);
1771
1772                 if (status != IXGBE_SUCCESS)
1773                         goto err_read_i2c_eeprom;
1774
1775                 vendor_oui =
1776                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1777                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1778                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1779
1780                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1781                         hw->phy.type = ixgbe_phy_qsfp_intel;
1782                 else
1783                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1784
1785                 ixgbe_get_device_caps(hw, &enforce_sfp);
1786                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1787                         /* Make sure we're a supported PHY type */
1788                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1789                                 status = IXGBE_SUCCESS;
1790                         } else {
1791                                 if (hw->allow_unsupported_sfp == true) {
1792                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1793                                         status = IXGBE_SUCCESS;
1794                                 } else {
1795                                         DEBUGOUT("QSFP module not supported\n");
1796                                         hw->phy.type =
1797                                                 ixgbe_phy_sfp_unsupported;
1798                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1799                                 }
1800                         }
1801                 } else {
1802                         status = IXGBE_SUCCESS;
1803                 }
1804         }
1805
1806 out:
1807         return status;
1808
1809 err_read_i2c_eeprom:
1810         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1811         hw->phy.id = 0;
1812         hw->phy.type = ixgbe_phy_unknown;
1813
1814         return IXGBE_ERR_SFP_NOT_PRESENT;
1815 }
1816
1817 /**
1818  * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1819  * @hw: pointer to hardware structure
1820  * @list_offset: offset to the SFP ID list
1821  * @data_offset: offset to the SFP data block
1822  *
1823  * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1824  * so it returns the offsets to the phy init sequence block.
1825  **/
1826 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1827                                         u16 *list_offset,
1828                                         u16 *data_offset)
1829 {
1830         u16 sfp_id;
1831         u16 sfp_type = hw->phy.sfp_type;
1832
1833         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1834
1835         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1836                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1837
1838         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1839                 return IXGBE_ERR_SFP_NOT_PRESENT;
1840
1841         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1842             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1843                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1844
1845         /*
1846          * Limiting active cables and 1G Phys must be initialized as
1847          * SR modules
1848          */
1849         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1850             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1851             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1852             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1853                 sfp_type = ixgbe_sfp_type_srlr_core0;
1854         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1855                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1856                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1857                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1858                 sfp_type = ixgbe_sfp_type_srlr_core1;
1859
1860         /* Read offset to PHY init contents */
1861         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1862                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1863                               "eeprom read at offset %d failed",
1864                               IXGBE_PHY_INIT_OFFSET_NL);
1865                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1866         }
1867
1868         if ((!*list_offset) || (*list_offset == 0xFFFF))
1869                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1870
1871         /* Shift offset to first ID word */
1872         (*list_offset)++;
1873
1874         /*
1875          * Find the matching SFP ID in the EEPROM
1876          * and program the init sequence
1877          */
1878         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1879                 goto err_phy;
1880
1881         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1882                 if (sfp_id == sfp_type) {
1883                         (*list_offset)++;
1884                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1885                                 goto err_phy;
1886                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1887                                 DEBUGOUT("SFP+ module not supported\n");
1888                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1889                         } else {
1890                                 break;
1891                         }
1892                 } else {
1893                         (*list_offset) += 2;
1894                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1895                                 goto err_phy;
1896                 }
1897         }
1898
1899         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1900                 DEBUGOUT("No matching SFP+ module found\n");
1901                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1902         }
1903
1904         return IXGBE_SUCCESS;
1905
1906 err_phy:
1907         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1908                       "eeprom read at offset %d failed", *list_offset);
1909         return IXGBE_ERR_PHY;
1910 }
1911
1912 /**
1913  * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1914  * @hw: pointer to hardware structure
1915  * @byte_offset: EEPROM byte offset to read
1916  * @eeprom_data: value read
1917  *
1918  * Performs byte read operation to SFP module's EEPROM over I2C interface.
1919  **/
1920 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1921                                   u8 *eeprom_data)
1922 {
1923         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1924
1925         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1926                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1927                                          eeprom_data);
1928 }
1929
1930 /**
1931  * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1932  * @hw: pointer to hardware structure
1933  * @byte_offset: byte offset at address 0xA2
1934  * @sff8472_data: value read
1935  *
1936  * Performs byte read operation to SFP module's SFF-8472 data over I2C
1937  **/
1938 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1939                                           u8 *sff8472_data)
1940 {
1941         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1943                                          sff8472_data);
1944 }
1945
1946 /**
1947  * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1948  * @hw: pointer to hardware structure
1949  * @byte_offset: EEPROM byte offset to write
1950  * @eeprom_data: value to write
1951  *
1952  * Performs byte write operation to SFP module's EEPROM over I2C interface.
1953  **/
1954 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1955                                    u8 eeprom_data)
1956 {
1957         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1958
1959         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1960                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1961                                           eeprom_data);
1962 }
1963
1964 /**
1965  * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1966  * @hw: pointer to hardware structure
1967  * @offset: eeprom offset to be read
1968  * @addr: I2C address to be read
1969  */
1970 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1971 {
1972         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1973             offset == IXGBE_SFF_IDENTIFIER &&
1974             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1975                 return true;
1976         return false;
1977 }
1978
1979 /**
1980  * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1981  * @hw: pointer to hardware structure
1982  * @byte_offset: byte offset to read
1983  * @dev_addr: address to read from
1984  * @data: value read
1985  * @lock: true if to take and release semaphore
1986  *
1987  * Performs byte read operation to SFP module's EEPROM over I2C interface at
1988  * a specified device address.
1989  **/
1990 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1991                                            u8 dev_addr, u8 *data, bool lock)
1992 {
1993         s32 status;
1994         u32 max_retry = 10;
1995         u32 retry = 0;
1996         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1997         bool nack = 1;
1998         *data = 0;
1999
2000         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2001
2002         if (hw->mac.type >= ixgbe_mac_X550)
2003                 max_retry = 3;
2004         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2005                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2006
2007         do {
2008                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2009                         return IXGBE_ERR_SWFW_SYNC;
2010
2011                 ixgbe_i2c_start(hw);
2012
2013                 /* Device Address and write indication */
2014                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2015                 if (status != IXGBE_SUCCESS)
2016                         goto fail;
2017
2018                 status = ixgbe_get_i2c_ack(hw);
2019                 if (status != IXGBE_SUCCESS)
2020                         goto fail;
2021
2022                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2023                 if (status != IXGBE_SUCCESS)
2024                         goto fail;
2025
2026                 status = ixgbe_get_i2c_ack(hw);
2027                 if (status != IXGBE_SUCCESS)
2028                         goto fail;
2029
2030                 ixgbe_i2c_start(hw);
2031
2032                 /* Device Address and read indication */
2033                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2034                 if (status != IXGBE_SUCCESS)
2035                         goto fail;
2036
2037                 status = ixgbe_get_i2c_ack(hw);
2038                 if (status != IXGBE_SUCCESS)
2039                         goto fail;
2040
2041                 ixgbe_clock_in_i2c_byte(hw, data);
2042
2043                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2044                 if (status != IXGBE_SUCCESS)
2045                         goto fail;
2046
2047                 ixgbe_i2c_stop(hw);
2048                 if (lock)
2049                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2050                 return IXGBE_SUCCESS;
2051
2052 fail:
2053                 ixgbe_i2c_bus_clear(hw);
2054                 if (lock) {
2055                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2056                         msec_delay(100);
2057                 }
2058                 if (retry < max_retry)
2059                         DEBUGOUT("I2C byte read error - Retrying.\n");
2060                 else
2061                         DEBUGOUT("I2C byte read error.\n");
2062                 retry++;
2063         } while (retry <= max_retry);
2064
2065         return status;
2066 }
2067
2068 /**
2069  * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2070  * @hw: pointer to hardware structure
2071  * @byte_offset: byte offset to read
2072  * @dev_addr: address to read from
2073  * @data: value read
2074  *
2075  * Performs byte read operation to SFP module's EEPROM over I2C interface at
2076  * a specified device address.
2077  **/
2078 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2079                                 u8 dev_addr, u8 *data)
2080 {
2081         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2082                                                data, true);
2083 }
2084
2085 /**
2086  * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2087  * @hw: pointer to hardware structure
2088  * @byte_offset: byte offset to read
2089  * @dev_addr: address to read from
2090  * @data: value read
2091  *
2092  * Performs byte read operation to SFP module's EEPROM over I2C interface at
2093  * a specified device address.
2094  **/
2095 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2096                                          u8 dev_addr, u8 *data)
2097 {
2098         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2099                                                data, false);
2100 }
2101
2102 /**
2103  * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2104  * @hw: pointer to hardware structure
2105  * @byte_offset: byte offset to write
2106  * @dev_addr: address to write to
2107  * @data: value to write
2108  * @lock: true if to take and release semaphore
2109  *
2110  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2111  * a specified device address.
2112  **/
2113 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2114                                             u8 dev_addr, u8 data, bool lock)
2115 {
2116         s32 status;
2117         u32 max_retry = 1;
2118         u32 retry = 0;
2119         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2120
2121         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2122
2123         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2124             IXGBE_SUCCESS)
2125                 return IXGBE_ERR_SWFW_SYNC;
2126
2127         do {
2128                 ixgbe_i2c_start(hw);
2129
2130                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2131                 if (status != IXGBE_SUCCESS)
2132                         goto fail;
2133
2134                 status = ixgbe_get_i2c_ack(hw);
2135                 if (status != IXGBE_SUCCESS)
2136                         goto fail;
2137
2138                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2139                 if (status != IXGBE_SUCCESS)
2140                         goto fail;
2141
2142                 status = ixgbe_get_i2c_ack(hw);
2143                 if (status != IXGBE_SUCCESS)
2144                         goto fail;
2145
2146                 status = ixgbe_clock_out_i2c_byte(hw, data);
2147                 if (status != IXGBE_SUCCESS)
2148                         goto fail;
2149
2150                 status = ixgbe_get_i2c_ack(hw);
2151                 if (status != IXGBE_SUCCESS)
2152                         goto fail;
2153
2154                 ixgbe_i2c_stop(hw);
2155                 if (lock)
2156                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2157                 return IXGBE_SUCCESS;
2158
2159 fail:
2160                 ixgbe_i2c_bus_clear(hw);
2161                 if (retry < max_retry)
2162                         DEBUGOUT("I2C byte write error - Retrying.\n");
2163                 else
2164                         DEBUGOUT("I2C byte write error.\n");
2165                 retry++;
2166         } while (retry <= max_retry);
2167
2168         if (lock)
2169                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2170
2171         return status;
2172 }
2173
2174 /**
2175  * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2176  * @hw: pointer to hardware structure
2177  * @byte_offset: byte offset to write
2178  * @dev_addr: address to write to
2179  * @data: value to write
2180  *
2181  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2182  * a specified device address.
2183  **/
2184 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2185                                  u8 dev_addr, u8 data)
2186 {
2187         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2188                                                 data, true);
2189 }
2190
2191 /**
2192  * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2193  * @hw: pointer to hardware structure
2194  * @byte_offset: byte offset to write
2195  * @dev_addr: address to write to
2196  * @data: value to write
2197  *
2198  * Performs byte write operation to SFP module's EEPROM over I2C interface at
2199  * a specified device address.
2200  **/
2201 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2202                                           u8 dev_addr, u8 data)
2203 {
2204         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2205                                                 data, false);
2206 }
2207
2208 /**
2209  * ixgbe_i2c_start - Sets I2C start condition
2210  * @hw: pointer to hardware structure
2211  *
2212  * Sets I2C start condition (High -> Low on SDA while SCL is High)
2213  * Set bit-bang mode on X550 hardware.
2214  **/
2215 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2216 {
2217         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2218
2219         DEBUGFUNC("ixgbe_i2c_start");
2220
2221         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2222
2223         /* Start condition must begin with data and clock high */
2224         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2225         ixgbe_raise_i2c_clk(hw, &i2cctl);
2226
2227         /* Setup time for start condition (4.7us) */
2228         usec_delay(IXGBE_I2C_T_SU_STA);
2229
2230         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2231
2232         /* Hold time for start condition (4us) */
2233         usec_delay(IXGBE_I2C_T_HD_STA);
2234
2235         ixgbe_lower_i2c_clk(hw, &i2cctl);
2236
2237         /* Minimum low period of clock is 4.7 us */
2238         usec_delay(IXGBE_I2C_T_LOW);
2239
2240 }
2241
2242 /**
2243  * ixgbe_i2c_stop - Sets I2C stop condition
2244  * @hw: pointer to hardware structure
2245  *
2246  * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2247  * Disables bit-bang mode and negates data output enable on X550
2248  * hardware.
2249  **/
2250 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2251 {
2252         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2253         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2254         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2255         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2256
2257         DEBUGFUNC("ixgbe_i2c_stop");
2258
2259         /* Stop condition must begin with data low and clock high */
2260         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2261         ixgbe_raise_i2c_clk(hw, &i2cctl);
2262
2263         /* Setup time for stop condition (4us) */
2264         usec_delay(IXGBE_I2C_T_SU_STO);
2265
2266         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2267
2268         /* bus free time between stop and start (4.7us)*/
2269         usec_delay(IXGBE_I2C_T_BUF);
2270
2271         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2272                 i2cctl &= ~bb_en_bit;
2273                 i2cctl |= data_oe_bit | clk_oe_bit;
2274                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2275                 IXGBE_WRITE_FLUSH(hw);
2276         }
2277 }
2278
2279 /**
2280  * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2281  * @hw: pointer to hardware structure
2282  * @data: data byte to clock in
2283  *
2284  * Clocks in one byte data via I2C data/clock
2285  **/
2286 static void ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2287 {
2288         s32 i;
2289         bool bit = 0;
2290
2291         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2292
2293         *data = 0;
2294         for (i = 7; i >= 0; i--) {
2295                 ixgbe_clock_in_i2c_bit(hw, &bit);
2296                 *data |= bit << i;
2297         }
2298 }
2299
2300 /**
2301  * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2302  * @hw: pointer to hardware structure
2303  * @data: data byte clocked out
2304  *
2305  * Clocks out one byte data via I2C data/clock
2306  **/
2307 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2308 {
2309         s32 status = IXGBE_SUCCESS;
2310         s32 i;
2311         u32 i2cctl;
2312         bool bit;
2313
2314         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2315
2316         for (i = 7; i >= 0; i--) {
2317                 bit = (data >> i) & 0x1;
2318                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2319
2320                 if (status != IXGBE_SUCCESS)
2321                         break;
2322         }
2323
2324         /* Release SDA line (set high) */
2325         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2326         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2327         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2328         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2329         IXGBE_WRITE_FLUSH(hw);
2330
2331         return status;
2332 }
2333
2334 /**
2335  * ixgbe_get_i2c_ack - Polls for I2C ACK
2336  * @hw: pointer to hardware structure
2337  *
2338  * Clocks in/out one bit via I2C data/clock
2339  **/
2340 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2341 {
2342         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2343         s32 status = IXGBE_SUCCESS;
2344         u32 i = 0;
2345         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2346         u32 timeout = 10;
2347         bool ack = 1;
2348
2349         DEBUGFUNC("ixgbe_get_i2c_ack");
2350
2351         if (data_oe_bit) {
2352                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2353                 i2cctl |= data_oe_bit;
2354                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2355                 IXGBE_WRITE_FLUSH(hw);
2356         }
2357         ixgbe_raise_i2c_clk(hw, &i2cctl);
2358
2359         /* Minimum high period of clock is 4us */
2360         usec_delay(IXGBE_I2C_T_HIGH);
2361
2362         /* Poll for ACK.  Note that ACK in I2C spec is
2363          * transition from 1 to 0 */
2364         for (i = 0; i < timeout; i++) {
2365                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2366                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2367
2368                 usec_delay(1);
2369                 if (!ack)
2370                         break;
2371         }
2372
2373         if (ack) {
2374                 DEBUGOUT("I2C ack was not received.\n");
2375                 status = IXGBE_ERR_I2C;
2376         }
2377
2378         ixgbe_lower_i2c_clk(hw, &i2cctl);
2379
2380         /* Minimum low period of clock is 4.7 us */
2381         usec_delay(IXGBE_I2C_T_LOW);
2382
2383         return status;
2384 }
2385
2386 /**
2387  * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2388  * @hw: pointer to hardware structure
2389  * @data: read data value
2390  *
2391  * Clocks in one bit via I2C data/clock
2392  **/
2393 static void ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2394 {
2395         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2396         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2397
2398         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2399
2400         if (data_oe_bit) {
2401                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2402                 i2cctl |= data_oe_bit;
2403                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2404                 IXGBE_WRITE_FLUSH(hw);
2405         }
2406         ixgbe_raise_i2c_clk(hw, &i2cctl);
2407
2408         /* Minimum high period of clock is 4us */
2409         usec_delay(IXGBE_I2C_T_HIGH);
2410
2411         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2412         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2413
2414         ixgbe_lower_i2c_clk(hw, &i2cctl);
2415
2416         /* Minimum low period of clock is 4.7 us */
2417         usec_delay(IXGBE_I2C_T_LOW);
2418 }
2419
2420 /**
2421  * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2422  * @hw: pointer to hardware structure
2423  * @data: data value to write
2424  *
2425  * Clocks out one bit via I2C data/clock
2426  **/
2427 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2428 {
2429         s32 status;
2430         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2431
2432         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2433
2434         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2435         if (status == IXGBE_SUCCESS) {
2436                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2437
2438                 /* Minimum high period of clock is 4us */
2439                 usec_delay(IXGBE_I2C_T_HIGH);
2440
2441                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2442
2443                 /* Minimum low period of clock is 4.7 us.
2444                  * This also takes care of the data hold time.
2445                  */
2446                 usec_delay(IXGBE_I2C_T_LOW);
2447         } else {
2448                 status = IXGBE_ERR_I2C;
2449                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2450                              "I2C data was not set to %X\n", data);
2451         }
2452
2453         return status;
2454 }
2455
2456 /**
2457  * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2458  * @hw: pointer to hardware structure
2459  * @i2cctl: Current value of I2CCTL register
2460  *
2461  * Raises the I2C clock line '0'->'1'
2462  * Negates the I2C clock output enable on X550 hardware.
2463  **/
2464 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2465 {
2466         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2467         u32 i = 0;
2468         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2469         u32 i2cctl_r = 0;
2470
2471         DEBUGFUNC("ixgbe_raise_i2c_clk");
2472
2473         if (clk_oe_bit) {
2474                 *i2cctl |= clk_oe_bit;
2475                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2476         }
2477
2478         for (i = 0; i < timeout; i++) {
2479                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2480
2481                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2482                 IXGBE_WRITE_FLUSH(hw);
2483                 /* SCL rise time (1000ns) */
2484                 usec_delay(IXGBE_I2C_T_RISE);
2485
2486                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2487                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2488                         break;
2489         }
2490 }
2491
2492 /**
2493  * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2494  * @hw: pointer to hardware structure
2495  * @i2cctl: Current value of I2CCTL register
2496  *
2497  * Lowers the I2C clock line '1'->'0'
2498  * Asserts the I2C clock output enable on X550 hardware.
2499  **/
2500 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2501 {
2502         DEBUGFUNC("ixgbe_lower_i2c_clk");
2503
2504         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2505         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2506
2507         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2508         IXGBE_WRITE_FLUSH(hw);
2509
2510         /* SCL fall time (300ns) */
2511         usec_delay(IXGBE_I2C_T_FALL);
2512 }
2513
2514 /**
2515  * ixgbe_set_i2c_data - Sets the I2C data bit
2516  * @hw: pointer to hardware structure
2517  * @i2cctl: Current value of I2CCTL register
2518  * @data: I2C data value (0 or 1) to set
2519  *
2520  * Sets the I2C data bit
2521  * Asserts the I2C data output enable on X550 hardware.
2522  **/
2523 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2524 {
2525         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2526         s32 status = IXGBE_SUCCESS;
2527
2528         DEBUGFUNC("ixgbe_set_i2c_data");
2529
2530         if (data)
2531                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2532         else
2533                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2534         *i2cctl &= ~data_oe_bit;
2535
2536         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2537         IXGBE_WRITE_FLUSH(hw);
2538
2539         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2540         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2541
2542         if (!data)      /* Can't verify data in this case */
2543                 return IXGBE_SUCCESS;
2544         if (data_oe_bit) {
2545                 *i2cctl |= data_oe_bit;
2546                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2547                 IXGBE_WRITE_FLUSH(hw);
2548         }
2549
2550         /* Verify data was set correctly */
2551         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2552         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2553                 status = IXGBE_ERR_I2C;
2554                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2555                              "Error - I2C data was not set to %X.\n",
2556                              data);
2557         }
2558
2559         return status;
2560 }
2561
2562 /**
2563  * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2564  * @hw: pointer to hardware structure
2565  * @i2cctl: Current value of I2CCTL register
2566  *
2567  * Returns the I2C data bit value
2568  * Negates the I2C data output enable on X550 hardware.
2569  **/
2570 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2571 {
2572         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2573         bool data;
2574         UNREFERENCED_1PARAMETER(hw);
2575
2576         DEBUGFUNC("ixgbe_get_i2c_data");
2577
2578         if (data_oe_bit) {
2579                 *i2cctl |= data_oe_bit;
2580                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2581                 IXGBE_WRITE_FLUSH(hw);
2582                 usec_delay(IXGBE_I2C_T_FALL);
2583         }
2584
2585         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2586                 data = 1;
2587         else
2588                 data = 0;
2589
2590         return data;
2591 }
2592
2593 /**
2594  * ixgbe_i2c_bus_clear - Clears the I2C bus
2595  * @hw: pointer to hardware structure
2596  *
2597  * Clears the I2C bus by sending nine clock pulses.
2598  * Used when data line is stuck low.
2599  **/
2600 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2601 {
2602         u32 i2cctl;
2603         u32 i;
2604
2605         DEBUGFUNC("ixgbe_i2c_bus_clear");
2606
2607         ixgbe_i2c_start(hw);
2608         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2609
2610         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2611
2612         for (i = 0; i < 9; i++) {
2613                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2614
2615                 /* Min high period of clock is 4us */
2616                 usec_delay(IXGBE_I2C_T_HIGH);
2617
2618                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2619
2620                 /* Min low period of clock is 4.7us*/
2621                 usec_delay(IXGBE_I2C_T_LOW);
2622         }
2623
2624         ixgbe_i2c_start(hw);
2625
2626         /* Put the i2c bus back to default state */
2627         ixgbe_i2c_stop(hw);
2628 }
2629
2630 /**
2631  * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2632  * @hw: pointer to hardware structure
2633  *
2634  * Checks if the LASI temp alarm status was triggered due to overtemp
2635  **/
2636 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2637 {
2638         s32 status = IXGBE_SUCCESS;
2639         u16 phy_data = 0;
2640
2641         DEBUGFUNC("ixgbe_tn_check_overtemp");
2642
2643         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2644                 goto out;
2645
2646         /* Check that the LASI temp alarm status was triggered */
2647         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2648                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2649
2650         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2651                 goto out;
2652
2653         status = IXGBE_ERR_OVERTEMP;
2654         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2655 out:
2656         return status;
2657 }
2658
2659 /**
2660  * ixgbe_set_copper_phy_power - Control power for copper phy
2661  * @hw: pointer to hardware structure
2662  * @on: true for on, false for off
2663  */
2664 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2665 {
2666         u32 status;
2667         u16 reg;
2668
2669         if (!on && ixgbe_mng_present(hw))
2670                 return 0;
2671
2672         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2673                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2674                                       &reg);
2675         if (status)
2676                 return status;
2677
2678         if (on) {
2679                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2680         } else {
2681                 if (ixgbe_check_reset_blocked(hw))
2682                         return 0;
2683                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2684         }
2685
2686         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2687                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2688                                        reg);
2689         return status;
2690 }