1 /******************************************************************************
3 Copyright (c) 2001-2015, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
55 * @hw: pointer to the hardware structure
58 * Returns an error code on error.
60 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
64 status = ixgbe_clock_out_i2c_byte(hw, byte);
67 return ixgbe_get_i2c_ack(hw);
71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
72 * @hw: pointer to the hardware structure
73 * @byte: pointer to a u8 to receive the byte
75 * Returns an error code on error.
77 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
81 status = ixgbe_clock_in_i2c_byte(hw, byte);
85 return ixgbe_clock_out_i2c_bit(hw, FALSE);
89 * ixgbe_ones_comp_byte_add - Perform one's complement addition
93 * Returns one's complement 8-bit sum.
95 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
97 u16 sum = add1 + add2;
99 sum = (sum & 0xFF) + (sum >> 8);
104 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
105 * @hw: pointer to the hardware structure
106 * @addr: I2C bus address to read from
107 * @reg: I2C device register to read from
108 * @val: pointer to location to receive read value
109 * @lock: TRUE if to take and release semaphore
111 * Returns an error code on error.
113 static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
114 u16 reg, u16 *val, bool lock)
116 u32 swfw_mask = hw->phy.phy_semaphore_mask;
125 if (hw->mac.type >= ixgbe_mac_X550)
127 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
128 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
132 return IXGBE_ERR_SWFW_SYNC;
134 /* Device Address and write indication */
135 if (ixgbe_out_i2c_byte_ack(hw, addr))
137 /* Write bits 14:8 */
138 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
141 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
144 if (ixgbe_out_i2c_byte_ack(hw, csum))
146 /* Re-start condition */
148 /* Device Address and read indication */
149 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
152 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
155 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
158 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
161 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
165 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
166 *val = (high_bits << 8) | low_bits;
170 ixgbe_i2c_bus_clear(hw);
172 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
174 if (retry < max_retry)
175 DEBUGOUT("I2C byte read combined error - Retrying.\n");
177 DEBUGOUT("I2C byte read combined error.\n");
178 } while (retry < max_retry);
180 return IXGBE_ERR_I2C;
184 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
185 * @hw: pointer to the hardware structure
186 * @addr: I2C bus address to read from
187 * @reg: I2C device register to read from
188 * @val: pointer to location to receive read value
190 * Returns an error code on error.
192 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
195 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
199 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
200 * @hw: pointer to the hardware structure
201 * @addr: I2C bus address to read from
202 * @reg: I2C device register to read from
203 * @val: pointer to location to receive read value
205 * Returns an error code on error.
208 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
211 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
215 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
216 * @hw: pointer to the hardware structure
217 * @addr: I2C bus address to write to
218 * @reg: I2C device register to write to
219 * @val: value to write
220 * @lock: TRUE if to take and release semaphore
222 * Returns an error code on error.
224 static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
225 u16 reg, u16 val, bool lock)
227 u32 swfw_mask = hw->phy.phy_semaphore_mask;
233 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
234 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
235 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
236 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
239 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
240 return IXGBE_ERR_SWFW_SYNC;
242 /* Device Address and write indication */
243 if (ixgbe_out_i2c_byte_ack(hw, addr))
245 /* Write bits 14:8 */
246 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
249 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
251 /* Write data 15:8 */
252 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
255 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
258 if (ixgbe_out_i2c_byte_ack(hw, csum))
262 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
266 ixgbe_i2c_bus_clear(hw);
268 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 if (retry < max_retry)
271 DEBUGOUT("I2C byte write combined error - Retrying.\n");
273 DEBUGOUT("I2C byte write combined error.\n");
274 } while (retry < max_retry);
276 return IXGBE_ERR_I2C;
280 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
281 * @hw: pointer to the hardware structure
282 * @addr: I2C bus address to write to
283 * @reg: I2C device register to write to
284 * @val: value to write
286 * Returns an error code on error.
288 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
289 u8 addr, u16 reg, u16 val)
291 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE);
295 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
296 * @hw: pointer to the hardware structure
297 * @addr: I2C bus address to write to
298 * @reg: I2C device register to write to
299 * @val: value to write
301 * Returns an error code on error.
304 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
305 u8 addr, u16 reg, u16 val)
307 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE);
311 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
312 * @hw: pointer to the hardware structure
314 * Initialize the function pointers.
316 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
318 struct ixgbe_phy_info *phy = &hw->phy;
320 DEBUGFUNC("ixgbe_init_phy_ops_generic");
323 phy->ops.identify = ixgbe_identify_phy_generic;
324 phy->ops.reset = ixgbe_reset_phy_generic;
325 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
326 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
327 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
328 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
329 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
330 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
331 phy->ops.check_link = NULL;
332 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
333 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
334 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
335 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
336 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
337 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
338 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
339 phy->ops.identify_sfp = ixgbe_identify_module_generic;
340 phy->sfp_type = ixgbe_sfp_type_unknown;
341 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
342 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
343 phy->ops.read_i2c_combined_unlocked =
344 ixgbe_read_i2c_combined_generic_unlocked;
345 phy->ops.write_i2c_combined_unlocked =
346 ixgbe_write_i2c_combined_generic_unlocked;
347 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
348 phy->ops.write_i2c_byte_unlocked =
349 ixgbe_write_i2c_byte_generic_unlocked;
350 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
351 return IXGBE_SUCCESS;
355 * ixgbe_identify_phy_generic - Get physical layer module
356 * @hw: pointer to hardware structure
358 * Determines the physical layer module found on the current adapter.
360 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
362 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
366 DEBUGFUNC("ixgbe_identify_phy_generic");
368 if (!hw->phy.phy_semaphore_mask) {
370 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
372 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
375 if (hw->phy.type == ixgbe_phy_unknown) {
376 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
377 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
378 hw->phy.addr = phy_addr;
379 ixgbe_get_phy_id(hw);
381 ixgbe_get_phy_type_from_id(hw->phy.id);
383 if (hw->phy.type == ixgbe_phy_unknown) {
384 hw->phy.ops.read_reg(hw,
385 IXGBE_MDIO_PHY_EXT_ABILITY,
386 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
389 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
390 IXGBE_MDIO_PHY_1000BASET_ABILITY))
392 ixgbe_phy_cu_unknown;
398 status = IXGBE_SUCCESS;
403 /* Certain media types do not have a phy so an address will not
404 * be found and the code will take this path. Caller has to
405 * decide if it is an error or not.
407 if (status != IXGBE_SUCCESS) {
411 status = IXGBE_SUCCESS;
418 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
419 * @hw: pointer to the hardware structure
421 * This function checks the MMNGC.MNG_VETO bit to see if there are
422 * any constraints on link from manageability. For MAC's that don't
423 * have this bit just return faluse since the link can not be blocked
426 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
430 DEBUGFUNC("ixgbe_check_reset_blocked");
432 /* If we don't have this bit, it can't be blocking */
433 if (hw->mac.type == ixgbe_mac_82598EB)
436 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
437 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
438 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
439 "MNG_VETO bit detected.\n");
447 * ixgbe_validate_phy_addr - Determines phy address is valid
448 * @hw: pointer to hardware structure
451 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
456 DEBUGFUNC("ixgbe_validate_phy_addr");
458 hw->phy.addr = phy_addr;
459 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
460 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
462 if (phy_id != 0xFFFF && phy_id != 0x0)
469 * ixgbe_get_phy_id - Get the phy type
470 * @hw: pointer to hardware structure
473 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
479 DEBUGFUNC("ixgbe_get_phy_id");
481 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
482 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
485 if (status == IXGBE_SUCCESS) {
486 hw->phy.id = (u32)(phy_id_high << 16);
487 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
488 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
490 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
491 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
497 * ixgbe_get_phy_type_from_id - Get the phy type
498 * @hw: pointer to hardware structure
501 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
503 enum ixgbe_phy_type phy_type;
505 DEBUGFUNC("ixgbe_get_phy_type_from_id");
509 phy_type = ixgbe_phy_tn;
513 phy_type = ixgbe_phy_aq;
516 phy_type = ixgbe_phy_qt;
519 phy_type = ixgbe_phy_nl;
522 phy_type = ixgbe_phy_x550em_ext_t;
525 phy_type = ixgbe_phy_unknown;
529 DEBUGOUT1("phy type found is %d\n", phy_type);
534 * ixgbe_reset_phy_generic - Performs a PHY reset
535 * @hw: pointer to hardware structure
537 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
541 s32 status = IXGBE_SUCCESS;
543 DEBUGFUNC("ixgbe_reset_phy_generic");
545 if (hw->phy.type == ixgbe_phy_unknown)
546 status = ixgbe_identify_phy_generic(hw);
548 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
551 /* Don't reset PHY if it's shut down due to overtemp. */
552 if (!hw->phy.reset_if_overtemp &&
553 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
556 /* Blocked by MNG FW so bail */
557 if (ixgbe_check_reset_blocked(hw))
561 * Perform soft PHY reset to the PHY_XS.
562 * This will cause a soft reset to the PHY
564 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
565 IXGBE_MDIO_PHY_XS_DEV_TYPE,
566 IXGBE_MDIO_PHY_XS_RESET);
569 * Poll for reset bit to self-clear indicating reset is complete.
570 * Some PHYs could take up to 3 seconds to complete and need about
571 * 1.7 usec delay after the reset is complete.
573 for (i = 0; i < 30; i++) {
575 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
576 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
577 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
583 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
584 status = IXGBE_ERR_RESET_FAILED;
585 ERROR_REPORT1(IXGBE_ERROR_POLLING,
586 "PHY reset polling failed to complete.\n");
594 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
596 * @hw: pointer to hardware structure
597 * @reg_addr: 32 bit address of PHY register to read
598 * @phy_data: Pointer to read data from PHY register
600 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
603 u32 i, data, command;
605 /* Setup and write the address cycle command */
606 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
607 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
608 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
609 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
611 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
614 * Check every 10 usec to see if the address cycle completed.
615 * The MDI Command bit will clear when the operation is
618 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
621 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
622 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
627 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
628 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
629 return IXGBE_ERR_PHY;
633 * Address cycle complete, setup and write the read
636 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
637 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
638 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
639 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
641 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
644 * Check every 10 usec to see if the address cycle
645 * completed. The MDI Command bit will clear when the
646 * operation is complete
648 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
651 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
652 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
656 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
657 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
658 return IXGBE_ERR_PHY;
662 * Read operation is complete. Get the data
665 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
666 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
667 *phy_data = (u16)(data);
669 return IXGBE_SUCCESS;
673 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
674 * using the SWFW lock - this function is needed in most cases
675 * @hw: pointer to hardware structure
676 * @reg_addr: 32 bit address of PHY register to read
677 * @phy_data: Pointer to read data from PHY register
679 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
680 u32 device_type, u16 *phy_data)
683 u32 gssr = hw->phy.phy_semaphore_mask;
685 DEBUGFUNC("ixgbe_read_phy_reg_generic");
687 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
688 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
690 hw->mac.ops.release_swfw_sync(hw, gssr);
692 status = IXGBE_ERR_SWFW_SYNC;
699 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
701 * @hw: pointer to hardware structure
702 * @reg_addr: 32 bit PHY register to write
703 * @device_type: 5 bit device type
704 * @phy_data: Data to write to the PHY register
706 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
707 u32 device_type, u16 phy_data)
711 /* Put the data in the MDI single read and write data register*/
712 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
714 /* Setup and write the address cycle command */
715 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
716 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
717 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
718 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
720 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
723 * Check every 10 usec to see if the address cycle completed.
724 * The MDI Command bit will clear when the operation is
727 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
730 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
731 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
735 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
736 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
737 return IXGBE_ERR_PHY;
741 * Address cycle complete, setup and write the write
744 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
745 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
746 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
747 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
749 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
752 * Check every 10 usec to see if the address cycle
753 * completed. The MDI Command bit will clear when the
754 * operation is complete
756 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
759 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
760 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
764 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
765 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
766 return IXGBE_ERR_PHY;
769 return IXGBE_SUCCESS;
773 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
774 * using SWFW lock- this function is needed in most cases
775 * @hw: pointer to hardware structure
776 * @reg_addr: 32 bit PHY register to write
777 * @device_type: 5 bit device type
778 * @phy_data: Data to write to the PHY register
780 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
781 u32 device_type, u16 phy_data)
784 u32 gssr = hw->phy.phy_semaphore_mask;
786 DEBUGFUNC("ixgbe_write_phy_reg_generic");
788 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
789 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
791 hw->mac.ops.release_swfw_sync(hw, gssr);
793 status = IXGBE_ERR_SWFW_SYNC;
800 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
801 * @hw: pointer to hardware structure
803 * Restart auto-negotiation and PHY and waits for completion.
805 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
807 s32 status = IXGBE_SUCCESS;
808 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
809 bool autoneg = FALSE;
810 ixgbe_link_speed speed;
812 DEBUGFUNC("ixgbe_setup_phy_link_generic");
814 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
816 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
817 /* Set or unset auto-negotiation 10G advertisement */
818 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
819 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
822 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
823 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
824 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
826 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
827 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
831 if (hw->mac.type == ixgbe_mac_X550) {
832 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
833 /* Set or unset auto-negotiation 1G advertisement */
834 hw->phy.ops.read_reg(hw,
835 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
836 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
839 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
840 if (hw->phy.autoneg_advertised &
841 IXGBE_LINK_SPEED_5GB_FULL)
842 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
844 hw->phy.ops.write_reg(hw,
845 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
846 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
850 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
851 /* Set or unset auto-negotiation 1G advertisement */
852 hw->phy.ops.read_reg(hw,
853 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
854 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
857 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
858 if (hw->phy.autoneg_advertised &
859 IXGBE_LINK_SPEED_2_5GB_FULL)
860 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
862 hw->phy.ops.write_reg(hw,
863 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
864 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
869 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
870 /* Set or unset auto-negotiation 1G advertisement */
871 hw->phy.ops.read_reg(hw,
872 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
873 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
876 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
877 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
878 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
880 hw->phy.ops.write_reg(hw,
881 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
882 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
886 if (speed & IXGBE_LINK_SPEED_100_FULL) {
887 /* Set or unset auto-negotiation 100M advertisement */
888 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
889 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
892 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
893 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
894 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
895 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
897 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
898 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
902 /* Blocked by MNG FW so don't reset PHY */
903 if (ixgbe_check_reset_blocked(hw))
906 /* Restart PHY auto-negotiation. */
907 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
908 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
910 autoneg_reg |= IXGBE_MII_RESTART;
912 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
913 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
919 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
920 * @hw: pointer to hardware structure
921 * @speed: new link speed
923 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
924 ixgbe_link_speed speed,
925 bool autoneg_wait_to_complete)
927 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
929 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
932 * Clear autoneg_advertised and set new values based on input link
935 hw->phy.autoneg_advertised = 0;
937 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
938 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
940 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
941 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
943 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
944 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
946 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
947 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
949 if (speed & IXGBE_LINK_SPEED_100_FULL)
950 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
952 /* Setup link based on the new speed settings */
953 hw->phy.ops.setup_link(hw);
955 return IXGBE_SUCCESS;
959 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
960 * @hw: pointer to hardware structure
961 * @speed: pointer to link speed
962 * @autoneg: boolean auto-negotiation value
964 * Determines the supported link capabilities by reading the PHY auto
965 * negotiation register.
967 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
968 ixgbe_link_speed *speed,
974 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
979 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
980 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
983 if (status == IXGBE_SUCCESS) {
984 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
985 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
986 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
987 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
988 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
989 *speed |= IXGBE_LINK_SPEED_100_FULL;
992 /* Internal PHY does not support 100 Mbps */
993 if (hw->mac.type == ixgbe_mac_X550EM_x)
994 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
996 if (hw->mac.type == ixgbe_mac_X550) {
997 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
998 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
1005 * ixgbe_check_phy_link_tnx - Determine link and speed status
1006 * @hw: pointer to hardware structure
1008 * Reads the VS1 register to determine if link is up and the current speed for
1011 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1014 s32 status = IXGBE_SUCCESS;
1016 u32 max_time_out = 10;
1021 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1023 /* Initialize speed and link to default case */
1025 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1028 * Check current speed and link status of the PHY register.
1029 * This is a vendor specific register and may have to
1030 * be changed for other copper PHYs.
1032 for (time_out = 0; time_out < max_time_out; time_out++) {
1034 status = hw->phy.ops.read_reg(hw,
1035 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1036 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1038 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1039 phy_speed = phy_data &
1040 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1041 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1044 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1045 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1054 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1055 * @hw: pointer to hardware structure
1057 * Restart auto-negotiation and PHY and waits for completion.
1059 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1061 s32 status = IXGBE_SUCCESS;
1062 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1063 bool autoneg = FALSE;
1064 ixgbe_link_speed speed;
1066 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1068 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1070 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1071 /* Set or unset auto-negotiation 10G advertisement */
1072 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1073 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1076 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1077 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1078 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1080 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1081 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1085 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1086 /* Set or unset auto-negotiation 1G advertisement */
1087 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1088 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1091 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1092 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1093 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1095 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1096 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1100 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1101 /* Set or unset auto-negotiation 100M advertisement */
1102 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1103 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1106 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1107 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1108 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1110 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1111 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1115 /* Blocked by MNG FW so don't reset PHY */
1116 if (ixgbe_check_reset_blocked(hw))
1119 /* Restart PHY auto-negotiation. */
1120 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1121 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1123 autoneg_reg |= IXGBE_MII_RESTART;
1125 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1126 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1132 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1133 * @hw: pointer to hardware structure
1134 * @firmware_version: pointer to the PHY Firmware Version
1136 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1137 u16 *firmware_version)
1141 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1143 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1144 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1151 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1152 * @hw: pointer to hardware structure
1153 * @firmware_version: pointer to the PHY Firmware Version
1155 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1156 u16 *firmware_version)
1160 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1162 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1163 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1170 * ixgbe_reset_phy_nl - Performs a PHY reset
1171 * @hw: pointer to hardware structure
1173 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1175 u16 phy_offset, control, eword, edata, block_crc;
1176 bool end_data = FALSE;
1177 u16 list_offset, data_offset;
1179 s32 ret_val = IXGBE_SUCCESS;
1182 DEBUGFUNC("ixgbe_reset_phy_nl");
1184 /* Blocked by MNG FW so bail */
1185 if (ixgbe_check_reset_blocked(hw))
1188 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1189 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1191 /* reset the PHY and poll for completion */
1192 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1193 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1194 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1196 for (i = 0; i < 100; i++) {
1197 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1198 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1199 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1204 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1205 DEBUGOUT("PHY reset did not complete.\n");
1206 ret_val = IXGBE_ERR_PHY;
1210 /* Get init offsets */
1211 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1213 if (ret_val != IXGBE_SUCCESS)
1216 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1220 * Read control word from PHY init contents offset
1222 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1225 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1226 IXGBE_CONTROL_SHIFT_NL;
1227 edata = eword & IXGBE_DATA_MASK_NL;
1229 case IXGBE_DELAY_NL:
1231 DEBUGOUT1("DELAY: %d MS\n", edata);
1235 DEBUGOUT("DATA:\n");
1237 ret_val = hw->eeprom.ops.read(hw, data_offset,
1242 for (i = 0; i < edata; i++) {
1243 ret_val = hw->eeprom.ops.read(hw, data_offset,
1247 hw->phy.ops.write_reg(hw, phy_offset,
1248 IXGBE_TWINAX_DEV, eword);
1249 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1255 case IXGBE_CONTROL_NL:
1257 DEBUGOUT("CONTROL:\n");
1258 if (edata == IXGBE_CONTROL_EOL_NL) {
1261 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1264 DEBUGOUT("Bad control value\n");
1265 ret_val = IXGBE_ERR_PHY;
1270 DEBUGOUT("Bad control type\n");
1271 ret_val = IXGBE_ERR_PHY;
1280 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1281 "eeprom read at offset %d failed", data_offset);
1282 return IXGBE_ERR_PHY;
1286 * ixgbe_identify_module_generic - Identifies module type
1287 * @hw: pointer to hardware structure
1289 * Determines HW type and calls appropriate function.
1291 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1293 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1295 DEBUGFUNC("ixgbe_identify_module_generic");
1297 switch (hw->mac.ops.get_media_type(hw)) {
1298 case ixgbe_media_type_fiber:
1299 status = ixgbe_identify_sfp_module_generic(hw);
1302 case ixgbe_media_type_fiber_qsfp:
1303 status = ixgbe_identify_qsfp_module_generic(hw);
1307 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1308 status = IXGBE_ERR_SFP_NOT_PRESENT;
1316 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1317 * @hw: pointer to hardware structure
1319 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1321 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1323 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1325 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1327 u8 comp_codes_1g = 0;
1328 u8 comp_codes_10g = 0;
1329 u8 oui_bytes[3] = {0, 0, 0};
1332 u16 enforce_sfp = 0;
1334 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1336 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1337 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1338 status = IXGBE_ERR_SFP_NOT_PRESENT;
1342 /* LAN ID is needed for I2C access */
1343 hw->mac.ops.set_lan_id(hw);
1345 status = hw->phy.ops.read_i2c_eeprom(hw,
1346 IXGBE_SFF_IDENTIFIER,
1349 if (status != IXGBE_SUCCESS)
1350 goto err_read_i2c_eeprom;
1352 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1353 hw->phy.type = ixgbe_phy_sfp_unsupported;
1354 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1356 status = hw->phy.ops.read_i2c_eeprom(hw,
1357 IXGBE_SFF_1GBE_COMP_CODES,
1360 if (status != IXGBE_SUCCESS)
1361 goto err_read_i2c_eeprom;
1363 status = hw->phy.ops.read_i2c_eeprom(hw,
1364 IXGBE_SFF_10GBE_COMP_CODES,
1367 if (status != IXGBE_SUCCESS)
1368 goto err_read_i2c_eeprom;
1369 status = hw->phy.ops.read_i2c_eeprom(hw,
1370 IXGBE_SFF_CABLE_TECHNOLOGY,
1373 if (status != IXGBE_SUCCESS)
1374 goto err_read_i2c_eeprom;
1381 * 3 SFP_DA_CORE0 - 82599-specific
1382 * 4 SFP_DA_CORE1 - 82599-specific
1383 * 5 SFP_SR/LR_CORE0 - 82599-specific
1384 * 6 SFP_SR/LR_CORE1 - 82599-specific
1385 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1386 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1387 * 9 SFP_1g_cu_CORE0 - 82599-specific
1388 * 10 SFP_1g_cu_CORE1 - 82599-specific
1389 * 11 SFP_1g_sx_CORE0 - 82599-specific
1390 * 12 SFP_1g_sx_CORE1 - 82599-specific
1392 if (hw->mac.type == ixgbe_mac_82598EB) {
1393 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1394 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1395 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1396 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1397 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1398 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1400 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1402 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1403 if (hw->bus.lan_id == 0)
1405 ixgbe_sfp_type_da_cu_core0;
1408 ixgbe_sfp_type_da_cu_core1;
1409 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1410 hw->phy.ops.read_i2c_eeprom(
1411 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1414 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1415 if (hw->bus.lan_id == 0)
1417 ixgbe_sfp_type_da_act_lmt_core0;
1420 ixgbe_sfp_type_da_act_lmt_core1;
1423 ixgbe_sfp_type_unknown;
1425 } else if (comp_codes_10g &
1426 (IXGBE_SFF_10GBASESR_CAPABLE |
1427 IXGBE_SFF_10GBASELR_CAPABLE)) {
1428 if (hw->bus.lan_id == 0)
1430 ixgbe_sfp_type_srlr_core0;
1433 ixgbe_sfp_type_srlr_core1;
1434 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1435 if (hw->bus.lan_id == 0)
1437 ixgbe_sfp_type_1g_cu_core0;
1440 ixgbe_sfp_type_1g_cu_core1;
1441 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1442 if (hw->bus.lan_id == 0)
1444 ixgbe_sfp_type_1g_sx_core0;
1447 ixgbe_sfp_type_1g_sx_core1;
1448 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1449 if (hw->bus.lan_id == 0)
1451 ixgbe_sfp_type_1g_lx_core0;
1454 ixgbe_sfp_type_1g_lx_core1;
1456 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1460 if (hw->phy.sfp_type != stored_sfp_type)
1461 hw->phy.sfp_setup_needed = TRUE;
1463 /* Determine if the SFP+ PHY is dual speed or not. */
1464 hw->phy.multispeed_fiber = FALSE;
1465 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1466 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1467 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1468 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1469 hw->phy.multispeed_fiber = TRUE;
1471 /* Determine PHY vendor */
1472 if (hw->phy.type != ixgbe_phy_nl) {
1473 hw->phy.id = identifier;
1474 status = hw->phy.ops.read_i2c_eeprom(hw,
1475 IXGBE_SFF_VENDOR_OUI_BYTE0,
1478 if (status != IXGBE_SUCCESS)
1479 goto err_read_i2c_eeprom;
1481 status = hw->phy.ops.read_i2c_eeprom(hw,
1482 IXGBE_SFF_VENDOR_OUI_BYTE1,
1485 if (status != IXGBE_SUCCESS)
1486 goto err_read_i2c_eeprom;
1488 status = hw->phy.ops.read_i2c_eeprom(hw,
1489 IXGBE_SFF_VENDOR_OUI_BYTE2,
1492 if (status != IXGBE_SUCCESS)
1493 goto err_read_i2c_eeprom;
1496 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1497 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1498 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1500 switch (vendor_oui) {
1501 case IXGBE_SFF_VENDOR_OUI_TYCO:
1502 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1504 ixgbe_phy_sfp_passive_tyco;
1506 case IXGBE_SFF_VENDOR_OUI_FTL:
1507 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1508 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1510 hw->phy.type = ixgbe_phy_sfp_ftl;
1512 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1513 hw->phy.type = ixgbe_phy_sfp_avago;
1515 case IXGBE_SFF_VENDOR_OUI_INTEL:
1516 hw->phy.type = ixgbe_phy_sfp_intel;
1519 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1521 ixgbe_phy_sfp_passive_unknown;
1522 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1524 ixgbe_phy_sfp_active_unknown;
1526 hw->phy.type = ixgbe_phy_sfp_unknown;
1531 /* Allow any DA cable vendor */
1532 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1533 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1534 status = IXGBE_SUCCESS;
1538 /* Verify supported 1G SFP modules */
1539 if (comp_codes_10g == 0 &&
1540 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1544 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1545 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1546 hw->phy.type = ixgbe_phy_sfp_unsupported;
1547 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1551 /* Anything else 82598-based is supported */
1552 if (hw->mac.type == ixgbe_mac_82598EB) {
1553 status = IXGBE_SUCCESS;
1557 ixgbe_get_device_caps(hw, &enforce_sfp);
1558 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1559 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1562 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1564 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1565 /* Make sure we're a supported PHY type */
1566 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1567 status = IXGBE_SUCCESS;
1569 if (hw->allow_unsupported_sfp == TRUE) {
1570 EWARN(hw, "WARNING: Intel (R) Network "
1571 "Connections are quality tested "
1572 "using Intel (R) Ethernet Optics."
1573 " Using untested modules is not "
1574 "supported and may cause unstable"
1575 " operation or damage to the "
1576 "module or the adapter. Intel "
1577 "Corporation is not responsible "
1578 "for any harm caused by using "
1579 "untested modules.\n", status);
1580 status = IXGBE_SUCCESS;
1582 DEBUGOUT("SFP+ module not supported\n");
1584 ixgbe_phy_sfp_unsupported;
1585 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1589 status = IXGBE_SUCCESS;
1596 err_read_i2c_eeprom:
1597 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1598 if (hw->phy.type != ixgbe_phy_nl) {
1600 hw->phy.type = ixgbe_phy_unknown;
1602 return IXGBE_ERR_SFP_NOT_PRESENT;
1606 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1607 * @hw: pointer to hardware structure
1609 * Determines physical layer capabilities of the current SFP.
1611 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1613 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1614 u8 comp_codes_10g = 0;
1615 u8 comp_codes_1g = 0;
1617 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1619 hw->phy.ops.identify_sfp(hw);
1620 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1621 return physical_layer;
1623 switch (hw->phy.type) {
1624 case ixgbe_phy_sfp_passive_tyco:
1625 case ixgbe_phy_sfp_passive_unknown:
1626 case ixgbe_phy_qsfp_passive_unknown:
1627 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1629 case ixgbe_phy_sfp_ftl_active:
1630 case ixgbe_phy_sfp_active_unknown:
1631 case ixgbe_phy_qsfp_active_unknown:
1632 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1634 case ixgbe_phy_sfp_avago:
1635 case ixgbe_phy_sfp_ftl:
1636 case ixgbe_phy_sfp_intel:
1637 case ixgbe_phy_sfp_unknown:
1638 hw->phy.ops.read_i2c_eeprom(hw,
1639 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1640 hw->phy.ops.read_i2c_eeprom(hw,
1641 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1642 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1643 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1644 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1645 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1646 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1647 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1648 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1649 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1651 case ixgbe_phy_qsfp_intel:
1652 case ixgbe_phy_qsfp_unknown:
1653 hw->phy.ops.read_i2c_eeprom(hw,
1654 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1655 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1656 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1657 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1658 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1664 return physical_layer;
1668 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1669 * @hw: pointer to hardware structure
1671 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1673 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1675 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1677 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1679 u8 comp_codes_1g = 0;
1680 u8 comp_codes_10g = 0;
1681 u8 oui_bytes[3] = {0, 0, 0};
1682 u16 enforce_sfp = 0;
1684 u8 cable_length = 0;
1686 bool active_cable = FALSE;
1688 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1690 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1691 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1692 status = IXGBE_ERR_SFP_NOT_PRESENT;
1696 /* LAN ID is needed for I2C access */
1697 hw->mac.ops.set_lan_id(hw);
1699 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1702 if (status != IXGBE_SUCCESS)
1703 goto err_read_i2c_eeprom;
1705 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1706 hw->phy.type = ixgbe_phy_sfp_unsupported;
1707 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1711 hw->phy.id = identifier;
1713 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1716 if (status != IXGBE_SUCCESS)
1717 goto err_read_i2c_eeprom;
1719 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1722 if (status != IXGBE_SUCCESS)
1723 goto err_read_i2c_eeprom;
1725 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1726 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1727 if (hw->bus.lan_id == 0)
1728 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1730 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1731 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1732 IXGBE_SFF_10GBASELR_CAPABLE)) {
1733 if (hw->bus.lan_id == 0)
1734 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1736 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1738 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1739 active_cable = TRUE;
1741 if (!active_cable) {
1742 /* check for active DA cables that pre-date
1744 hw->phy.ops.read_i2c_eeprom(hw,
1745 IXGBE_SFF_QSFP_CONNECTOR,
1748 hw->phy.ops.read_i2c_eeprom(hw,
1749 IXGBE_SFF_QSFP_CABLE_LENGTH,
1752 hw->phy.ops.read_i2c_eeprom(hw,
1753 IXGBE_SFF_QSFP_DEVICE_TECH,
1757 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1758 (cable_length > 0) &&
1759 ((device_tech >> 4) ==
1760 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1761 active_cable = TRUE;
1765 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1766 if (hw->bus.lan_id == 0)
1768 ixgbe_sfp_type_da_act_lmt_core0;
1771 ixgbe_sfp_type_da_act_lmt_core1;
1773 /* unsupported module type */
1774 hw->phy.type = ixgbe_phy_sfp_unsupported;
1775 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1780 if (hw->phy.sfp_type != stored_sfp_type)
1781 hw->phy.sfp_setup_needed = TRUE;
1783 /* Determine if the QSFP+ PHY is dual speed or not. */
1784 hw->phy.multispeed_fiber = FALSE;
1785 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1786 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1787 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1788 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1789 hw->phy.multispeed_fiber = TRUE;
1791 /* Determine PHY vendor for optical modules */
1792 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1793 IXGBE_SFF_10GBASELR_CAPABLE)) {
1794 status = hw->phy.ops.read_i2c_eeprom(hw,
1795 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1798 if (status != IXGBE_SUCCESS)
1799 goto err_read_i2c_eeprom;
1801 status = hw->phy.ops.read_i2c_eeprom(hw,
1802 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1805 if (status != IXGBE_SUCCESS)
1806 goto err_read_i2c_eeprom;
1808 status = hw->phy.ops.read_i2c_eeprom(hw,
1809 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1812 if (status != IXGBE_SUCCESS)
1813 goto err_read_i2c_eeprom;
1816 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1817 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1818 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1820 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1821 hw->phy.type = ixgbe_phy_qsfp_intel;
1823 hw->phy.type = ixgbe_phy_qsfp_unknown;
1825 ixgbe_get_device_caps(hw, &enforce_sfp);
1826 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1827 /* Make sure we're a supported PHY type */
1828 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1829 status = IXGBE_SUCCESS;
1831 if (hw->allow_unsupported_sfp == TRUE) {
1832 EWARN(hw, "WARNING: Intel (R) Network "
1833 "Connections are quality tested "
1834 "using Intel (R) Ethernet Optics."
1835 " Using untested modules is not "
1836 "supported and may cause unstable"
1837 " operation or damage to the "
1838 "module or the adapter. Intel "
1839 "Corporation is not responsible "
1840 "for any harm caused by using "
1841 "untested modules.\n", status);
1842 status = IXGBE_SUCCESS;
1844 DEBUGOUT("QSFP module not supported\n");
1846 ixgbe_phy_sfp_unsupported;
1847 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1851 status = IXGBE_SUCCESS;
1858 err_read_i2c_eeprom:
1859 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1861 hw->phy.type = ixgbe_phy_unknown;
1863 return IXGBE_ERR_SFP_NOT_PRESENT;
1868 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1869 * @hw: pointer to hardware structure
1870 * @list_offset: offset to the SFP ID list
1871 * @data_offset: offset to the SFP data block
1873 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1874 * so it returns the offsets to the phy init sequence block.
1876 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1881 u16 sfp_type = hw->phy.sfp_type;
1883 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1885 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1886 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1888 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1889 return IXGBE_ERR_SFP_NOT_PRESENT;
1891 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1892 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1893 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1896 * Limiting active cables and 1G Phys must be initialized as
1899 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1900 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1901 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1902 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1903 sfp_type = ixgbe_sfp_type_srlr_core0;
1904 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1905 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1906 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1907 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1908 sfp_type = ixgbe_sfp_type_srlr_core1;
1910 /* Read offset to PHY init contents */
1911 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1912 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1913 "eeprom read at offset %d failed",
1914 IXGBE_PHY_INIT_OFFSET_NL);
1915 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1918 if ((!*list_offset) || (*list_offset == 0xFFFF))
1919 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1921 /* Shift offset to first ID word */
1925 * Find the matching SFP ID in the EEPROM
1926 * and program the init sequence
1928 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1931 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1932 if (sfp_id == sfp_type) {
1934 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1936 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1937 DEBUGOUT("SFP+ module not supported\n");
1938 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1943 (*list_offset) += 2;
1944 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1949 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1950 DEBUGOUT("No matching SFP+ module found\n");
1951 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1954 return IXGBE_SUCCESS;
1957 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1958 "eeprom read at offset %d failed", *list_offset);
1959 return IXGBE_ERR_PHY;
1963 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1964 * @hw: pointer to hardware structure
1965 * @byte_offset: EEPROM byte offset to read
1966 * @eeprom_data: value read
1968 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1970 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1973 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1975 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1976 IXGBE_I2C_EEPROM_DEV_ADDR,
1981 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1982 * @hw: pointer to hardware structure
1983 * @byte_offset: byte offset at address 0xA2
1984 * @eeprom_data: value read
1986 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1988 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1991 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1992 IXGBE_I2C_EEPROM_DEV_ADDR2,
1997 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1998 * @hw: pointer to hardware structure
1999 * @byte_offset: EEPROM byte offset to write
2000 * @eeprom_data: value to write
2002 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2004 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2007 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
2009 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2010 IXGBE_I2C_EEPROM_DEV_ADDR,
2015 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
2016 * @hw: pointer to hardware structure
2017 * @offset: eeprom offset to be read
2018 * @addr: I2C address to be read
2020 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2022 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2023 offset == IXGBE_SFF_IDENTIFIER &&
2024 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2030 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2031 * @hw: pointer to hardware structure
2032 * @byte_offset: byte offset to read
2034 * @lock: TRUE if to take and release semaphore
2036 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2037 * a specified device address.
2039 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2040 u8 dev_addr, u8 *data, bool lock)
2045 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2049 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2051 if (hw->mac.type >= ixgbe_mac_X550)
2053 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2054 max_retry = IXGBE_SFP_DETECT_RETRIES;
2057 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2058 return IXGBE_ERR_SWFW_SYNC;
2060 ixgbe_i2c_start(hw);
2062 /* Device Address and write indication */
2063 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2064 if (status != IXGBE_SUCCESS)
2067 status = ixgbe_get_i2c_ack(hw);
2068 if (status != IXGBE_SUCCESS)
2071 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2072 if (status != IXGBE_SUCCESS)
2075 status = ixgbe_get_i2c_ack(hw);
2076 if (status != IXGBE_SUCCESS)
2079 ixgbe_i2c_start(hw);
2081 /* Device Address and read indication */
2082 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2083 if (status != IXGBE_SUCCESS)
2086 status = ixgbe_get_i2c_ack(hw);
2087 if (status != IXGBE_SUCCESS)
2090 status = ixgbe_clock_in_i2c_byte(hw, data);
2091 if (status != IXGBE_SUCCESS)
2094 status = ixgbe_clock_out_i2c_bit(hw, nack);
2095 if (status != IXGBE_SUCCESS)
2100 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2101 return IXGBE_SUCCESS;
2104 ixgbe_i2c_bus_clear(hw);
2106 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2110 if (retry < max_retry)
2111 DEBUGOUT("I2C byte read error - Retrying.\n");
2113 DEBUGOUT("I2C byte read error.\n");
2115 } while (retry < max_retry);
2121 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2122 * @hw: pointer to hardware structure
2123 * @byte_offset: byte offset to read
2126 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2127 * a specified device address.
2129 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2130 u8 dev_addr, u8 *data)
2132 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2137 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2138 * @hw: pointer to hardware structure
2139 * @byte_offset: byte offset to read
2142 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2143 * a specified device address.
2145 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2146 u8 dev_addr, u8 *data)
2148 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2153 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2154 * @hw: pointer to hardware structure
2155 * @byte_offset: byte offset to write
2156 * @data: value to write
2157 * @lock: TRUE if to take and release semaphore
2159 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2160 * a specified device address.
2162 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2163 u8 dev_addr, u8 data, bool lock)
2168 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2170 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2172 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2174 return IXGBE_ERR_SWFW_SYNC;
2177 ixgbe_i2c_start(hw);
2179 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2180 if (status != IXGBE_SUCCESS)
2183 status = ixgbe_get_i2c_ack(hw);
2184 if (status != IXGBE_SUCCESS)
2187 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2188 if (status != IXGBE_SUCCESS)
2191 status = ixgbe_get_i2c_ack(hw);
2192 if (status != IXGBE_SUCCESS)
2195 status = ixgbe_clock_out_i2c_byte(hw, data);
2196 if (status != IXGBE_SUCCESS)
2199 status = ixgbe_get_i2c_ack(hw);
2200 if (status != IXGBE_SUCCESS)
2205 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2206 return IXGBE_SUCCESS;
2209 ixgbe_i2c_bus_clear(hw);
2211 if (retry < max_retry)
2212 DEBUGOUT("I2C byte write error - Retrying.\n");
2214 DEBUGOUT("I2C byte write error.\n");
2215 } while (retry < max_retry);
2218 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2224 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2225 * @hw: pointer to hardware structure
2226 * @byte_offset: byte offset to write
2227 * @data: value to write
2229 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2230 * a specified device address.
2232 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2233 u8 dev_addr, u8 data)
2235 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2240 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2241 * @hw: pointer to hardware structure
2242 * @byte_offset: byte offset to write
2243 * @data: value to write
2245 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2246 * a specified device address.
2248 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2249 u8 dev_addr, u8 data)
2251 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2256 * ixgbe_i2c_start - Sets I2C start condition
2257 * @hw: pointer to hardware structure
2259 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2260 * Set bit-bang mode on X550 hardware.
2262 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2264 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2266 DEBUGFUNC("ixgbe_i2c_start");
2268 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2270 /* Start condition must begin with data and clock high */
2271 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2272 ixgbe_raise_i2c_clk(hw, &i2cctl);
2274 /* Setup time for start condition (4.7us) */
2275 usec_delay(IXGBE_I2C_T_SU_STA);
2277 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2279 /* Hold time for start condition (4us) */
2280 usec_delay(IXGBE_I2C_T_HD_STA);
2282 ixgbe_lower_i2c_clk(hw, &i2cctl);
2284 /* Minimum low period of clock is 4.7 us */
2285 usec_delay(IXGBE_I2C_T_LOW);
2290 * ixgbe_i2c_stop - Sets I2C stop condition
2291 * @hw: pointer to hardware structure
2293 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2294 * Disables bit-bang mode and negates data output enable on X550
2297 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2299 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2300 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2301 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2302 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2304 DEBUGFUNC("ixgbe_i2c_stop");
2306 /* Stop condition must begin with data low and clock high */
2307 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2308 ixgbe_raise_i2c_clk(hw, &i2cctl);
2310 /* Setup time for stop condition (4us) */
2311 usec_delay(IXGBE_I2C_T_SU_STO);
2313 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2315 /* bus free time between stop and start (4.7us)*/
2316 usec_delay(IXGBE_I2C_T_BUF);
2318 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2319 i2cctl &= ~bb_en_bit;
2320 i2cctl |= data_oe_bit | clk_oe_bit;
2321 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2322 IXGBE_WRITE_FLUSH(hw);
2327 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2328 * @hw: pointer to hardware structure
2329 * @data: data byte to clock in
2331 * Clocks in one byte data via I2C data/clock
2333 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2338 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2341 for (i = 7; i >= 0; i--) {
2342 ixgbe_clock_in_i2c_bit(hw, &bit);
2346 return IXGBE_SUCCESS;
2350 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2351 * @hw: pointer to hardware structure
2352 * @data: data byte clocked out
2354 * Clocks out one byte data via I2C data/clock
2356 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2358 s32 status = IXGBE_SUCCESS;
2363 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2365 for (i = 7; i >= 0; i--) {
2366 bit = (data >> i) & 0x1;
2367 status = ixgbe_clock_out_i2c_bit(hw, bit);
2369 if (status != IXGBE_SUCCESS)
2373 /* Release SDA line (set high) */
2374 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2375 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2376 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2377 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2378 IXGBE_WRITE_FLUSH(hw);
2384 * ixgbe_get_i2c_ack - Polls for I2C ACK
2385 * @hw: pointer to hardware structure
2387 * Clocks in/out one bit via I2C data/clock
2389 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2391 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2392 s32 status = IXGBE_SUCCESS;
2394 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2398 DEBUGFUNC("ixgbe_get_i2c_ack");
2401 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2402 i2cctl |= data_oe_bit;
2403 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2404 IXGBE_WRITE_FLUSH(hw);
2406 ixgbe_raise_i2c_clk(hw, &i2cctl);
2408 /* Minimum high period of clock is 4us */
2409 usec_delay(IXGBE_I2C_T_HIGH);
2411 /* Poll for ACK. Note that ACK in I2C spec is
2412 * transition from 1 to 0 */
2413 for (i = 0; i < timeout; i++) {
2414 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2415 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2423 DEBUGOUT("I2C ack was not received.\n");
2424 status = IXGBE_ERR_I2C;
2427 ixgbe_lower_i2c_clk(hw, &i2cctl);
2429 /* Minimum low period of clock is 4.7 us */
2430 usec_delay(IXGBE_I2C_T_LOW);
2436 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2437 * @hw: pointer to hardware structure
2438 * @data: read data value
2440 * Clocks in one bit via I2C data/clock
2442 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2444 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2445 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2447 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2450 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2451 i2cctl |= data_oe_bit;
2452 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2453 IXGBE_WRITE_FLUSH(hw);
2455 ixgbe_raise_i2c_clk(hw, &i2cctl);
2457 /* Minimum high period of clock is 4us */
2458 usec_delay(IXGBE_I2C_T_HIGH);
2460 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2461 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2463 ixgbe_lower_i2c_clk(hw, &i2cctl);
2465 /* Minimum low period of clock is 4.7 us */
2466 usec_delay(IXGBE_I2C_T_LOW);
2468 return IXGBE_SUCCESS;
2472 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2473 * @hw: pointer to hardware structure
2474 * @data: data value to write
2476 * Clocks out one bit via I2C data/clock
2478 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2481 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2483 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2485 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2486 if (status == IXGBE_SUCCESS) {
2487 ixgbe_raise_i2c_clk(hw, &i2cctl);
2489 /* Minimum high period of clock is 4us */
2490 usec_delay(IXGBE_I2C_T_HIGH);
2492 ixgbe_lower_i2c_clk(hw, &i2cctl);
2494 /* Minimum low period of clock is 4.7 us.
2495 * This also takes care of the data hold time.
2497 usec_delay(IXGBE_I2C_T_LOW);
2499 status = IXGBE_ERR_I2C;
2500 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2501 "I2C data was not set to %X\n", data);
2508 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2509 * @hw: pointer to hardware structure
2510 * @i2cctl: Current value of I2CCTL register
2512 * Raises the I2C clock line '0'->'1'
2513 * Negates the I2C clock output enable on X550 hardware.
2515 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2517 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2519 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2522 DEBUGFUNC("ixgbe_raise_i2c_clk");
2525 *i2cctl |= clk_oe_bit;
2526 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2529 for (i = 0; i < timeout; i++) {
2530 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2532 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2533 IXGBE_WRITE_FLUSH(hw);
2534 /* SCL rise time (1000ns) */
2535 usec_delay(IXGBE_I2C_T_RISE);
2537 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2538 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2544 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2545 * @hw: pointer to hardware structure
2546 * @i2cctl: Current value of I2CCTL register
2548 * Lowers the I2C clock line '1'->'0'
2549 * Asserts the I2C clock output enable on X550 hardware.
2551 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2553 DEBUGFUNC("ixgbe_lower_i2c_clk");
2555 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2556 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2558 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2559 IXGBE_WRITE_FLUSH(hw);
2561 /* SCL fall time (300ns) */
2562 usec_delay(IXGBE_I2C_T_FALL);
2566 * ixgbe_set_i2c_data - Sets the I2C data bit
2567 * @hw: pointer to hardware structure
2568 * @i2cctl: Current value of I2CCTL register
2569 * @data: I2C data value (0 or 1) to set
2571 * Sets the I2C data bit
2572 * Asserts the I2C data output enable on X550 hardware.
2574 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2576 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2577 s32 status = IXGBE_SUCCESS;
2579 DEBUGFUNC("ixgbe_set_i2c_data");
2582 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2584 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2585 *i2cctl &= ~data_oe_bit;
2587 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2588 IXGBE_WRITE_FLUSH(hw);
2590 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2591 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2593 if (!data) /* Can't verify data in this case */
2594 return IXGBE_SUCCESS;
2596 *i2cctl |= data_oe_bit;
2597 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2598 IXGBE_WRITE_FLUSH(hw);
2601 /* Verify data was set correctly */
2602 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2603 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2604 status = IXGBE_ERR_I2C;
2605 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2606 "Error - I2C data was not set to %X.\n",
2614 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2615 * @hw: pointer to hardware structure
2616 * @i2cctl: Current value of I2CCTL register
2618 * Returns the I2C data bit value
2619 * Negates the I2C data output enable on X550 hardware.
2621 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2623 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2626 DEBUGFUNC("ixgbe_get_i2c_data");
2629 *i2cctl |= data_oe_bit;
2630 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2631 IXGBE_WRITE_FLUSH(hw);
2632 usec_delay(IXGBE_I2C_T_FALL);
2635 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2644 * ixgbe_i2c_bus_clear - Clears the I2C bus
2645 * @hw: pointer to hardware structure
2647 * Clears the I2C bus by sending nine clock pulses.
2648 * Used when data line is stuck low.
2650 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2655 DEBUGFUNC("ixgbe_i2c_bus_clear");
2657 ixgbe_i2c_start(hw);
2658 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2660 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2662 for (i = 0; i < 9; i++) {
2663 ixgbe_raise_i2c_clk(hw, &i2cctl);
2665 /* Min high period of clock is 4us */
2666 usec_delay(IXGBE_I2C_T_HIGH);
2668 ixgbe_lower_i2c_clk(hw, &i2cctl);
2670 /* Min low period of clock is 4.7us*/
2671 usec_delay(IXGBE_I2C_T_LOW);
2674 ixgbe_i2c_start(hw);
2676 /* Put the i2c bus back to default state */
2681 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2682 * @hw: pointer to hardware structure
2684 * Checks if the LASI temp alarm status was triggered due to overtemp
2686 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2688 s32 status = IXGBE_SUCCESS;
2691 DEBUGFUNC("ixgbe_tn_check_overtemp");
2693 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2696 /* Check that the LASI temp alarm status was triggered */
2697 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2698 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2700 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2703 status = IXGBE_ERR_OVERTEMP;
2704 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2710 * ixgbe_set_copper_phy_power - Control power for copper phy
2711 * @hw: pointer to hardware structure
2712 * @on: TRUE for on, FALSE for off
2714 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2719 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2720 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2726 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2728 if (ixgbe_check_reset_blocked(hw))
2730 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2733 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2734 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,