sys/dev/ixgbe/ixgbe_phy.c

   1 /******************************************************************************
   2   SPDX-License-Identifier: BSD-3-Clause
   3
   4   Copyright (c) 2001-2017, Intel Corporation
   5   All rights reserved.
   6
   7   Redistribution and use in source and binary forms, with or without
   8   modification, are permitted provided that the following conditions are met:
   9
  10    1. Redistributions of source code must retain the above copyright notice,
  11       this list of conditions and the following disclaimer.
  12
  13    2. Redistributions in binary form must reproduce the above copyright
  14       notice, this list of conditions and the following disclaimer in the
  15       documentation and/or other materials provided with the distribution.
  16
  17    3. Neither the name of the Intel Corporation nor the names of its
  18       contributors may be used to endorse or promote products derived from
  19       this software without specific prior written permission.
  20
  21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  31   POSSIBILITY OF SUCH DAMAGE.
  32
  33 ******************************************************************************/
  34 /*$FreeBSD$*/
  35
  36 #include "ixgbe_api.h"
  37 #include "ixgbe_common.h"
  38 #include "ixgbe_phy.h"
  39
  40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  52                                           u8 *sff8472_data);
  53
  54 /**
  55  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  56  * @hw: pointer to the hardware structure
  57  * @byte: byte to send
  58  *
  59  * Returns an error code on error.
  60  */
  61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  62 {
  63         s32 status;
  64
  65         status = ixgbe_clock_out_i2c_byte(hw, byte);
  66         if (status)
  67                 return status;
  68         return ixgbe_get_i2c_ack(hw);
  69 }
  70
  71 /**
  72  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  73  * @hw: pointer to the hardware structure
  74  * @byte: pointer to a u8 to receive the byte
  75  *
  76  * Returns an error code on error.
  77  */
  78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  79 {
  80         s32 status;
  81
  82         status = ixgbe_clock_in_i2c_byte(hw, byte);
  83         if (status)
  84                 return status;
  85         /* ACK */
  86         return ixgbe_clock_out_i2c_bit(hw, FALSE);
  87 }
  88
  89 /**
  90  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  91  * @add1 - addend 1
  92  * @add2 - addend 2
  93  *
  94  * Returns one's complement 8-bit sum.
  95  */
  96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  97 {
  98         u16 sum = add1 + add2;
  99
 100         sum = (sum & 0xFF) + (sum >> 8);
 101         return sum & 0xFF;
 102 }
 103
 104 /**
 105  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
 106  * @hw: pointer to the hardware structure
 107  * @addr: I2C bus address to read from
 108  * @reg: I2C device register to read from
 109  * @val: pointer to location to receive read value
 110  * @lock: TRUE if to take and release semaphore
 111  *
 112  * Returns an error code on error.
 113  */
 114 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 115                                         u16 *val, bool lock)
 116 {
 117         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 118         int max_retry = 3;
 119         int retry = 0;
 120         u8 csum_byte;
 121         u8 high_bits;
 122         u8 low_bits;
 123         u8 reg_high;
 124         u8 csum;
 125
 126         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 127         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 128         csum = ~csum;
 129         do {
 130                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 131                         return IXGBE_ERR_SWFW_SYNC;
 132                 ixgbe_i2c_start(hw);
 133                 /* Device Address and write indication */
 134                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 135                         goto fail;
 136                 /* Write bits 14:8 */
 137                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 138                         goto fail;
 139                 /* Write bits 7:0 */
 140                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 141                         goto fail;
 142                 /* Write csum */
 143                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 144                         goto fail;
 145                 /* Re-start condition */
 146                 ixgbe_i2c_start(hw);
 147                 /* Device Address and read indication */
 148                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 149                         goto fail;
 150                 /* Get upper bits */
 151                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 152                         goto fail;
 153                 /* Get low bits */
 154                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 155                         goto fail;
 156                 /* Get csum */
 157                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 158                         goto fail;
 159                 /* NACK */
 160                 if (ixgbe_clock_out_i2c_bit(hw, FALSE))
 161                         goto fail;
 162                 ixgbe_i2c_stop(hw);
 163                 if (lock)
 164                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 165                 *val = (high_bits << 8) | low_bits;
 166                 return 0;
 167
 168 fail:
 169                 ixgbe_i2c_bus_clear(hw);
 170                 if (lock)
 171                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 172                 retry++;
 173                 if (retry < max_retry)
 174                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 175                 else
 176                         DEBUGOUT("I2C byte read combined error.\n");
 177         } while (retry < max_retry);
 178
 179         return IXGBE_ERR_I2C;
 180 }
 181
 182 /**
 183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
 184  * @hw: pointer to the hardware structure
 185  * @addr: I2C bus address to write to
 186  * @reg: I2C device register to write to
 187  * @val: value to write
 188  * @lock: TRUE if to take and release semaphore
 189  *
 190  * Returns an error code on error.
 191  */
 192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
 193                                          u16 val, bool lock)
 194 {
 195         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 196         int max_retry = 1;
 197         int retry = 0;
 198         u8 reg_high;
 199         u8 csum;
 200
 201         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 202         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 203         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 204         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 205         csum = ~csum;
 206         do {
 207                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 208                         return IXGBE_ERR_SWFW_SYNC;
 209                 ixgbe_i2c_start(hw);
 210                 /* Device Address and write indication */
 211                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 212                         goto fail;
 213                 /* Write bits 14:8 */
 214                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 215                         goto fail;
 216                 /* Write bits 7:0 */
 217                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 218                         goto fail;
 219                 /* Write data 15:8 */
 220                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 221                         goto fail;
 222                 /* Write data 7:0 */
 223                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 224                         goto fail;
 225                 /* Write csum */
 226                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 227                         goto fail;
 228                 ixgbe_i2c_stop(hw);
 229                 if (lock)
 230                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 231                 return 0;
 232
 233 fail:
 234                 ixgbe_i2c_bus_clear(hw);
 235                 if (lock)
 236                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 237                 retry++;
 238                 if (retry < max_retry)
 239                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 240                 else
 241                         DEBUGOUT("I2C byte write combined error.\n");
 242         } while (retry < max_retry);
 243
 244         return IXGBE_ERR_I2C;
 245 }
 246
 247 /**
 248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 249  *  @hw: pointer to the hardware structure
 250  *
 251  *  Initialize the function pointers.
 252  **/
 253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 254 {
 255         struct ixgbe_phy_info *phy = &hw->phy;
 256
 257         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 258
 259         /* PHY */
 260         phy->ops.identify = ixgbe_identify_phy_generic;
 261         phy->ops.reset = ixgbe_reset_phy_generic;
 262         phy->ops.read_reg = ixgbe_read_phy_reg_generic;
 263         phy->ops.write_reg = ixgbe_write_phy_reg_generic;
 264         phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
 265         phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
 266         phy->ops.setup_link = ixgbe_setup_phy_link_generic;
 267         phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
 268         phy->ops.check_link = NULL;
 269         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 270         phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
 271         phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
 272         phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
 273         phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
 274         phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
 275         phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
 276         phy->ops.identify_sfp = ixgbe_identify_module_generic;
 277         phy->sfp_type = ixgbe_sfp_type_unknown;
 278         phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
 279         phy->ops.write_i2c_byte_unlocked =
 280                                 ixgbe_write_i2c_byte_generic_unlocked;
 281         phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
 282         return IXGBE_SUCCESS;
 283 }
 284
 285 /**
 286  * ixgbe_probe_phy - Probe a single address for a PHY
 287  * @hw: pointer to hardware structure
 288  * @phy_addr: PHY address to probe
 289  *
 290  * Returns TRUE if PHY found
 291  */
 292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
 293 {
 294         u16 ext_ability = 0;
 295
 296         if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
 297                 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
 298                         phy_addr);
 299                 return FALSE;
 300         }
 301
 302         if (ixgbe_get_phy_id(hw))
 303                 return FALSE;
 304
 305         hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
 306
 307         if (hw->phy.type == ixgbe_phy_unknown) {
 308                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
 309                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 310                 if (ext_ability &
 311                     (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 312                      IXGBE_MDIO_PHY_1000BASET_ABILITY))
 313                         hw->phy.type = ixgbe_phy_cu_unknown;
 314                 else
 315                         hw->phy.type = ixgbe_phy_generic;
 316         }
 317
 318         return TRUE;
 319 }
 320
 321 /**
 322  *  ixgbe_identify_phy_generic - Get physical layer module
 323  *  @hw: pointer to hardware structure
 324  *
 325  *  Determines the physical layer module found on the current adapter.
 326  **/
 327 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 328 {
 329         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 330         u16 phy_addr;
 331
 332         DEBUGFUNC("ixgbe_identify_phy_generic");
 333
 334         if (!hw->phy.phy_semaphore_mask) {
 335                 if (hw->bus.lan_id)
 336                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 337                 else
 338                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 339         }
 340
 341         if (hw->phy.type != ixgbe_phy_unknown)
 342                 return IXGBE_SUCCESS;
 343
 344         if (hw->phy.nw_mng_if_sel) {
 345                 phy_addr = (hw->phy.nw_mng_if_sel &
 346                             IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
 347                            IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
 348                 if (ixgbe_probe_phy(hw, phy_addr))
 349                         return IXGBE_SUCCESS;
 350                 else
 351                         return IXGBE_ERR_PHY_ADDR_INVALID;
 352         }
 353
 354         for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 355                 if (ixgbe_probe_phy(hw, phy_addr)) {
 356                         status = IXGBE_SUCCESS;
 357                         break;
 358                 }
 359         }
 360
 361         /* Certain media types do not have a phy so an address will not
 362          * be found and the code will take this path.  Caller has to
 363          * decide if it is an error or not.
 364          */
 365         if (status != IXGBE_SUCCESS)
 366                 hw->phy.addr = 0;
 367
 368         return status;
 369 }
 370
 371 /**
 372  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 373  * @hw: pointer to the hardware structure
 374  *
 375  * This function checks the MMNGC.MNG_VETO bit to see if there are
 376  * any constraints on link from manageability.  For MAC's that don't
 377  * have this bit just return faluse since the link can not be blocked
 378  * via this method.
 379  **/
 380 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 381 {
 382         u32 mmngc;
 383
 384         DEBUGFUNC("ixgbe_check_reset_blocked");
 385
 386         /* If we don't have this bit, it can't be blocking */
 387         if (hw->mac.type == ixgbe_mac_82598EB)
 388                 return FALSE;
 389
 390         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 391         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 392                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 393                               "MNG_VETO bit detected.\n");
 394                 return TRUE;
 395         }
 396
 397         return FALSE;
 398 }
 399
 400 /**
 401  *  ixgbe_validate_phy_addr - Determines phy address is valid
 402  *  @hw: pointer to hardware structure
 403  *
 404  **/
 405 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 406 {
 407         u16 phy_id = 0;
 408         bool valid = FALSE;
 409
 410         DEBUGFUNC("ixgbe_validate_phy_addr");
 411
 412         hw->phy.addr = phy_addr;
 413         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 414                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 415
 416         if (phy_id != 0xFFFF && phy_id != 0x0)
 417                 valid = TRUE;
 418
 419         DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
 420
 421         return valid;
 422 }
 423
 424 /**
 425  *  ixgbe_get_phy_id - Get the phy type
 426  *  @hw: pointer to hardware structure
 427  *
 428  **/
 429 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 430 {
 431         u32 status;
 432         u16 phy_id_high = 0;
 433         u16 phy_id_low = 0;
 434
 435         DEBUGFUNC("ixgbe_get_phy_id");
 436
 437         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 438                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 439                                       &phy_id_high);
 440
 441         if (status == IXGBE_SUCCESS) {
 442                 hw->phy.id = (u32)(phy_id_high << 16);
 443                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 444                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 445                                               &phy_id_low);
 446                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 447                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 448         }
 449         DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
 450                   phy_id_high, phy_id_low);
 451
 452         return status;
 453 }
 454
 455 /**
 456  *  ixgbe_get_phy_type_from_id - Get the phy type
 457  *  @phy_id: PHY ID information
 458  *
 459  **/
 460 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 461 {
 462         enum ixgbe_phy_type phy_type;
 463
 464         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 465
 466         switch (phy_id) {
 467         case TN1010_PHY_ID:
 468                 phy_type = ixgbe_phy_tn;
 469                 break;
 470         case X550_PHY_ID2:
 471         case X550_PHY_ID3:
 472         case X540_PHY_ID:
 473                 phy_type = ixgbe_phy_aq;
 474                 break;
 475         case QT2022_PHY_ID:
 476                 phy_type = ixgbe_phy_qt;
 477                 break;
 478         case ATH_PHY_ID:
 479                 phy_type = ixgbe_phy_nl;
 480                 break;
 481         case X557_PHY_ID:
 482         case X557_PHY_ID2:
 483                 phy_type = ixgbe_phy_x550em_ext_t;
 484                 break;
 485         case IXGBE_M88E1500_E_PHY_ID:
 486         case IXGBE_M88E1543_E_PHY_ID:
 487                 phy_type = ixgbe_phy_ext_1g_t;
 488                 break;
 489         default:
 490                 phy_type = ixgbe_phy_unknown;
 491                 break;
 492         }
 493         return phy_type;
 494 }
 495
 496 /**
 497  *  ixgbe_reset_phy_generic - Performs a PHY reset
 498  *  @hw: pointer to hardware structure
 499  **/
 500 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 501 {
 502         u32 i;
 503         u16 ctrl = 0;
 504         s32 status = IXGBE_SUCCESS;
 505
 506         DEBUGFUNC("ixgbe_reset_phy_generic");
 507
 508         if (hw->phy.type == ixgbe_phy_unknown)
 509                 status = ixgbe_identify_phy_generic(hw);
 510
 511         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 512                 goto out;
 513
 514         /* Don't reset PHY if it's shut down due to overtemp. */
 515         if (!hw->phy.reset_if_overtemp &&
 516             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 517                 goto out;
 518
 519         /* Blocked by MNG FW so bail */
 520         if (ixgbe_check_reset_blocked(hw))
 521                 goto out;
 522
 523         /*
 524          * Perform soft PHY reset to the PHY_XS.
 525          * This will cause a soft reset to the PHY
 526          */
 527         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 528                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 529                               IXGBE_MDIO_PHY_XS_RESET);
 530
 531         /*
 532          * Poll for reset bit to self-clear indicating reset is complete.
 533          * Some PHYs could take up to 3 seconds to complete and need about
 534          * 1.7 usec delay after the reset is complete.
 535          */
 536         for (i = 0; i < 30; i++) {
 537                 msec_delay(100);
 538                 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
 539                         status = hw->phy.ops.read_reg(hw,
 540                                                   IXGBE_MDIO_TX_VENDOR_ALARMS_3,
 541                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 542                                                   &ctrl);
 543                         if (status != IXGBE_SUCCESS)
 544                                 return status;
 545
 546                         if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
 547                                 usec_delay(2);
 548                                 break;
 549                         }
 550                 } else {
 551                         status = hw->phy.ops.read_reg(hw,
 552                                                      IXGBE_MDIO_PHY_XS_CONTROL,
 553                                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 554                                                      &ctrl);
 555                         if (status != IXGBE_SUCCESS)
 556                                 return status;
 557
 558                         if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 559                                 usec_delay(2);
 560                                 break;
 561                         }
 562                 }
 563         }
 564
 565         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 566                 status = IXGBE_ERR_RESET_FAILED;
 567                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 568                              "PHY reset polling failed to complete.\n");
 569         }
 570
 571 out:
 572         return status;
 573 }
 574
 575 /**
 576  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 577  *  the SWFW lock
 578  *  @hw: pointer to hardware structure
 579  *  @reg_addr: 32 bit address of PHY register to read
 580  *  @phy_data: Pointer to read data from PHY register
 581  **/
 582 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 583                            u16 *phy_data)
 584 {
 585         u32 i, data, command;
 586
 587         /* Setup and write the address cycle command */
 588         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 589                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 590                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 591                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 592
 593         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 594
 595         /*
 596          * Check every 10 usec to see if the address cycle completed.
 597          * The MDI Command bit will clear when the operation is
 598          * complete
 599          */
 600         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 601                 usec_delay(10);
 602
 603                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 604                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 605                         break;
 606         }
 607
 608
 609         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 610                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 611                 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
 612                 return IXGBE_ERR_PHY;
 613         }
 614
 615         /*
 616          * Address cycle complete, setup and write the read
 617          * command
 618          */
 619         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 620                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 621                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 622                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 623
 624         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 625
 626         /*
 627          * Check every 10 usec to see if the address cycle
 628          * completed. The MDI Command bit will clear when the
 629          * operation is complete
 630          */
 631         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 632                 usec_delay(10);
 633
 634                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 635                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 636                         break;
 637         }
 638
 639         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 640                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 641                 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
 642                 return IXGBE_ERR_PHY;
 643         }
 644
 645         /*
 646          * Read operation is complete.  Get the data
 647          * from MSRWD
 648          */
 649         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 650         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 651         *phy_data = (u16)(data);
 652
 653         return IXGBE_SUCCESS;
 654 }
 655
 656 /**
 657  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 658  *  using the SWFW lock - this function is needed in most cases
 659  *  @hw: pointer to hardware structure
 660  *  @reg_addr: 32 bit address of PHY register to read
 661  *  @phy_data: Pointer to read data from PHY register
 662  **/
 663 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 664                                u32 device_type, u16 *phy_data)
 665 {
 666         s32 status;
 667         u32 gssr = hw->phy.phy_semaphore_mask;
 668
 669         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 670
 671         if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
 672                 return IXGBE_ERR_SWFW_SYNC;
 673
 674         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
 675
 676         hw->mac.ops.release_swfw_sync(hw, gssr);
 677
 678         return status;
 679 }
 680
 681 /**
 682  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 683  *  without SWFW lock
 684  *  @hw: pointer to hardware structure
 685  *  @reg_addr: 32 bit PHY register to write
 686  *  @device_type: 5 bit device type
 687  *  @phy_data: Data to write to the PHY register
 688  **/
 689 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 690                                 u32 device_type, u16 phy_data)
 691 {
 692         u32 i, command;
 693
 694         /* Put the data in the MDI single read and write data register*/
 695         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 696
 697         /* Setup and write the address cycle command */
 698         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 699                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 700                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 701                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 702
 703         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 704
 705         /*
 706          * Check every 10 usec to see if the address cycle completed.
 707          * The MDI Command bit will clear when the operation is
 708          * complete
 709          */
 710         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 711                 usec_delay(10);
 712
 713                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 714                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 715                         break;
 716         }
 717
 718         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 719                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 720                 return IXGBE_ERR_PHY;
 721         }
 722
 723         /*
 724          * Address cycle complete, setup and write the write
 725          * command
 726          */
 727         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 728                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 729                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 730                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 731
 732         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 733
 734         /*
 735          * Check every 10 usec to see if the address cycle
 736          * completed. The MDI Command bit will clear when the
 737          * operation is complete
 738          */
 739         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 740                 usec_delay(10);
 741
 742                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 743                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 744                         break;
 745         }
 746
 747         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 748                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 749                 return IXGBE_ERR_PHY;
 750         }
 751
 752         return IXGBE_SUCCESS;
 753 }
 754
 755 /**
 756  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 757  *  using SWFW lock- this function is needed in most cases
 758  *  @hw: pointer to hardware structure
 759  *  @reg_addr: 32 bit PHY register to write
 760  *  @device_type: 5 bit device type
 761  *  @phy_data: Data to write to the PHY register
 762  **/
 763 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 764                                 u32 device_type, u16 phy_data)
 765 {
 766         s32 status;
 767         u32 gssr = hw->phy.phy_semaphore_mask;
 768
 769         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 770
 771         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 772                 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
 773                                                  phy_data);
 774                 hw->mac.ops.release_swfw_sync(hw, gssr);
 775         } else {
 776                 status = IXGBE_ERR_SWFW_SYNC;
 777         }
 778
 779         return status;
 780 }
 781
 782 /**
 783  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 784  *  @hw: pointer to hardware structure
 785  *
 786  *  Restart auto-negotiation and PHY and waits for completion.
 787  **/
 788 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 789 {
 790         s32 status = IXGBE_SUCCESS;
 791         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 792         bool autoneg = FALSE;
 793         ixgbe_link_speed speed;
 794
 795         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 796
 797         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 798
 799         /* Set or unset auto-negotiation 10G advertisement */
 800         hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 801                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 802                              &autoneg_reg);
 803
 804         autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 805         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
 806             (speed & IXGBE_LINK_SPEED_10GB_FULL))
 807                 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 808
 809         hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 810                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 811                               autoneg_reg);
 812
 813         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 814                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 815                              &autoneg_reg);
 816
 817         if (hw->mac.type == ixgbe_mac_X550) {
 818                 /* Set or unset auto-negotiation 5G advertisement */
 819                 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
 820                 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
 821                     (speed & IXGBE_LINK_SPEED_5GB_FULL))
 822                         autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
 823
 824                 /* Set or unset auto-negotiation 2.5G advertisement */
 825                 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
 826                 if ((hw->phy.autoneg_advertised &
 827                      IXGBE_LINK_SPEED_2_5GB_FULL) &&
 828                     (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
 829                         autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
 830         }
 831
 832         /* Set or unset auto-negotiation 1G advertisement */
 833         autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 834         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
 835             (speed & IXGBE_LINK_SPEED_1GB_FULL))
 836                 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 837
 838         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 839                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 840                               autoneg_reg);
 841
 842         /* Set or unset auto-negotiation 100M advertisement */
 843         hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 844                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 845                              &autoneg_reg);
 846
 847         autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 848                          IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 849         if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
 850             (speed & IXGBE_LINK_SPEED_100_FULL))
 851                 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 852
 853         hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 854                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 855                               autoneg_reg);
 856
 857         /* Blocked by MNG FW so don't reset PHY */
 858         if (ixgbe_check_reset_blocked(hw))
 859                 return status;
 860
 861         /* Restart PHY auto-negotiation. */
 862         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 863                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 864
 865         autoneg_reg |= IXGBE_MII_RESTART;
 866
 867         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 868                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 869
 870         return status;
 871 }
 872
 873 /**
 874  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 875  *  @hw: pointer to hardware structure
 876  *  @speed: new link speed
 877  **/
 878 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 879                                        ixgbe_link_speed speed,
 880                                        bool autoneg_wait_to_complete)
 881 {
 882         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 883
 884         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 885
 886         /*
 887          * Clear autoneg_advertised and set new values based on input link
 888          * speed.
 889          */
 890         hw->phy.autoneg_advertised = 0;
 891
 892         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 893                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 894
 895         if (speed & IXGBE_LINK_SPEED_5GB_FULL)
 896                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
 897
 898         if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
 899                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
 900
 901         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 902                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 903
 904         if (speed & IXGBE_LINK_SPEED_100_FULL)
 905                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 906
 907         if (speed & IXGBE_LINK_SPEED_10_FULL)
 908                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
 909
 910         /* Setup link based on the new speed settings */
 911         ixgbe_setup_phy_link(hw);
 912
 913         return IXGBE_SUCCESS;
 914 }
 915
 916 /**
 917  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
 918  * @hw: pointer to hardware structure
 919  *
 920  * Determines the supported link capabilities by reading the PHY auto
 921  * negotiation register.
 922  **/
 923 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
 924 {
 925         s32 status;
 926         u16 speed_ability;
 927
 928         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 929                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 930                                       &speed_ability);
 931         if (status)
 932                 return status;
 933
 934         if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 935                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
 936         if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 937                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
 938         if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 939                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
 940
 941         switch (hw->mac.type) {
 942         case ixgbe_mac_X550:
 943                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
 944                 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
 945                 break;
 946         case ixgbe_mac_X550EM_x:
 947         case ixgbe_mac_X550EM_a:
 948                 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
 949                 break;
 950         default:
 951                 break;
 952         }
 953
 954         return status;
 955 }
 956
 957 /**
 958  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 959  *  @hw: pointer to hardware structure
 960  *  @speed: pointer to link speed
 961  *  @autoneg: boolean auto-negotiation value
 962  **/
 963 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 964                                                ixgbe_link_speed *speed,
 965                                                bool *autoneg)
 966 {
 967         s32 status = IXGBE_SUCCESS;
 968
 969         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 970
 971         *autoneg = TRUE;
 972         if (!hw->phy.speeds_supported)
 973                 status = ixgbe_get_copper_speeds_supported(hw);
 974
 975         *speed = hw->phy.speeds_supported;
 976         return status;
 977 }
 978
 979 /**
 980  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 981  *  @hw: pointer to hardware structure
 982  *
 983  *  Reads the VS1 register to determine if link is up and the current speed for
 984  *  the PHY.
 985  **/
 986 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 987                              bool *link_up)
 988 {
 989         s32 status = IXGBE_SUCCESS;
 990         u32 time_out;
 991         u32 max_time_out = 10;
 992         u16 phy_link = 0;
 993         u16 phy_speed = 0;
 994         u16 phy_data = 0;
 995
 996         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 997
 998         /* Initialize speed and link to default case */
 999         *link_up = FALSE;
1000         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1001
1002         /*
1003          * Check current speed and link status of the PHY register.
1004          * This is a vendor specific register and may have to
1005          * be changed for other copper PHYs.
1006          */
1007         for (time_out = 0; time_out < max_time_out; time_out++) {
1008                 usec_delay(10);
1009                 status = hw->phy.ops.read_reg(hw,
1010                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1011                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1012                                         &phy_data);
1013                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1014                 phy_speed = phy_data &
1015                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1016                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1017                         *link_up = TRUE;
1018                         if (phy_speed ==
1019                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1020                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1021                         break;
1022                 }
1023         }
1024
1025         return status;
1026 }
1027
1028 /**
1029  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1030  *      @hw: pointer to hardware structure
1031  *
1032  *      Restart auto-negotiation and PHY and waits for completion.
1033  **/
1034 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1035 {
1036         s32 status = IXGBE_SUCCESS;
1037         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1038         bool autoneg = FALSE;
1039         ixgbe_link_speed speed;
1040
1041         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1042
1043         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1044
1045         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1046                 /* Set or unset auto-negotiation 10G advertisement */
1047                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1048                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1049                                      &autoneg_reg);
1050
1051                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1052                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1053                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1054
1055                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1056                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1057                                       autoneg_reg);
1058         }
1059
1060         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1061                 /* Set or unset auto-negotiation 1G advertisement */
1062                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1063                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1064                                      &autoneg_reg);
1065
1066                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1067                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1068                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1069
1070                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1071                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1072                                       autoneg_reg);
1073         }
1074
1075         if (speed & IXGBE_LINK_SPEED_100_FULL) {
1076                 /* Set or unset auto-negotiation 100M advertisement */
1077                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1078                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1079                                      &autoneg_reg);
1080
1081                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1082                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1083                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1084
1085                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1086                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1087                                       autoneg_reg);
1088         }
1089
1090         /* Blocked by MNG FW so don't reset PHY */
1091         if (ixgbe_check_reset_blocked(hw))
1092                 return status;
1093
1094         /* Restart PHY auto-negotiation. */
1095         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1096                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1097
1098         autoneg_reg |= IXGBE_MII_RESTART;
1099
1100         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1101                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1102
1103         return status;
1104 }
1105
1106 /**
1107  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1108  *  @hw: pointer to hardware structure
1109  *  @firmware_version: pointer to the PHY Firmware Version
1110  **/
1111 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1112                                        u16 *firmware_version)
1113 {
1114         s32 status;
1115
1116         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1117
1118         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1119                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1120                                       firmware_version);
1121
1122         return status;
1123 }
1124
1125 /**
1126  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1127  *  @hw: pointer to hardware structure
1128  *  @firmware_version: pointer to the PHY Firmware Version
1129  **/
1130 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1131                                            u16 *firmware_version)
1132 {
1133         s32 status;
1134
1135         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1136
1137         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1138                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1139                                       firmware_version);
1140
1141         return status;
1142 }
1143
1144 /**
1145  *  ixgbe_reset_phy_nl - Performs a PHY reset
1146  *  @hw: pointer to hardware structure
1147  **/
1148 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1149 {
1150         u16 phy_offset, control, eword, edata, block_crc;
1151         bool end_data = FALSE;
1152         u16 list_offset, data_offset;
1153         u16 phy_data = 0;
1154         s32 ret_val = IXGBE_SUCCESS;
1155         u32 i;
1156
1157         DEBUGFUNC("ixgbe_reset_phy_nl");
1158
1159         /* Blocked by MNG FW so bail */
1160         if (ixgbe_check_reset_blocked(hw))
1161                 goto out;
1162
1163         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1164                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1165
1166         /* reset the PHY and poll for completion */
1167         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1169                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1170
1171         for (i = 0; i < 100; i++) {
1172                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1173                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1174                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1175                         break;
1176                 msec_delay(10);
1177         }
1178
1179         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1180                 DEBUGOUT("PHY reset did not complete.\n");
1181                 ret_val = IXGBE_ERR_PHY;
1182                 goto out;
1183         }
1184
1185         /* Get init offsets */
1186         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1187                                                       &data_offset);
1188         if (ret_val != IXGBE_SUCCESS)
1189                 goto out;
1190
1191         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1192         data_offset++;
1193         while (!end_data) {
1194                 /*
1195                  * Read control word from PHY init contents offset
1196                  */
1197                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1198                 if (ret_val)
1199                         goto err_eeprom;
1200                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1201                            IXGBE_CONTROL_SHIFT_NL;
1202                 edata = eword & IXGBE_DATA_MASK_NL;
1203                 switch (control) {
1204                 case IXGBE_DELAY_NL:
1205                         data_offset++;
1206                         DEBUGOUT1("DELAY: %d MS\n", edata);
1207                         msec_delay(edata);
1208                         break;
1209                 case IXGBE_DATA_NL:
1210                         DEBUGOUT("DATA:\n");
1211                         data_offset++;
1212                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1213                                                       &phy_offset);
1214                         if (ret_val)
1215                                 goto err_eeprom;
1216                         data_offset++;
1217                         for (i = 0; i < edata; i++) {
1218                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1219                                                               &eword);
1220                                 if (ret_val)
1221                                         goto err_eeprom;
1222                                 hw->phy.ops.write_reg(hw, phy_offset,
1223                                                       IXGBE_TWINAX_DEV, eword);
1224                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1225                                           phy_offset);
1226                                 data_offset++;
1227                                 phy_offset++;
1228                         }
1229                         break;
1230                 case IXGBE_CONTROL_NL:
1231                         data_offset++;
1232                         DEBUGOUT("CONTROL:\n");
1233                         if (edata == IXGBE_CONTROL_EOL_NL) {
1234                                 DEBUGOUT("EOL\n");
1235                                 end_data = TRUE;
1236                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1237                                 DEBUGOUT("SOL\n");
1238                         } else {
1239                                 DEBUGOUT("Bad control value\n");
1240                                 ret_val = IXGBE_ERR_PHY;
1241                                 goto out;
1242                         }
1243                         break;
1244                 default:
1245                         DEBUGOUT("Bad control type\n");
1246                         ret_val = IXGBE_ERR_PHY;
1247                         goto out;
1248                 }
1249         }
1250
1251 out:
1252         return ret_val;
1253
1254 err_eeprom:
1255         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1256                       "eeprom read at offset %d failed", data_offset);
1257         return IXGBE_ERR_PHY;
1258 }
1259
1260 /**
1261  *  ixgbe_identify_module_generic - Identifies module type
1262  *  @hw: pointer to hardware structure
1263  *
1264  *  Determines HW type and calls appropriate function.
1265  **/
1266 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1267 {
1268         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1269
1270         DEBUGFUNC("ixgbe_identify_module_generic");
1271
1272         switch (hw->mac.ops.get_media_type(hw)) {
1273         case ixgbe_media_type_fiber:
1274                 status = ixgbe_identify_sfp_module_generic(hw);
1275                 break;
1276
1277         case ixgbe_media_type_fiber_qsfp:
1278                 status = ixgbe_identify_qsfp_module_generic(hw);
1279                 break;
1280
1281         default:
1282                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1283                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1284                 break;
1285         }
1286
1287         return status;
1288 }
1289
1290 /**
1291  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1292  *  @hw: pointer to hardware structure
1293  *
1294  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1295  **/
1296 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1297 {
1298         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1299         u32 vendor_oui = 0;
1300         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1301         u8 identifier = 0;
1302         u8 comp_codes_1g = 0;
1303         u8 comp_codes_10g = 0;
1304         u8 oui_bytes[3] = {0, 0, 0};
1305         u8 cable_tech = 0;
1306         u8 cable_spec = 0;
1307         u16 enforce_sfp = 0;
1308
1309         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1310
1311         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1312                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1313                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1314                 goto out;
1315         }
1316
1317         /* LAN ID is needed for I2C access */
1318         hw->mac.ops.set_lan_id(hw);
1319
1320         status = hw->phy.ops.read_i2c_eeprom(hw,
1321                                              IXGBE_SFF_IDENTIFIER,
1322                                              &identifier);
1323
1324         if (status != IXGBE_SUCCESS)
1325                 goto err_read_i2c_eeprom;
1326
1327         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1328                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1329                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1330         } else {
1331                 status = hw->phy.ops.read_i2c_eeprom(hw,
1332                                                      IXGBE_SFF_1GBE_COMP_CODES,
1333                                                      &comp_codes_1g);
1334
1335                 if (status != IXGBE_SUCCESS)
1336                         goto err_read_i2c_eeprom;
1337
1338                 status = hw->phy.ops.read_i2c_eeprom(hw,
1339                                                      IXGBE_SFF_10GBE_COMP_CODES,
1340                                                      &comp_codes_10g);
1341
1342                 if (status != IXGBE_SUCCESS)
1343                         goto err_read_i2c_eeprom;
1344                 status = hw->phy.ops.read_i2c_eeprom(hw,
1345                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1346                                                      &cable_tech);
1347
1348                 if (status != IXGBE_SUCCESS)
1349                         goto err_read_i2c_eeprom;
1350
1351                  /* ID Module
1352                   * =========
1353                   * 0   SFP_DA_CU
1354                   * 1   SFP_SR
1355                   * 2   SFP_LR
1356                   * 3   SFP_DA_CORE0 - 82599-specific
1357                   * 4   SFP_DA_CORE1 - 82599-specific
1358                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1359                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1360                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1361                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1362                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1363                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1364                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1365                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1366                   */
1367                 if (hw->mac.type == ixgbe_mac_82598EB) {
1368                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1369                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1370                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1371                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1372                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1373                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1374                         else
1375                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1376                 } else {
1377                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1378                                 if (hw->bus.lan_id == 0)
1379                                         hw->phy.sfp_type =
1380                                                      ixgbe_sfp_type_da_cu_core0;
1381                                 else
1382                                         hw->phy.sfp_type =
1383                                                      ixgbe_sfp_type_da_cu_core1;
1384                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1385                                 hw->phy.ops.read_i2c_eeprom(
1386                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1387                                                 &cable_spec);
1388                                 if (cable_spec &
1389                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1390                                         if (hw->bus.lan_id == 0)
1391                                                 hw->phy.sfp_type =
1392                                                 ixgbe_sfp_type_da_act_lmt_core0;
1393                                         else
1394                                                 hw->phy.sfp_type =
1395                                                 ixgbe_sfp_type_da_act_lmt_core1;
1396                                 } else {
1397                                         hw->phy.sfp_type =
1398                                                         ixgbe_sfp_type_unknown;
1399                                 }
1400                         } else if (comp_codes_10g &
1401                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1402                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1403                                 if (hw->bus.lan_id == 0)
1404                                         hw->phy.sfp_type =
1405                                                       ixgbe_sfp_type_srlr_core0;
1406                                 else
1407                                         hw->phy.sfp_type =
1408                                                       ixgbe_sfp_type_srlr_core1;
1409                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1410                                 if (hw->bus.lan_id == 0)
1411                                         hw->phy.sfp_type =
1412                                                 ixgbe_sfp_type_1g_cu_core0;
1413                                 else
1414                                         hw->phy.sfp_type =
1415                                                 ixgbe_sfp_type_1g_cu_core1;
1416                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1417                                 if (hw->bus.lan_id == 0)
1418                                         hw->phy.sfp_type =
1419                                                 ixgbe_sfp_type_1g_sx_core0;
1420                                 else
1421                                         hw->phy.sfp_type =
1422                                                 ixgbe_sfp_type_1g_sx_core1;
1423                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1424                                 if (hw->bus.lan_id == 0)
1425                                         hw->phy.sfp_type =
1426                                                 ixgbe_sfp_type_1g_lx_core0;
1427                                 else
1428                                         hw->phy.sfp_type =
1429                                                 ixgbe_sfp_type_1g_lx_core1;
1430                         } else {
1431                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1432                         }
1433                 }
1434
1435                 if (hw->phy.sfp_type != stored_sfp_type)
1436                         hw->phy.sfp_setup_needed = TRUE;
1437
1438                 /* Determine if the SFP+ PHY is dual speed or not. */
1439                 hw->phy.multispeed_fiber = FALSE;
1440                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1441                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1442                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1443                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1444                         hw->phy.multispeed_fiber = TRUE;
1445
1446                 /* Determine PHY vendor */
1447                 if (hw->phy.type != ixgbe_phy_nl) {
1448                         hw->phy.id = identifier;
1449                         status = hw->phy.ops.read_i2c_eeprom(hw,
1450                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1451                                                     &oui_bytes[0]);
1452
1453                         if (status != IXGBE_SUCCESS)
1454                                 goto err_read_i2c_eeprom;
1455
1456                         status = hw->phy.ops.read_i2c_eeprom(hw,
1457                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1458                                                     &oui_bytes[1]);
1459
1460                         if (status != IXGBE_SUCCESS)
1461                                 goto err_read_i2c_eeprom;
1462
1463                         status = hw->phy.ops.read_i2c_eeprom(hw,
1464                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1465                                                     &oui_bytes[2]);
1466
1467                         if (status != IXGBE_SUCCESS)
1468                                 goto err_read_i2c_eeprom;
1469
1470                         vendor_oui =
1471                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1472                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1473                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1474
1475                         switch (vendor_oui) {
1476                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1477                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1478                                         hw->phy.type =
1479                                                     ixgbe_phy_sfp_passive_tyco;
1480                                 break;
1481                         case IXGBE_SFF_VENDOR_OUI_FTL:
1482                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1483                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1484                                 else
1485                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1486                                 break;
1487                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1488                                 hw->phy.type = ixgbe_phy_sfp_avago;
1489                                 break;
1490                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1491                                 hw->phy.type = ixgbe_phy_sfp_intel;
1492                                 break;
1493                         default:
1494                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1495                                         hw->phy.type =
1496                                                  ixgbe_phy_sfp_passive_unknown;
1497                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1498                                         hw->phy.type =
1499                                                 ixgbe_phy_sfp_active_unknown;
1500                                 else
1501                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1502                                 break;
1503                         }
1504                 }
1505
1506                 /* Allow any DA cable vendor */
1507                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1508                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1509                         status = IXGBE_SUCCESS;
1510                         goto out;
1511                 }
1512
1513                 /* Verify supported 1G SFP modules */
1514                 if (comp_codes_10g == 0 &&
1515                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1516                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1517                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1518                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1519                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1520                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1521                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1522                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1523                         goto out;
1524                 }
1525
1526                 /* Anything else 82598-based is supported */
1527                 if (hw->mac.type == ixgbe_mac_82598EB) {
1528                         status = IXGBE_SUCCESS;
1529                         goto out;
1530                 }
1531
1532                 ixgbe_get_device_caps(hw, &enforce_sfp);
1533                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1534                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1535                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1536                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1537                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1538                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1539                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1540                         /* Make sure we're a supported PHY type */
1541                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1542                                 status = IXGBE_SUCCESS;
1543                         } else {
1544                                 if (hw->allow_unsupported_sfp == TRUE) {
1545                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1546                                         status = IXGBE_SUCCESS;
1547                                 } else {
1548                                         DEBUGOUT("SFP+ module not supported\n");
1549                                         hw->phy.type =
1550                                                 ixgbe_phy_sfp_unsupported;
1551                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1552                                 }
1553                         }
1554                 } else {
1555                         status = IXGBE_SUCCESS;
1556                 }
1557         }
1558
1559 out:
1560         return status;
1561
1562 err_read_i2c_eeprom:
1563         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1564         if (hw->phy.type != ixgbe_phy_nl) {
1565                 hw->phy.id = 0;
1566                 hw->phy.type = ixgbe_phy_unknown;
1567         }
1568         return IXGBE_ERR_SFP_NOT_PRESENT;
1569 }
1570
1571 /**
1572  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1573  *  @hw: pointer to hardware structure
1574  *
1575  *  Determines physical layer capabilities of the current SFP.
1576  */
1577 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1578 {
1579         u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1580         u8 comp_codes_10g = 0;
1581         u8 comp_codes_1g = 0;
1582
1583         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1584
1585         hw->phy.ops.identify_sfp(hw);
1586         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1587                 return physical_layer;
1588
1589         switch (hw->phy.type) {
1590         case ixgbe_phy_sfp_passive_tyco:
1591         case ixgbe_phy_sfp_passive_unknown:
1592         case ixgbe_phy_qsfp_passive_unknown:
1593                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1594                 break;
1595         case ixgbe_phy_sfp_ftl_active:
1596         case ixgbe_phy_sfp_active_unknown:
1597         case ixgbe_phy_qsfp_active_unknown:
1598                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1599                 break;
1600         case ixgbe_phy_sfp_avago:
1601         case ixgbe_phy_sfp_ftl:
1602         case ixgbe_phy_sfp_intel:
1603         case ixgbe_phy_sfp_unknown:
1604                 hw->phy.ops.read_i2c_eeprom(hw,
1605                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1606                 hw->phy.ops.read_i2c_eeprom(hw,
1607                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1608                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1609                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1610                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1611                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1612                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1613                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1614                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1615                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1616                 break;
1617         case ixgbe_phy_qsfp_intel:
1618         case ixgbe_phy_qsfp_unknown:
1619                 hw->phy.ops.read_i2c_eeprom(hw,
1620                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1621                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1622                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1623                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1624                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1625                 break;
1626         default:
1627                 break;
1628         }
1629
1630         return physical_layer;
1631 }
1632
1633 /**
1634  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1635  *  @hw: pointer to hardware structure
1636  *
1637  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1638  **/
1639 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1640 {
1641         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1642         u32 vendor_oui = 0;
1643         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1644         u8 identifier = 0;
1645         u8 comp_codes_1g = 0;
1646         u8 comp_codes_10g = 0;
1647         u8 oui_bytes[3] = {0, 0, 0};
1648         u16 enforce_sfp = 0;
1649         u8 connector = 0;
1650         u8 cable_length = 0;
1651         u8 device_tech = 0;
1652         bool active_cable = FALSE;
1653
1654         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1655
1656         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1657                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1658                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1659                 goto out;
1660         }
1661
1662         /* LAN ID is needed for I2C access */
1663         hw->mac.ops.set_lan_id(hw);
1664
1665         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1666                                              &identifier);
1667
1668         if (status != IXGBE_SUCCESS)
1669                 goto err_read_i2c_eeprom;
1670
1671         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1672                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1673                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1674                 goto out;
1675         }
1676
1677         hw->phy.id = identifier;
1678
1679         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1680                                              &comp_codes_10g);
1681
1682         if (status != IXGBE_SUCCESS)
1683                 goto err_read_i2c_eeprom;
1684
1685         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1686                                              &comp_codes_1g);
1687
1688         if (status != IXGBE_SUCCESS)
1689                 goto err_read_i2c_eeprom;
1690
1691         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1692                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1693                 if (hw->bus.lan_id == 0)
1694                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1695                 else
1696                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1697         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1698                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1699                 if (hw->bus.lan_id == 0)
1700                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1701                 else
1702                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1703         } else {
1704                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1705                         active_cable = TRUE;
1706
1707                 if (!active_cable) {
1708                         /* check for active DA cables that pre-date
1709                          * SFF-8436 v3.6 */
1710                         hw->phy.ops.read_i2c_eeprom(hw,
1711                                         IXGBE_SFF_QSFP_CONNECTOR,
1712                                         &connector);
1713
1714                         hw->phy.ops.read_i2c_eeprom(hw,
1715                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1716                                         &cable_length);
1717
1718                         hw->phy.ops.read_i2c_eeprom(hw,
1719                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1720                                         &device_tech);
1721
1722                         if ((connector ==
1723                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1724                             (cable_length > 0) &&
1725                             ((device_tech >> 4) ==
1726                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1727                                 active_cable = TRUE;
1728                 }
1729
1730                 if (active_cable) {
1731                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1732                         if (hw->bus.lan_id == 0)
1733                                 hw->phy.sfp_type =
1734                                                 ixgbe_sfp_type_da_act_lmt_core0;
1735                         else
1736                                 hw->phy.sfp_type =
1737                                                 ixgbe_sfp_type_da_act_lmt_core1;
1738                 } else {
1739                         /* unsupported module type */
1740                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1741                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1742                         goto out;
1743                 }
1744         }
1745
1746         if (hw->phy.sfp_type != stored_sfp_type)
1747                 hw->phy.sfp_setup_needed = TRUE;
1748
1749         /* Determine if the QSFP+ PHY is dual speed or not. */
1750         hw->phy.multispeed_fiber = FALSE;
1751         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1752            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1753            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1754            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1755                 hw->phy.multispeed_fiber = TRUE;
1756
1757         /* Determine PHY vendor for optical modules */
1758         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1759                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1760                 status = hw->phy.ops.read_i2c_eeprom(hw,
1761                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1762                                             &oui_bytes[0]);
1763
1764                 if (status != IXGBE_SUCCESS)
1765                         goto err_read_i2c_eeprom;
1766
1767                 status = hw->phy.ops.read_i2c_eeprom(hw,
1768                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1769                                             &oui_bytes[1]);
1770
1771                 if (status != IXGBE_SUCCESS)
1772                         goto err_read_i2c_eeprom;
1773
1774                 status = hw->phy.ops.read_i2c_eeprom(hw,
1775                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1776                                             &oui_bytes[2]);
1777
1778                 if (status != IXGBE_SUCCESS)
1779                         goto err_read_i2c_eeprom;
1780
1781                 vendor_oui =
1782                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1783                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1784                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1785
1786                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1787                         hw->phy.type = ixgbe_phy_qsfp_intel;
1788                 else
1789                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1790
1791                 ixgbe_get_device_caps(hw, &enforce_sfp);
1792                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1793                         /* Make sure we're a supported PHY type */
1794                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1795                                 status = IXGBE_SUCCESS;
1796                         } else {
1797                                 if (hw->allow_unsupported_sfp == TRUE) {
1798                                         EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1799                                         status = IXGBE_SUCCESS;
1800                                 } else {
1801                                         DEBUGOUT("QSFP module not supported\n");
1802                                         hw->phy.type =
1803                                                 ixgbe_phy_sfp_unsupported;
1804                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1805                                 }
1806                         }
1807                 } else {
1808                         status = IXGBE_SUCCESS;
1809                 }
1810         }
1811
1812 out:
1813         return status;
1814
1815 err_read_i2c_eeprom:
1816         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1817         hw->phy.id = 0;
1818         hw->phy.type = ixgbe_phy_unknown;
1819
1820         return IXGBE_ERR_SFP_NOT_PRESENT;
1821 }
1822
1823 /**
1824  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1825  *  @hw: pointer to hardware structure
1826  *  @list_offset: offset to the SFP ID list
1827  *  @data_offset: offset to the SFP data block
1828  *
1829  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1830  *  so it returns the offsets to the phy init sequence block.
1831  **/
1832 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1833                                         u16 *list_offset,
1834                                         u16 *data_offset)
1835 {
1836         u16 sfp_id;
1837         u16 sfp_type = hw->phy.sfp_type;
1838
1839         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1840
1841         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1842                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1843
1844         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1845                 return IXGBE_ERR_SFP_NOT_PRESENT;
1846
1847         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1848             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1849                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1850
1851         /*
1852          * Limiting active cables and 1G Phys must be initialized as
1853          * SR modules
1854          */
1855         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1856             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1857             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1858             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1859                 sfp_type = ixgbe_sfp_type_srlr_core0;
1860         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1861                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1862                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1863                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1864                 sfp_type = ixgbe_sfp_type_srlr_core1;
1865
1866         /* Read offset to PHY init contents */
1867         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1868                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1869                               "eeprom read at offset %d failed",
1870                               IXGBE_PHY_INIT_OFFSET_NL);
1871                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1872         }
1873
1874         if ((!*list_offset) || (*list_offset == 0xFFFF))
1875                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1876
1877         /* Shift offset to first ID word */
1878         (*list_offset)++;
1879
1880         /*
1881          * Find the matching SFP ID in the EEPROM
1882          * and program the init sequence
1883          */
1884         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1885                 goto err_phy;
1886
1887         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1888                 if (sfp_id == sfp_type) {
1889                         (*list_offset)++;
1890                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1891                                 goto err_phy;
1892                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1893                                 DEBUGOUT("SFP+ module not supported\n");
1894                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1895                         } else {
1896                                 break;
1897                         }
1898                 } else {
1899                         (*list_offset) += 2;
1900                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1901                                 goto err_phy;
1902                 }
1903         }
1904
1905         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1906                 DEBUGOUT("No matching SFP+ module found\n");
1907                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1908         }
1909
1910         return IXGBE_SUCCESS;
1911
1912 err_phy:
1913         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1914                       "eeprom read at offset %d failed", *list_offset);
1915         return IXGBE_ERR_PHY;
1916 }
1917
1918 /**
1919  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1920  *  @hw: pointer to hardware structure
1921  *  @byte_offset: EEPROM byte offset to read
1922  *  @eeprom_data: value read
1923  *
1924  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1925  **/
1926 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1927                                   u8 *eeprom_data)
1928 {
1929         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1930
1931         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1932                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1933                                          eeprom_data);
1934 }
1935
1936 /**
1937  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1938  *  @hw: pointer to hardware structure
1939  *  @byte_offset: byte offset at address 0xA2
1940  *  @eeprom_data: value read
1941  *
1942  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1943  **/
1944 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1945                                           u8 *sff8472_data)
1946 {
1947         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1948                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1949                                          sff8472_data);
1950 }
1951
1952 /**
1953  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1954  *  @hw: pointer to hardware structure
1955  *  @byte_offset: EEPROM byte offset to write
1956  *  @eeprom_data: value to write
1957  *
1958  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1959  **/
1960 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1961                                    u8 eeprom_data)
1962 {
1963         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1964
1965         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1966                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1967                                           eeprom_data);
1968 }
1969
1970 /**
1971  * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
1972  * @hw: pointer to hardware structure
1973  * @offset: eeprom offset to be read
1974  * @addr: I2C address to be read
1975  */
1976 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1977 {
1978         if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1979             offset == IXGBE_SFF_IDENTIFIER &&
1980             hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1981                 return TRUE;
1982         return FALSE;
1983 }
1984
1985 /**
1986  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1987  *  @hw: pointer to hardware structure
1988  *  @byte_offset: byte offset to read
1989  *  @data: value read
1990  *  @lock: TRUE if to take and release semaphore
1991  *
1992  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1993  *  a specified device address.
1994  **/
1995 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1996                                            u8 dev_addr, u8 *data, bool lock)
1997 {
1998         s32 status;
1999         u32 max_retry = 10;
2000         u32 retry = 0;
2001         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2002         bool nack = 1;
2003         *data = 0;
2004
2005         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2006
2007         if (hw->mac.type >= ixgbe_mac_X550)
2008                 max_retry = 3;
2009         if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2010                 max_retry = IXGBE_SFP_DETECT_RETRIES;
2011
2012         do {
2013                 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2014                         return IXGBE_ERR_SWFW_SYNC;
2015
2016                 ixgbe_i2c_start(hw);
2017
2018                 /* Device Address and write indication */
2019                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2020                 if (status != IXGBE_SUCCESS)
2021                         goto fail;
2022
2023                 status = ixgbe_get_i2c_ack(hw);
2024                 if (status != IXGBE_SUCCESS)
2025                         goto fail;
2026
2027                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2028                 if (status != IXGBE_SUCCESS)
2029                         goto fail;
2030
2031                 status = ixgbe_get_i2c_ack(hw);
2032                 if (status != IXGBE_SUCCESS)
2033                         goto fail;
2034
2035                 ixgbe_i2c_start(hw);
2036
2037                 /* Device Address and read indication */
2038                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2039                 if (status != IXGBE_SUCCESS)
2040                         goto fail;
2041
2042                 status = ixgbe_get_i2c_ack(hw);
2043                 if (status != IXGBE_SUCCESS)
2044                         goto fail;
2045
2046                 status = ixgbe_clock_in_i2c_byte(hw, data);
2047                 if (status != IXGBE_SUCCESS)
2048                         goto fail;
2049
2050                 status = ixgbe_clock_out_i2c_bit(hw, nack);
2051                 if (status != IXGBE_SUCCESS)
2052                         goto fail;
2053
2054                 ixgbe_i2c_stop(hw);
2055                 if (lock)
2056                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2057                 return IXGBE_SUCCESS;
2058
2059 fail:
2060                 ixgbe_i2c_bus_clear(hw);
2061                 if (lock) {
2062                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2063                         msec_delay(100);
2064                 }
2065                 retry++;
2066                 if (retry < max_retry)
2067                         DEBUGOUT("I2C byte read error - Retrying.\n");
2068                 else
2069                         DEBUGOUT("I2C byte read error.\n");
2070
2071         } while (retry < max_retry);
2072
2073         return status;
2074 }
2075
2076 /**
2077  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2078  *  @hw: pointer to hardware structure
2079  *  @byte_offset: byte offset to read
2080  *  @data: value read
2081  *
2082  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2083  *  a specified device address.
2084  **/
2085 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2086                                 u8 dev_addr, u8 *data)
2087 {
2088         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2089                                                data, TRUE);
2090 }
2091
2092 /**
2093  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2094  *  @hw: pointer to hardware structure
2095  *  @byte_offset: byte offset to read
2096  *  @data: value read
2097  *
2098  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2099  *  a specified device address.
2100  **/
2101 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2102                                          u8 dev_addr, u8 *data)
2103 {
2104         return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2105                                                data, FALSE);
2106 }
2107
2108 /**
2109  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2110  *  @hw: pointer to hardware structure
2111  *  @byte_offset: byte offset to write
2112  *  @data: value to write
2113  *  @lock: TRUE if to take and release semaphore
2114  *
2115  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2116  *  a specified device address.
2117  **/
2118 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2119                                             u8 dev_addr, u8 data, bool lock)
2120 {
2121         s32 status;
2122         u32 max_retry = 1;
2123         u32 retry = 0;
2124         u32 swfw_mask = hw->phy.phy_semaphore_mask;
2125
2126         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2127
2128         if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2129             IXGBE_SUCCESS)
2130                 return IXGBE_ERR_SWFW_SYNC;
2131
2132         do {
2133                 ixgbe_i2c_start(hw);
2134
2135                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2136                 if (status != IXGBE_SUCCESS)
2137                         goto fail;
2138
2139                 status = ixgbe_get_i2c_ack(hw);
2140                 if (status != IXGBE_SUCCESS)
2141                         goto fail;
2142
2143                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2144                 if (status != IXGBE_SUCCESS)
2145                         goto fail;
2146
2147                 status = ixgbe_get_i2c_ack(hw);
2148                 if (status != IXGBE_SUCCESS)
2149                         goto fail;
2150
2151                 status = ixgbe_clock_out_i2c_byte(hw, data);
2152                 if (status != IXGBE_SUCCESS)
2153                         goto fail;
2154
2155                 status = ixgbe_get_i2c_ack(hw);
2156                 if (status != IXGBE_SUCCESS)
2157                         goto fail;
2158
2159                 ixgbe_i2c_stop(hw);
2160                 if (lock)
2161                         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2162                 return IXGBE_SUCCESS;
2163
2164 fail:
2165                 ixgbe_i2c_bus_clear(hw);
2166                 retry++;
2167                 if (retry < max_retry)
2168                         DEBUGOUT("I2C byte write error - Retrying.\n");
2169                 else
2170                         DEBUGOUT("I2C byte write error.\n");
2171         } while (retry < max_retry);
2172
2173         if (lock)
2174                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2175
2176         return status;
2177 }
2178
2179 /**
2180  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2181  *  @hw: pointer to hardware structure
2182  *  @byte_offset: byte offset to write
2183  *  @data: value to write
2184  *
2185  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2186  *  a specified device address.
2187  **/
2188 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2189                                  u8 dev_addr, u8 data)
2190 {
2191         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2192                                                 data, TRUE);
2193 }
2194
2195 /**
2196  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2197  *  @hw: pointer to hardware structure
2198  *  @byte_offset: byte offset to write
2199  *  @data: value to write
2200  *
2201  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2202  *  a specified device address.
2203  **/
2204 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2205                                           u8 dev_addr, u8 data)
2206 {
2207         return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2208                                                 data, FALSE);
2209 }
2210
2211 /**
2212  *  ixgbe_i2c_start - Sets I2C start condition
2213  *  @hw: pointer to hardware structure
2214  *
2215  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2216  *  Set bit-bang mode on X550 hardware.
2217  **/
2218 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2219 {
2220         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2221
2222         DEBUGFUNC("ixgbe_i2c_start");
2223
2224         i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2225
2226         /* Start condition must begin with data and clock high */
2227         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2228         ixgbe_raise_i2c_clk(hw, &i2cctl);
2229
2230         /* Setup time for start condition (4.7us) */
2231         usec_delay(IXGBE_I2C_T_SU_STA);
2232
2233         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2234
2235         /* Hold time for start condition (4us) */
2236         usec_delay(IXGBE_I2C_T_HD_STA);
2237
2238         ixgbe_lower_i2c_clk(hw, &i2cctl);
2239
2240         /* Minimum low period of clock is 4.7 us */
2241         usec_delay(IXGBE_I2C_T_LOW);
2242
2243 }
2244
2245 /**
2246  *  ixgbe_i2c_stop - Sets I2C stop condition
2247  *  @hw: pointer to hardware structure
2248  *
2249  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2250  *  Disables bit-bang mode and negates data output enable on X550
2251  *  hardware.
2252  **/
2253 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2254 {
2255         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2256         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2257         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2258         u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2259
2260         DEBUGFUNC("ixgbe_i2c_stop");
2261
2262         /* Stop condition must begin with data low and clock high */
2263         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2264         ixgbe_raise_i2c_clk(hw, &i2cctl);
2265
2266         /* Setup time for stop condition (4us) */
2267         usec_delay(IXGBE_I2C_T_SU_STO);
2268
2269         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2270
2271         /* bus free time between stop and start (4.7us)*/
2272         usec_delay(IXGBE_I2C_T_BUF);
2273
2274         if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2275                 i2cctl &= ~bb_en_bit;
2276                 i2cctl |= data_oe_bit | clk_oe_bit;
2277                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2278                 IXGBE_WRITE_FLUSH(hw);
2279         }
2280 }
2281
2282 /**
2283  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2284  *  @hw: pointer to hardware structure
2285  *  @data: data byte to clock in
2286  *
2287  *  Clocks in one byte data via I2C data/clock
2288  **/
2289 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2290 {
2291         s32 i;
2292         bool bit = 0;
2293
2294         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2295
2296         *data = 0;
2297         for (i = 7; i >= 0; i--) {
2298                 ixgbe_clock_in_i2c_bit(hw, &bit);
2299                 *data |= bit << i;
2300         }
2301
2302         return IXGBE_SUCCESS;
2303 }
2304
2305 /**
2306  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2307  *  @hw: pointer to hardware structure
2308  *  @data: data byte clocked out
2309  *
2310  *  Clocks out one byte data via I2C data/clock
2311  **/
2312 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2313 {
2314         s32 status = IXGBE_SUCCESS;
2315         s32 i;
2316         u32 i2cctl;
2317         bool bit;
2318
2319         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2320
2321         for (i = 7; i >= 0; i--) {
2322                 bit = (data >> i) & 0x1;
2323                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2324
2325                 if (status != IXGBE_SUCCESS)
2326                         break;
2327         }
2328
2329         /* Release SDA line (set high) */
2330         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2331         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2332         i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2333         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2334         IXGBE_WRITE_FLUSH(hw);
2335
2336         return status;
2337 }
2338
2339 /**
2340  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2341  *  @hw: pointer to hardware structure
2342  *
2343  *  Clocks in/out one bit via I2C data/clock
2344  **/
2345 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2346 {
2347         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2348         s32 status = IXGBE_SUCCESS;
2349         u32 i = 0;
2350         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2351         u32 timeout = 10;
2352         bool ack = 1;
2353
2354         DEBUGFUNC("ixgbe_get_i2c_ack");
2355
2356         if (data_oe_bit) {
2357                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2358                 i2cctl |= data_oe_bit;
2359                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2360                 IXGBE_WRITE_FLUSH(hw);
2361         }
2362         ixgbe_raise_i2c_clk(hw, &i2cctl);
2363
2364         /* Minimum high period of clock is 4us */
2365         usec_delay(IXGBE_I2C_T_HIGH);
2366
2367         /* Poll for ACK.  Note that ACK in I2C spec is
2368          * transition from 1 to 0 */
2369         for (i = 0; i < timeout; i++) {
2370                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2371                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2372
2373                 usec_delay(1);
2374                 if (!ack)
2375                         break;
2376         }
2377
2378         if (ack) {
2379                 DEBUGOUT("I2C ack was not received.\n");
2380                 status = IXGBE_ERR_I2C;
2381         }
2382
2383         ixgbe_lower_i2c_clk(hw, &i2cctl);
2384
2385         /* Minimum low period of clock is 4.7 us */
2386         usec_delay(IXGBE_I2C_T_LOW);
2387
2388         return status;
2389 }
2390
2391 /**
2392  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2393  *  @hw: pointer to hardware structure
2394  *  @data: read data value
2395  *
2396  *  Clocks in one bit via I2C data/clock
2397  **/
2398 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2399 {
2400         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2401         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2402
2403         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2404
2405         if (data_oe_bit) {
2406                 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2407                 i2cctl |= data_oe_bit;
2408                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2409                 IXGBE_WRITE_FLUSH(hw);
2410         }
2411         ixgbe_raise_i2c_clk(hw, &i2cctl);
2412
2413         /* Minimum high period of clock is 4us */
2414         usec_delay(IXGBE_I2C_T_HIGH);
2415
2416         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2417         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2418
2419         ixgbe_lower_i2c_clk(hw, &i2cctl);
2420
2421         /* Minimum low period of clock is 4.7 us */
2422         usec_delay(IXGBE_I2C_T_LOW);
2423
2424         return IXGBE_SUCCESS;
2425 }
2426
2427 /**
2428  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2429  *  @hw: pointer to hardware structure
2430  *  @data: data value to write
2431  *
2432  *  Clocks out one bit via I2C data/clock
2433  **/
2434 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2435 {
2436         s32 status;
2437         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2438
2439         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2440
2441         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2442         if (status == IXGBE_SUCCESS) {
2443                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2444
2445                 /* Minimum high period of clock is 4us */
2446                 usec_delay(IXGBE_I2C_T_HIGH);
2447
2448                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2449
2450                 /* Minimum low period of clock is 4.7 us.
2451                  * This also takes care of the data hold time.
2452                  */
2453                 usec_delay(IXGBE_I2C_T_LOW);
2454         } else {
2455                 status = IXGBE_ERR_I2C;
2456                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2457                              "I2C data was not set to %X\n", data);
2458         }
2459
2460         return status;
2461 }
2462
2463 /**
2464  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2465  *  @hw: pointer to hardware structure
2466  *  @i2cctl: Current value of I2CCTL register
2467  *
2468  *  Raises the I2C clock line '0'->'1'
2469  *  Negates the I2C clock output enable on X550 hardware.
2470  **/
2471 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2472 {
2473         u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2474         u32 i = 0;
2475         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2476         u32 i2cctl_r = 0;
2477
2478         DEBUGFUNC("ixgbe_raise_i2c_clk");
2479
2480         if (clk_oe_bit) {
2481                 *i2cctl |= clk_oe_bit;
2482                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2483         }
2484
2485         for (i = 0; i < timeout; i++) {
2486                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2487
2488                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2489                 IXGBE_WRITE_FLUSH(hw);
2490                 /* SCL rise time (1000ns) */
2491                 usec_delay(IXGBE_I2C_T_RISE);
2492
2493                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2494                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2495                         break;
2496         }
2497 }
2498
2499 /**
2500  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2501  *  @hw: pointer to hardware structure
2502  *  @i2cctl: Current value of I2CCTL register
2503  *
2504  *  Lowers the I2C clock line '1'->'0'
2505  *  Asserts the I2C clock output enable on X550 hardware.
2506  **/
2507 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2508 {
2509         DEBUGFUNC("ixgbe_lower_i2c_clk");
2510
2511         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2512         *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2513
2514         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2515         IXGBE_WRITE_FLUSH(hw);
2516
2517         /* SCL fall time (300ns) */
2518         usec_delay(IXGBE_I2C_T_FALL);
2519 }
2520
2521 /**
2522  *  ixgbe_set_i2c_data - Sets the I2C data bit
2523  *  @hw: pointer to hardware structure
2524  *  @i2cctl: Current value of I2CCTL register
2525  *  @data: I2C data value (0 or 1) to set
2526  *
2527  *  Sets the I2C data bit
2528  *  Asserts the I2C data output enable on X550 hardware.
2529  **/
2530 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2531 {
2532         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2533         s32 status = IXGBE_SUCCESS;
2534
2535         DEBUGFUNC("ixgbe_set_i2c_data");
2536
2537         if (data)
2538                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2539         else
2540                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2541         *i2cctl &= ~data_oe_bit;
2542
2543         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2544         IXGBE_WRITE_FLUSH(hw);
2545
2546         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2547         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2548
2549         if (!data)      /* Can't verify data in this case */
2550                 return IXGBE_SUCCESS;
2551         if (data_oe_bit) {
2552                 *i2cctl |= data_oe_bit;
2553                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2554                 IXGBE_WRITE_FLUSH(hw);
2555         }
2556
2557         /* Verify data was set correctly */
2558         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2559         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2560                 status = IXGBE_ERR_I2C;
2561                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2562                              "Error - I2C data was not set to %X.\n",
2563                              data);
2564         }
2565
2566         return status;
2567 }
2568
2569 /**
2570  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2571  *  @hw: pointer to hardware structure
2572  *  @i2cctl: Current value of I2CCTL register
2573  *
2574  *  Returns the I2C data bit value
2575  *  Negates the I2C data output enable on X550 hardware.
2576  **/
2577 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2578 {
2579         u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2580         bool data;
2581
2582         DEBUGFUNC("ixgbe_get_i2c_data");
2583
2584         if (data_oe_bit) {
2585                 *i2cctl |= data_oe_bit;
2586                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2587                 IXGBE_WRITE_FLUSH(hw);
2588                 usec_delay(IXGBE_I2C_T_FALL);
2589         }
2590
2591         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2592                 data = 1;
2593         else
2594                 data = 0;
2595
2596         return data;
2597 }
2598
2599 /**
2600  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2601  *  @hw: pointer to hardware structure
2602  *
2603  *  Clears the I2C bus by sending nine clock pulses.
2604  *  Used when data line is stuck low.
2605  **/
2606 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2607 {
2608         u32 i2cctl;
2609         u32 i;
2610
2611         DEBUGFUNC("ixgbe_i2c_bus_clear");
2612
2613         ixgbe_i2c_start(hw);
2614         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2615
2616         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2617
2618         for (i = 0; i < 9; i++) {
2619                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2620
2621                 /* Min high period of clock is 4us */
2622                 usec_delay(IXGBE_I2C_T_HIGH);
2623
2624                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2625
2626                 /* Min low period of clock is 4.7us*/
2627                 usec_delay(IXGBE_I2C_T_LOW);
2628         }
2629
2630         ixgbe_i2c_start(hw);
2631
2632         /* Put the i2c bus back to default state */
2633         ixgbe_i2c_stop(hw);
2634 }
2635
2636 /**
2637  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2638  *  @hw: pointer to hardware structure
2639  *
2640  *  Checks if the LASI temp alarm status was triggered due to overtemp
2641  **/
2642 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2643 {
2644         s32 status = IXGBE_SUCCESS;
2645         u16 phy_data = 0;
2646
2647         DEBUGFUNC("ixgbe_tn_check_overtemp");
2648
2649         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2650                 goto out;
2651
2652         /* Check that the LASI temp alarm status was triggered */
2653         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2654                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2655
2656         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2657                 goto out;
2658
2659         status = IXGBE_ERR_OVERTEMP;
2660         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2661 out:
2662         return status;
2663 }
2664
2665 /**
2666  * ixgbe_set_copper_phy_power - Control power for copper phy
2667  * @hw: pointer to hardware structure
2668  * @on: TRUE for on, FALSE for off
2669  */
2670 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2671 {
2672         u32 status;
2673         u16 reg;
2674
2675         if (!on && ixgbe_mng_present(hw))
2676                 return 0;
2677
2678         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2679                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2680                                       &reg);
2681         if (status)
2682                 return status;
2683
2684         if (on) {
2685                 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2686         } else {
2687                 if (ixgbe_check_reset_blocked(hw))
2688                         return 0;
2689                 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2690         }
2691
2692         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2693                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2694                                        reg);
2695         return status;
2696 }